1 /* Instruction printing code for the ARM 2 Copyright (C) 1994-2016 Free Software Foundation, Inc. 3 Contributed by Richard Earnshaw (rwe (at) pegasus.esprit.ec.org) 4 Modification by James G. Smith (jsmith (at) cygnus.co.uk) 5 6 This file is part of libopcodes. 7 8 This library is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 It is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23 #include "sysdep.h" 24 25 #include "dis-asm.h" 26 #include "opcode/arm.h" 27 #include "opintl.h" 28 #include "safe-ctype.h" 29 #include "floatformat.h" 30 31 /* FIXME: This shouldn't be done here. */ 32 #include "coff/internal.h" 33 #include "libcoff.h" 34 #include "elf-bfd.h" 35 #include "elf/internal.h" 36 #include "elf/arm.h" 37 #include "mach-o.h" 38 39 /* FIXME: Belongs in global header. */ 40 #ifndef strneq 41 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) 42 #endif 43 44 #ifndef NUM_ELEM 45 #define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) 46 #endif 47 48 /* Cached mapping symbol state. */ 49 enum map_type 50 { 51 MAP_ARM, 52 MAP_THUMB, 53 MAP_DATA 54 }; 55 56 struct arm_private_data 57 { 58 /* The features to use when disassembling optional instructions. */ 59 arm_feature_set features; 60 61 /* Whether any mapping symbols are present in the provided symbol 62 table. -1 if we do not know yet, otherwise 0 or 1. */ 63 int has_mapping_symbols; 64 65 /* Track the last type (although this doesn't seem to be useful) */ 66 enum map_type last_type; 67 68 /* Tracking symbol table information */ 69 int last_mapping_sym; 70 bfd_vma last_mapping_addr; 71 }; 72 73 struct opcode32 74 { 75 arm_feature_set arch; /* Architecture defining this insn. */ 76 unsigned long value; /* If arch is 0 then value is a sentinel. */ 77 unsigned long mask; /* Recognise insn if (op & mask) == value. */ 78 const char * assembler; /* How to disassemble this insn. */ 79 }; 80 81 struct opcode16 82 { 83 arm_feature_set arch; /* Architecture defining this insn. */ 84 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */ 85 const char *assembler; /* How to disassemble this insn. */ 86 }; 87 88 /* print_insn_coprocessor recognizes the following format control codes: 89 90 %% % 91 92 %c print condition code (always bits 28-31 in ARM mode) 93 %q print shifter argument 94 %u print condition code (unconditional in ARM mode, 95 UNPREDICTABLE if not AL in Thumb) 96 %A print address for ldc/stc/ldf/stf instruction 97 %B print vstm/vldm register list 98 %I print cirrus signed shift immediate: bits 0..3|4..6 99 %F print the COUNT field of a LFM/SFM instruction. 100 %P print floating point precision in arithmetic insn 101 %Q print floating point precision in ldf/stf insn 102 %R print floating point rounding mode 103 104 %<bitfield>c print as a condition code (for vsel) 105 %<bitfield>r print as an ARM register 106 %<bitfield>R as %<>r but r15 is UNPREDICTABLE 107 %<bitfield>ru as %<>r but each u register must be unique. 108 %<bitfield>d print the bitfield in decimal 109 %<bitfield>k print immediate for VFPv3 conversion instruction 110 %<bitfield>x print the bitfield in hex 111 %<bitfield>X print the bitfield as 1 hex digit without leading "0x" 112 %<bitfield>f print a floating point constant if >7 else a 113 floating point register 114 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us 115 %<bitfield>g print as an iWMMXt 64-bit register 116 %<bitfield>G print as an iWMMXt general purpose or control register 117 %<bitfield>D print as a NEON D register 118 %<bitfield>Q print as a NEON Q register 119 %<bitfield>E print a quarter-float immediate value 120 121 %y<code> print a single precision VFP reg. 122 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair 123 %z<code> print a double precision VFP reg 124 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list 125 126 %<bitfield>'c print specified char iff bitfield is all ones 127 %<bitfield>`c print specified char iff bitfield is all zeroes 128 %<bitfield>?ab... select from array of values in big endian order 129 130 %L print as an iWMMXt N/M width field. 131 %Z print the Immediate of a WSHUFH instruction. 132 %l like 'A' except use byte offsets for 'B' & 'H' 133 versions. 134 %i print 5-bit immediate in bits 8,3..0 135 (print "32" when 0) 136 %r print register offset address for wldt/wstr instruction. */ 137 138 enum opcode_sentinel_enum 139 { 140 SENTINEL_IWMMXT_START = 1, 141 SENTINEL_IWMMXT_END, 142 SENTINEL_GENERIC_START 143 } opcode_sentinels; 144 145 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x" 146 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>" 147 148 /* Common coprocessor opcodes shared between Arm and Thumb-2. */ 149 150 static const struct opcode32 coprocessor_opcodes[] = 151 { 152 /* XScale instructions. */ 153 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 154 0x0e200010, 0x0fff0ff0, 155 "mia%c\tacc0, %0-3r, %12-15r"}, 156 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 157 0x0e280010, 0x0fff0ff0, 158 "miaph%c\tacc0, %0-3r, %12-15r"}, 159 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 160 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"}, 161 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 162 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"}, 163 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 164 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"}, 165 166 /* Intel Wireless MMX technology instructions. */ 167 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" }, 168 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), 169 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"}, 170 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 171 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"}, 172 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 173 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"}, 174 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 175 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"}, 176 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 177 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"}, 178 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 179 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"}, 180 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 181 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"}, 182 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 183 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"}, 184 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 185 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"}, 186 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 187 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"}, 188 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 189 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"}, 190 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 191 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"}, 192 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 193 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"}, 194 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 195 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"}, 196 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 197 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"}, 198 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 199 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"}, 200 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 201 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"}, 202 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 203 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 204 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 205 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"}, 206 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 207 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"}, 208 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 209 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"}, 210 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 211 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"}, 212 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 213 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"}, 214 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 215 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"}, 216 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 217 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"}, 218 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 219 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 220 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 221 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 222 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 223 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"}, 224 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 225 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"}, 226 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 227 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"}, 228 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 229 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"}, 230 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 231 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"}, 232 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 233 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"}, 234 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 235 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 236 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 237 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"}, 238 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 239 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 240 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 241 0x0e800120, 0x0f800ff0, 242 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 243 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 244 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 245 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 246 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"}, 247 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 248 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"}, 249 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 250 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"}, 251 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 252 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"}, 253 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 254 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"}, 255 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 256 0x0e8000a0, 0x0f800ff0, 257 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 258 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 259 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"}, 260 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 261 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"}, 262 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 263 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"}, 264 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 265 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 266 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 267 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"}, 268 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 269 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 270 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 271 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"}, 272 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 273 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"}, 274 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 275 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"}, 276 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 277 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"}, 278 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 279 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 280 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 281 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 282 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 283 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"}, 284 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 285 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 286 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 287 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 288 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 289 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"}, 290 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 291 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 292 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 293 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 294 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 295 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"}, 296 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 297 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"}, 298 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 299 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"}, 300 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 301 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 302 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 303 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"}, 304 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 305 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 306 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 307 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"}, 308 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 309 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"}, 310 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 311 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"}, 312 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 313 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"}, 314 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 315 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 316 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 317 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 318 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 319 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"}, 320 {ARM_FEATURE_CORE_LOW (0), 321 SENTINEL_IWMMXT_END, 0, "" }, 322 323 /* Floating point coprocessor (FPA) instructions. */ 324 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 325 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 326 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 327 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 328 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 329 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 330 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 331 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 332 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 333 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 334 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 335 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 336 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 337 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, 338 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 339 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, 340 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 341 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 342 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 343 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, 344 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 345 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, 346 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 347 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, 348 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 349 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, 350 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 351 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, 352 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 353 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, 354 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 355 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, 356 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 357 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, 358 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 359 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, 360 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 361 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, 362 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 363 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, 364 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 365 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, 366 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 367 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, 368 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 369 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, 370 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 371 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, 372 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 373 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, 374 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 375 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, 376 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 377 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, 378 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 379 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, 380 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 381 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, 382 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 383 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, 384 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 385 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, 386 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 387 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, 388 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 389 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, 390 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 391 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, 392 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 393 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, 394 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 395 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, 396 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 397 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, 398 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 399 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, 400 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 401 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, 402 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 403 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, 404 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 405 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, 406 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2), 407 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, 408 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2), 409 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, 410 411 /* ARMv8-M Mainline Security Extensions instructions. */ 412 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN), 413 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"}, 414 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN), 415 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"}, 416 417 /* Register load/store. */ 418 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 419 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"}, 420 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 421 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"}, 422 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 423 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"}, 424 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 425 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"}, 426 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 427 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"}, 428 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 429 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"}, 430 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 431 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"}, 432 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 433 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"}, 434 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 435 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"}, 436 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 437 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"}, 438 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 439 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"}, 440 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 441 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"}, 442 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 443 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"}, 444 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 445 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"}, 446 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 447 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"}, 448 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 449 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"}, 450 451 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 452 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, 453 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 454 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, 455 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 456 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, 457 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 458 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, 459 460 /* Data transfer between ARM and NEON registers. */ 461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 462 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"}, 463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 464 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"}, 465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 466 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"}, 467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 468 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"}, 469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 470 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"}, 471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 472 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"}, 473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 474 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"}, 475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 476 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"}, 477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 478 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"}, 479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 480 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"}, 481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 482 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"}, 483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 484 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"}, 485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 486 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"}, 487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 488 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"}, 489 /* Half-precision conversion instructions. */ 490 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 491 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"}, 492 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 493 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"}, 494 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 495 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"}, 496 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 497 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"}, 498 499 /* Floating point coprocessor (VFP) instructions. */ 500 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 501 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"}, 502 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 503 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"}, 504 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 505 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"}, 506 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 507 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"}, 508 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 509 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"}, 510 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 511 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"}, 512 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 513 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"}, 514 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 515 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"}, 516 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 517 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"}, 518 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 519 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"}, 520 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 521 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"}, 522 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 523 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"}, 524 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 525 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"}, 526 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 527 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"}, 528 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 529 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"}, 530 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 531 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"}, 532 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 533 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"}, 534 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 535 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"}, 536 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 537 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"}, 538 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 539 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"}, 540 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 541 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"}, 542 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 543 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"}, 544 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 545 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"}, 546 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 547 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"}, 548 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 549 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"}, 550 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 551 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"}, 552 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 553 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"}, 554 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 555 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"}, 556 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 557 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"}, 558 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 559 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"}, 560 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 561 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"}, 562 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 563 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"}, 564 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 565 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"}, 566 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 567 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"}, 568 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 569 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"}, 570 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 571 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"}, 572 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 573 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"}, 574 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 575 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"}, 576 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 577 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"}, 578 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 579 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"}, 580 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 581 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"}, 582 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 583 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"}, 584 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 585 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"}, 586 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 587 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"}, 588 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 589 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"}, 590 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 591 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"}, 592 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 593 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"}, 594 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 595 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"}, 596 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 597 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"}, 598 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 599 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"}, 600 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 601 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"}, 602 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 603 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"}, 604 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 605 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"}, 606 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 607 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"}, 608 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 609 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"}, 610 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 611 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"}, 612 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 613 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"}, 614 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 615 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"}, 616 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 617 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"}, 618 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 619 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"}, 620 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 621 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"}, 622 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 623 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"}, 624 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 625 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"}, 626 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 627 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"}, 628 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 629 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"}, 630 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 631 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"}, 632 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 633 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"}, 634 635 /* Cirrus coprocessor instructions. */ 636 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 637 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, 638 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 639 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, 640 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 641 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, 642 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 643 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, 644 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 645 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, 646 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 647 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, 648 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 649 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, 650 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 651 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, 652 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 653 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, 654 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 655 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, 656 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 657 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, 658 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 659 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, 660 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 661 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, 662 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 663 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, 664 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 665 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, 666 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 667 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, 668 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 669 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"}, 670 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 671 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"}, 672 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 673 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"}, 674 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 675 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"}, 676 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 677 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"}, 678 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 679 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"}, 680 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 681 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"}, 682 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 683 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"}, 684 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 685 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"}, 686 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 687 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"}, 688 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 689 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"}, 690 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 691 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"}, 692 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 693 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"}, 694 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 695 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"}, 696 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 697 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"}, 698 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 699 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"}, 700 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 701 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"}, 702 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 703 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"}, 704 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 705 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"}, 706 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 707 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"}, 708 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 709 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"}, 710 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 711 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"}, 712 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 713 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"}, 714 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 715 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"}, 716 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 717 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"}, 718 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 719 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"}, 720 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 721 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"}, 722 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 723 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"}, 724 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 725 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"}, 726 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 727 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"}, 728 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 729 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"}, 730 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 731 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"}, 732 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 733 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"}, 734 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 735 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"}, 736 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 737 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"}, 738 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 739 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"}, 740 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 741 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"}, 742 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 743 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"}, 744 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 745 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"}, 746 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 747 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"}, 748 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 749 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"}, 750 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 751 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"}, 752 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 753 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"}, 754 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 755 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"}, 756 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 757 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"}, 758 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 759 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"}, 760 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 761 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 762 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 763 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 764 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 765 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 766 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 767 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 768 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 769 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 770 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 771 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 772 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 773 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"}, 774 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 775 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"}, 776 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 777 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"}, 778 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 779 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"}, 780 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 781 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 782 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 783 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 784 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 785 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 786 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 787 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 788 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 789 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 790 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 791 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 792 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 793 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 794 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 795 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 796 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 797 0x0e000600, 0x0ff00f10, 798 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 799 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 800 0x0e100600, 0x0ff00f10, 801 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 802 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 803 0x0e200600, 0x0ff00f10, 804 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, 805 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 806 0x0e300600, 0x0ff00f10, 807 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, 808 809 /* VFP Fused multiply add instructions. */ 810 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 811 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"}, 812 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 813 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"}, 814 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 815 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"}, 816 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 817 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"}, 818 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 819 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"}, 820 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 821 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"}, 822 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 823 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"}, 824 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 825 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"}, 826 827 /* FP v5. */ 828 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 829 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"}, 830 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 831 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"}, 832 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 833 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"}, 834 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 835 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"}, 836 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 837 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"}, 838 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 839 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"}, 840 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 841 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"}, 842 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 843 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"}, 844 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 845 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"}, 846 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 847 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"}, 848 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 849 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"}, 850 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 851 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"}, 852 853 /* Generic coprocessor instructions. */ 854 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" }, 855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 856 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"}, 857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 858 0x0c500000, 0x0ff00000, 859 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, 860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 861 0x0e000000, 0x0f000010, 862 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, 863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 864 0x0e10f010, 0x0f10f010, 865 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"}, 866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 867 0x0e100010, 0x0f100010, 868 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 870 0x0e000010, 0x0f100010, 871 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, 872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 873 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"}, 874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 875 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"}, 876 877 /* V6 coprocessor instructions. */ 878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 879 0xfc500000, 0xfff00000, 880 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, 881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 882 0xfc400000, 0xfff00000, 883 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"}, 884 885 /* V5 coprocessor instructions. */ 886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 887 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"}, 888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 889 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"}, 890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 891 0xfe000000, 0xff000010, 892 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, 893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 894 0xfe000010, 0xff100010, 895 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, 896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 897 0xfe100010, 0xff100010, 898 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 899 900 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions. 901 cp_num: bit <11:8> == 0b1001. 902 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */ 903 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 904 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"}, 905 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 906 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"}, 907 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 908 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"}, 909 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 910 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"}, 911 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 912 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"}, 913 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 914 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"}, 915 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 916 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"}, 917 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 918 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"}, 919 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 920 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"}, 921 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 922 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"}, 923 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 924 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"}, 925 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 926 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"}, 927 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 928 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"}, 929 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 930 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"}, 931 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 932 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"}, 933 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 934 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"}, 935 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 936 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"}, 937 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 938 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"}, 939 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 940 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"}, 941 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 942 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"}, 943 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 944 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"}, 945 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 946 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"}, 947 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 948 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"}, 949 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 950 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"}, 951 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 952 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"}, 953 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 954 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"}, 955 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 956 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"}, 957 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 958 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"}, 959 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 960 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"}, 961 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 962 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"}, 963 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 964 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"}, 965 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 966 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"}, 967 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 968 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"}, 969 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 970 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"}, 971 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 972 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"}, 973 974 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 975 }; 976 977 /* Neon opcode table: This does not encode the top byte -- that is 978 checked by the print_insn_neon routine, as it depends on whether we are 979 doing thumb32 or arm32 disassembly. */ 980 981 /* print_insn_neon recognizes the following format control codes: 982 983 %% % 984 985 %c print condition code 986 %u print condition code (unconditional in ARM mode, 987 UNPREDICTABLE if not AL in Thumb) 988 %A print v{st,ld}[1234] operands 989 %B print v{st,ld}[1234] any one operands 990 %C print v{st,ld}[1234] single->all operands 991 %D print scalar 992 %E print vmov, vmvn, vorr, vbic encoded constant 993 %F print vtbl,vtbx register list 994 995 %<bitfield>r print as an ARM register 996 %<bitfield>d print the bitfield in decimal 997 %<bitfield>e print the 2^N - bitfield in decimal 998 %<bitfield>D print as a NEON D register 999 %<bitfield>Q print as a NEON Q register 1000 %<bitfield>R print as a NEON D or Q register 1001 %<bitfield>Sn print byte scaled width limited by n 1002 %<bitfield>Tn print short scaled width limited by n 1003 %<bitfield>Un print long scaled width limited by n 1004 1005 %<bitfield>'c print specified char iff bitfield is all ones 1006 %<bitfield>`c print specified char iff bitfield is all zeroes 1007 %<bitfield>?ab... select from array of values in big endian order. */ 1008 1009 static const struct opcode32 neon_opcodes[] = 1010 { 1011 /* Extract. */ 1012 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1013 0xf2b00840, 0xffb00850, 1014 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, 1015 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1016 0xf2b00000, 0xffb00810, 1017 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, 1018 1019 /* Move data element to all lanes. */ 1020 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1021 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"}, 1022 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1023 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"}, 1024 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1025 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"}, 1026 1027 /* Table lookup. */ 1028 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1029 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"}, 1030 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1031 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"}, 1032 1033 /* Half-precision conversions. */ 1034 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 1035 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"}, 1036 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 1037 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"}, 1038 1039 /* NEON fused multiply add instructions. */ 1040 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), 1041 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1042 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1043 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1044 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), 1045 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1046 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1047 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1048 1049 /* Two registers, miscellaneous. */ 1050 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1051 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"}, 1052 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1053 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"}, 1054 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1055 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"}, 1056 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1057 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"}, 1058 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1059 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"}, 1060 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1061 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"}, 1062 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1063 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"}, 1064 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1065 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"}, 1066 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1067 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"}, 1068 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1069 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"}, 1070 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1071 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"}, 1072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1073 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"}, 1074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1075 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"}, 1076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1077 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"}, 1078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1079 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"}, 1080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1081 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"}, 1082 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1083 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"}, 1084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1085 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"}, 1086 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1087 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, 1088 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1089 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, 1090 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1091 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"}, 1092 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1093 0xf3b20300, 0xffb30fd0, 1094 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"}, 1095 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1096 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, 1097 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1098 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"}, 1099 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1100 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, 1101 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1102 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"}, 1103 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1104 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1105 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1106 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1107 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1108 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1109 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1110 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1111 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1112 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"}, 1113 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1114 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1115 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1116 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1117 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1118 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1119 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1120 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1121 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1122 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1123 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1124 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1125 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1126 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1127 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1128 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1129 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1130 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1131 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1132 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1133 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1134 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, 1135 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1136 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, 1137 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1138 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, 1139 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1140 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, 1141 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1142 0xf3bb0600, 0xffbf0e10, 1143 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"}, 1144 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1145 0xf3b70600, 0xffbf0e10, 1146 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"}, 1147 1148 /* Three registers of the same length. */ 1149 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1150 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1151 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1152 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1153 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1154 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1155 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1156 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1157 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1158 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1159 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1160 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1161 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1162 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1163 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1164 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1165 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1166 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1167 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1168 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1169 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1170 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1171 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1172 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1173 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1174 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1175 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1176 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1177 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1178 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1179 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1180 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1181 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1182 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1183 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1184 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1185 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1186 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1187 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1188 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1189 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1190 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1191 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1192 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1193 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1194 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1195 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1196 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1197 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1198 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1199 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1200 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1201 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1202 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1203 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1204 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1205 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1206 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1207 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1208 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1209 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1210 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1211 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1212 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1213 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1214 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1215 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1216 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1217 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1218 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1219 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1220 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1221 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1222 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1223 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1224 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1225 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1226 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1227 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1228 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1229 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1230 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1231 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1232 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1233 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1234 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1235 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1236 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1237 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1238 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1239 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1240 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1241 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1242 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1243 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1244 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1245 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1246 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1247 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1248 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1249 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1250 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1251 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1252 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1253 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1254 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1255 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1256 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1257 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1258 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1259 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1260 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1261 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1262 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1263 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1264 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1265 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1266 0xf2000b00, 0xff800f10, 1267 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1268 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1269 0xf2000b10, 0xff800f10, 1270 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1271 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1272 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1273 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1274 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1275 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1276 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1277 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1278 0xf3000b00, 0xff800f10, 1279 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1280 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1281 0xf2000000, 0xfe800f10, 1282 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1283 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1284 0xf2000010, 0xfe800f10, 1285 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1286 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1287 0xf2000100, 0xfe800f10, 1288 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1289 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1290 0xf2000200, 0xfe800f10, 1291 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1292 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1293 0xf2000210, 0xfe800f10, 1294 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1295 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1296 0xf2000300, 0xfe800f10, 1297 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1298 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1299 0xf2000310, 0xfe800f10, 1300 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1301 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1302 0xf2000400, 0xfe800f10, 1303 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1304 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1305 0xf2000410, 0xfe800f10, 1306 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1307 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1308 0xf2000500, 0xfe800f10, 1309 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1310 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1311 0xf2000510, 0xfe800f10, 1312 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1313 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1314 0xf2000600, 0xfe800f10, 1315 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1316 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1317 0xf2000610, 0xfe800f10, 1318 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1319 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1320 0xf2000700, 0xfe800f10, 1321 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1322 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1323 0xf2000710, 0xfe800f10, 1324 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1325 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1326 0xf2000910, 0xfe800f10, 1327 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1328 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1329 0xf2000a00, 0xfe800f10, 1330 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1331 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1332 0xf2000a10, 0xfe800f10, 1333 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1334 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1335 0xf3000b10, 0xff800f10, 1336 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1337 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1338 0xf3000c10, 0xff800f10, 1339 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1340 1341 /* One register and an immediate value. */ 1342 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1343 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"}, 1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1345 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"}, 1346 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1347 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"}, 1348 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1349 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"}, 1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1351 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"}, 1352 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1353 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"}, 1354 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1355 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"}, 1356 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1357 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"}, 1358 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1359 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"}, 1360 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1361 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"}, 1362 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1363 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"}, 1364 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1365 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"}, 1366 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1367 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"}, 1368 1369 /* Two registers and a shift amount. */ 1370 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1371 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1372 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1373 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1374 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1375 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1376 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1377 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1378 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1379 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1380 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1381 0xf2880950, 0xfeb80fd0, 1382 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1383 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1384 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"}, 1385 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1386 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1387 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1388 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1389 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1390 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1391 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1392 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1393 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1394 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1395 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1396 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1397 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1398 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1399 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1400 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1401 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1402 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1403 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1404 0xf2900950, 0xfeb00fd0, 1405 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1407 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"}, 1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1409 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1411 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1413 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1415 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1416 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1417 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1419 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1421 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1423 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1424 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1425 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1427 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1429 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1430 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1431 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"}, 1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1433 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1434 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1435 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1436 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1437 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1439 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1440 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1441 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1443 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1444 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1445 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1446 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1447 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1448 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1449 0xf2a00950, 0xfea00fd0, 1450 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1452 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1453 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1454 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1456 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1458 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1460 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1462 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1464 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1466 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1468 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1470 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1472 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1474 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1476 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1478 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1480 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1482 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1484 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1486 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1488 0xf2a00e10, 0xfea00e90, 1489 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1490 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1491 0xf2a00c10, 0xfea00e90, 1492 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"}, 1493 1494 /* Three registers of different lengths. */ 1495 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1496 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1498 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1500 0xf2800400, 0xff800f50, 1501 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1502 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1503 0xf2800600, 0xff800f50, 1504 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1506 0xf2800900, 0xff800f50, 1507 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1508 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1509 0xf2800b00, 0xff800f50, 1510 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1512 0xf2800d00, 0xff800f50, 1513 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1514 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1515 0xf3800400, 0xff800f50, 1516 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1518 0xf3800600, 0xff800f50, 1519 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1520 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1521 0xf2800000, 0xfe800f50, 1522 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1523 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1524 0xf2800100, 0xfe800f50, 1525 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, 1526 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1527 0xf2800200, 0xfe800f50, 1528 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1530 0xf2800300, 0xfe800f50, 1531 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, 1532 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1533 0xf2800500, 0xfe800f50, 1534 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1536 0xf2800700, 0xfe800f50, 1537 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1539 0xf2800800, 0xfe800f50, 1540 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1541 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1542 0xf2800a00, 0xfe800f50, 1543 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1544 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1545 0xf2800c00, 0xfe800f50, 1546 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1547 1548 /* Two registers and a scalar. */ 1549 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1550 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1552 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, 1553 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1554 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"}, 1555 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1556 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1558 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1559 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1560 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1561 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1562 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"}, 1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1564 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1565 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1566 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1567 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1568 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, 1569 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1570 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"}, 1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1572 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1573 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1574 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1576 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1577 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1578 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1579 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1580 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 1581 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1582 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1584 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1586 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 1587 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1588 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1590 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1591 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1592 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 1593 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1594 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 1595 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1596 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1597 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1598 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1600 0xf2800240, 0xfe800f50, 1601 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1603 0xf2800640, 0xfe800f50, 1604 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1606 0xf2800a40, 0xfe800f50, 1607 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1609 0xf2800e40, 0xff800f50, 1610 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1611 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1612 0xf2800f40, 0xff800f50, 1613 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1615 0xf3800e40, 0xff800f50, 1616 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1618 0xf3800f40, 0xff800f50, 1619 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D" 1620 }, 1621 1622 /* Element and structure load/store. */ 1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1624 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"}, 1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1626 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"}, 1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1628 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"}, 1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1630 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"}, 1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1632 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"}, 1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1634 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1636 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1638 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, 1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1640 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, 1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1642 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1644 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1646 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 1647 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1648 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1650 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1652 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"}, 1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1654 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"}, 1655 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1656 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"}, 1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1658 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"}, 1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1660 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"}, 1661 1662 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0} 1663 }; 1664 1665 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially 1666 ordered: they must be searched linearly from the top to obtain a correct 1667 match. */ 1668 1669 /* print_insn_arm recognizes the following format control codes: 1670 1671 %% % 1672 1673 %a print address for ldr/str instruction 1674 %s print address for ldr/str halfword/signextend instruction 1675 %S like %s but allow UNPREDICTABLE addressing 1676 %b print branch destination 1677 %c print condition code (always bits 28-31) 1678 %m print register mask for ldm/stm instruction 1679 %o print operand2 (immediate or register + shift) 1680 %p print 'p' iff bits 12-15 are 15 1681 %t print 't' iff bit 21 set and bit 24 clear 1682 %B print arm BLX(1) destination 1683 %C print the PSR sub type. 1684 %U print barrier type. 1685 %P print address for pli instruction. 1686 1687 %<bitfield>r print as an ARM register 1688 %<bitfield>T print as an ARM register + 1 1689 %<bitfield>R as %r but r15 is UNPREDICTABLE 1690 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE 1691 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE 1692 %<bitfield>d print the bitfield in decimal 1693 %<bitfield>W print the bitfield plus one in decimal 1694 %<bitfield>x print the bitfield in hex 1695 %<bitfield>X print the bitfield as 1 hex digit without leading "0x" 1696 1697 %<bitfield>'c print specified char iff bitfield is all ones 1698 %<bitfield>`c print specified char iff bitfield is all zeroes 1699 %<bitfield>?ab... select from array of values in big endian order 1700 1701 %e print arm SMI operand (bits 0..7,8..19). 1702 %E print the LSB and WIDTH fields of a BFI or BFC instruction. 1703 %V print the 16-bit immediate field of a MOVT or MOVW instruction. 1704 %R print the SPSR/CPSR or banked register of an MRS. */ 1705 1706 static const struct opcode32 arm_opcodes[] = 1707 { 1708 /* ARM instructions. */ 1709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 1710 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"}, 1711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 1712 0xe7f000f0, 0xfff000f0, "udf\t#%e"}, 1713 1714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5), 1715 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, 1716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1717 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"}, 1718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1719 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 1720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S), 1721 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"}, 1722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M), 1723 0x00800090, 0x0fa000f0, 1724 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 1725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M), 1726 0x00a00090, 0x0fa000f0, 1727 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 1728 1729 /* V8.2 RAS extension instructions. */ 1730 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), 1731 0xe320f010, 0xffffffff, "esb"}, 1732 1733 /* V8 instructions. */ 1734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 1735 0x0320f005, 0x0fffffff, "sevl"}, 1736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 1737 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"}, 1738 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS), 1739 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"}, 1740 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1741 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, 1742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 1743 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"}, 1744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 1745 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"}, 1746 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1747 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"}, 1748 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1749 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, 1750 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1751 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"}, 1752 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1753 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, 1754 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1755 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"}, 1756 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1757 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"}, 1758 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1759 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"}, 1760 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1761 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"}, 1762 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1763 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"}, 1764 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1765 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"}, 1766 /* CRC32 instructions. */ 1767 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1768 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"}, 1769 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1770 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"}, 1771 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1772 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"}, 1773 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1774 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"}, 1775 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1776 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"}, 1777 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1778 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"}, 1779 1780 /* Privileged Access Never extension instructions. */ 1781 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 1782 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"}, 1783 1784 /* Virtualization Extension instructions. */ 1785 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"}, 1786 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"}, 1787 1788 /* Integer Divide Extension instructions. */ 1789 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), 1790 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"}, 1791 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), 1792 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"}, 1793 1794 /* MP Extension instructions. */ 1795 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"}, 1796 1797 /* V7 instructions. */ 1798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"}, 1799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"}, 1800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"}, 1801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"}, 1802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"}, 1803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"}, 1804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"}, 1805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 1806 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"}, 1807 1808 /* ARM V6T2 instructions. */ 1809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1810 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"}, 1811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1812 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"}, 1813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1814 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 1815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1816 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"}, 1817 1818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1819 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION }, 1820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1821 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"}, 1822 1823 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 1824 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"}, 1825 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 1826 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"}, 1827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1828 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"}, 1829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1830 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"}, 1831 1832 /* ARM Security extension instructions. */ 1833 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 1834 0x01600070, 0x0ff000f0, "smc%c\t%e"}, 1835 1836 /* ARM V6K instructions. */ 1837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1838 0xf57ff01f, 0xffffffff, "clrex"}, 1839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1840 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"}, 1841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1842 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"}, 1843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1844 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"}, 1845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1846 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"}, 1847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1848 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"}, 1849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1850 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"}, 1851 1852 /* ARM V6K NOP hints. */ 1853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1854 0x0320f001, 0x0fffffff, "yield%c"}, 1855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1856 0x0320f002, 0x0fffffff, "wfe%c"}, 1857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1858 0x0320f003, 0x0fffffff, "wfi%c"}, 1859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1860 0x0320f004, 0x0fffffff, "sev%c"}, 1861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1862 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"}, 1863 1864 /* ARM V6 instructions. */ 1865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1866 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"}, 1867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1868 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"}, 1869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1870 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"}, 1871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1872 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"}, 1873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1874 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"}, 1875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1876 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"}, 1877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1878 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"}, 1879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1880 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"}, 1881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1882 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"}, 1883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1884 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"}, 1885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1886 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"}, 1887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1888 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"}, 1889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1890 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"}, 1891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1892 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"}, 1893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1894 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"}, 1895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1896 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"}, 1897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1898 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"}, 1899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1900 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"}, 1901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1902 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"}, 1903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1904 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"}, 1905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1906 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"}, 1907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1908 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"}, 1909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1910 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"}, 1911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1912 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"}, 1913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1914 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"}, 1915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1916 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"}, 1917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1918 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"}, 1919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1920 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"}, 1921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1922 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"}, 1923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1924 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"}, 1925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1926 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"}, 1927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1928 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"}, 1929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1930 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"}, 1931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1932 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"}, 1933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1934 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"}, 1935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1936 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"}, 1937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1938 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"}, 1939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1940 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"}, 1941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1942 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"}, 1943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1944 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"}, 1945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1946 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"}, 1947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1948 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"}, 1949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1950 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"}, 1951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1952 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"}, 1953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1954 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"}, 1955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1956 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"}, 1957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1958 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"}, 1959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1960 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"}, 1961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1962 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"}, 1963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1964 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"}, 1965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1966 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"}, 1967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1968 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"}, 1969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1970 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"}, 1971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1972 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"}, 1973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1974 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"}, 1975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1976 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"}, 1977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1978 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"}, 1979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1980 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"}, 1981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1982 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"}, 1983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1984 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"}, 1985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1986 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"}, 1987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1988 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"}, 1989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1990 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"}, 1991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1992 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"}, 1993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1994 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"}, 1995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1996 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"}, 1997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1998 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"}, 1999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2000 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"}, 2001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2002 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"}, 2003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2004 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"}, 2005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2006 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"}, 2007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2008 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"}, 2009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2010 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"}, 2011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2012 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"}, 2013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2014 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"}, 2015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2016 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2018 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2020 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 2021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2022 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"}, 2023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2024 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2026 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2028 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 2029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2030 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"}, 2031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2032 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2034 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2036 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 2037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2038 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"}, 2039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2040 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2042 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2044 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 2045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2046 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"}, 2047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2048 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2050 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2052 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"}, 2053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2054 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"}, 2055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2056 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2058 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2060 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 2061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2062 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"}, 2063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2064 0xf1010000, 0xfffffc00, "setend\t%9?ble"}, 2065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2066 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"}, 2067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2068 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"}, 2069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2070 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2072 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2074 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2076 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2078 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"}, 2079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2080 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2082 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2084 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"}, 2085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2086 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"}, 2087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2088 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"}, 2089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2090 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"}, 2091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2092 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"}, 2093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2094 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"}, 2095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2096 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"}, 2097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2098 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"}, 2099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2100 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2102 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"}, 2103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2104 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"}, 2105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2106 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"}, 2107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2108 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"}, 2109 2110 /* V5J instruction. */ 2111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J), 2112 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"}, 2113 2114 /* V5 Instructions. */ 2115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 2116 0xe1200070, 0xfff000f0, 2117 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"}, 2118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 2119 0xfa000000, 0xfe000000, "blx\t%B"}, 2120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 2121 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"}, 2122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 2123 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"}, 2124 2125 /* V5E "El Segundo" Instructions. */ 2126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 2127 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"}, 2128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 2129 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"}, 2130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 2131 0xf450f000, 0xfc70f000, "pld\t%a"}, 2132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2133 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2135 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2137 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2139 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"}, 2140 2141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2142 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2144 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"}, 2145 2146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2147 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2149 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2151 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2153 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2154 2155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2156 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"}, 2157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2158 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"}, 2159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2160 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"}, 2161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2162 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"}, 2163 2164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2165 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"}, 2166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2167 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"}, 2168 2169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2170 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"}, 2171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2172 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"}, 2173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2174 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"}, 2175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2176 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"}, 2177 2178 /* ARM Instructions. */ 2179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2180 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"}, 2181 2182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2183 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"}, 2184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2185 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"}, 2186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2187 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"}, 2188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2189 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"}, 2190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2191 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"}, 2192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2193 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"}, 2194 2195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2196 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"}, 2197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2198 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"}, 2199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2200 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"}, 2201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2202 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"}, 2203 2204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2205 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION}, 2206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2207 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"}, 2208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2209 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION}, 2210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2211 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"}, 2212 2213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2214 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"}, 2215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2216 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"}, 2217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2218 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"}, 2219 2220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2221 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"}, 2222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2223 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"}, 2224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2225 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"}, 2226 2227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2228 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"}, 2229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2230 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"}, 2231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2232 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"}, 2233 2234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2235 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"}, 2236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2237 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"}, 2238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2239 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"}, 2240 2241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2242 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"}, 2243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2244 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"}, 2245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2246 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"}, 2247 2248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2249 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"}, 2250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2251 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"}, 2252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2253 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"}, 2254 2255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2256 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"}, 2257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2258 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"}, 2259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2260 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"}, 2261 2262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2263 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"}, 2264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2265 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"}, 2266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2267 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"}, 2268 2269 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 2270 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"}, 2271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 2272 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"}, 2273 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 2274 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"}, 2275 2276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2277 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"}, 2278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2279 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"}, 2280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2281 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"}, 2282 2283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2284 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"}, 2285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2286 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"}, 2287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2288 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"}, 2289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 2290 0x0130f000, 0x0ff0f010, "bx%c\t%0-3r"}, 2291 2292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2293 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"}, 2294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2295 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"}, 2296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2297 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"}, 2298 2299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2300 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"}, 2301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2302 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"}, 2303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2304 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"}, 2305 2306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2307 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"}, 2308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2309 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"}, 2310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2311 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"}, 2312 2313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2314 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"}, 2315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2316 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"}, 2317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2318 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"}, 2319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2320 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"}, 2321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2322 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"}, 2323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2324 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"}, 2325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2326 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"}, 2327 2328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2329 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"}, 2330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2331 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"}, 2332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2333 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"}, 2334 2335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2336 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"}, 2337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2338 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"}, 2339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2340 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"}, 2341 2342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2343 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION}, 2344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2345 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"}, 2346 2347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2348 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"}, 2349 2350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2351 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"}, 2352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2353 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"}, 2354 2355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2356 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2358 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2360 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2362 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2364 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2366 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2368 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2370 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2372 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2374 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2376 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2378 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2380 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2382 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2384 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2386 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2388 0x092d0000, 0x0fff0000, "push%c\t%m"}, 2389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2390 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"}, 2391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2392 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, 2393 2394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2395 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2397 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2399 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2401 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2403 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2405 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2407 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2409 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2411 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2413 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2415 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2417 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2419 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2421 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2423 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2425 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2427 0x08bd0000, 0x0fff0000, "pop%c\t%m"}, 2428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2429 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"}, 2430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2431 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, 2432 2433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2434 0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, 2435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2436 0x0f000000, 0x0f000000, "svc%c\t%0-23x"}, 2437 2438 /* The rest. */ 2439 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 2440 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION}, 2441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2442 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, 2443 {ARM_FEATURE_CORE_LOW (0), 2444 0x00000000, 0x00000000, 0} 2445 }; 2446 2447 /* print_insn_thumb16 recognizes the following format control codes: 2448 2449 %S print Thumb register (bits 3..5 as high number if bit 6 set) 2450 %D print Thumb register (bits 0..2 as high number if bit 7 set) 2451 %<bitfield>I print bitfield as a signed decimal 2452 (top bit of range being the sign bit) 2453 %N print Thumb register mask (with LR) 2454 %O print Thumb register mask (with PC) 2455 %M print Thumb register mask 2456 %b print CZB's 6-bit unsigned branch destination 2457 %s print Thumb right-shift immediate (6..10; 0 == 32). 2458 %c print the condition code 2459 %C print the condition code, or "s" if not conditional 2460 %x print warning if conditional an not at end of IT block" 2461 %X print "\t; unpredictable <IT:code>" if conditional 2462 %I print IT instruction suffix and operands 2463 %W print Thumb Writeback indicator for LDMIA 2464 %<bitfield>r print bitfield as an ARM register 2465 %<bitfield>d print bitfield as a decimal 2466 %<bitfield>H print (bitfield * 2) as a decimal 2467 %<bitfield>W print (bitfield * 4) as a decimal 2468 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol 2469 %<bitfield>B print Thumb branch destination (signed displacement) 2470 %<bitfield>c print bitfield as a condition code 2471 %<bitnum>'c print specified char iff bit is one 2472 %<bitnum>?ab print a if bit is one else print b. */ 2473 2474 static const struct opcode16 thumb_opcodes[] = 2475 { 2476 /* Thumb instructions. */ 2477 2478 /* ARMv8-M Security Extensions instructions. */ 2479 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"}, 2480 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff07, "bxns\t%3-6r"}, 2481 2482 /* ARM V8 instructions. */ 2483 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"}, 2484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"}, 2485 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"}, 2486 2487 /* ARM V6K no-argument instructions. */ 2488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"}, 2489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"}, 2490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"}, 2491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"}, 2492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"}, 2493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"}, 2494 2495 /* ARM V6T2 instructions. */ 2496 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2497 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"}, 2498 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2499 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"}, 2500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"}, 2501 2502 /* ARM V6. */ 2503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"}, 2504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"}, 2505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"}, 2506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"}, 2507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"}, 2508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"}, 2509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"}, 2510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"}, 2511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"}, 2512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"}, 2513 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"}, 2514 2515 /* ARM V5 ISA extends Thumb. */ 2516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T), 2517 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */ 2518 /* This is BLX(2). BLX(1) is a 32-bit instruction. */ 2519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T), 2520 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */ 2521 /* ARM V4T ISA (Thumb v1). */ 2522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2523 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"}, 2524 /* Format 4. */ 2525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"}, 2526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"}, 2527 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"}, 2528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"}, 2529 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"}, 2530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"}, 2531 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"}, 2532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"}, 2533 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"}, 2534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"}, 2535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"}, 2536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"}, 2537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"}, 2538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"}, 2539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"}, 2540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"}, 2541 /* format 13 */ 2542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"}, 2543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"}, 2544 /* format 5 */ 2545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"}, 2546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"}, 2547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"}, 2548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"}, 2549 /* format 14 */ 2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"}, 2551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"}, 2552 /* format 2 */ 2553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2554 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"}, 2555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2556 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"}, 2557 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2558 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"}, 2559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2560 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"}, 2561 /* format 8 */ 2562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2563 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"}, 2564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2565 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"}, 2566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2567 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"}, 2568 /* format 7 */ 2569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2570 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, 2571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2572 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, 2573 /* format 1 */ 2574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"}, 2575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2576 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"}, 2577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"}, 2578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"}, 2579 /* format 3 */ 2580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"}, 2581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"}, 2582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"}, 2583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"}, 2584 /* format 6 */ 2585 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */ 2586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2587 0x4800, 0xF800, 2588 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"}, 2589 /* format 9 */ 2590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2591 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"}, 2592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2593 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"}, 2594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2595 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"}, 2596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2597 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"}, 2598 /* format 10 */ 2599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2600 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"}, 2601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2602 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"}, 2603 /* format 11 */ 2604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2605 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"}, 2606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2607 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"}, 2608 /* format 12 */ 2609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2610 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"}, 2611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2612 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"}, 2613 /* format 15 */ 2614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"}, 2615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"}, 2616 /* format 17 */ 2617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"}, 2618 /* format 16 */ 2619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"}, 2620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION}, 2621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"}, 2622 /* format 18 */ 2623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"}, 2624 2625 /* The E800 .. FFFF range is unconditionally redirected to the 2626 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs 2627 are processed via that table. Thus, we can never encounter a 2628 bare "second half of BL/BLX(1)" instruction here. */ 2629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION}, 2630 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 2631 }; 2632 2633 /* Thumb32 opcodes use the same table structure as the ARM opcodes. 2634 We adopt the convention that hw1 is the high 16 bits of .value and 2635 .mask, hw2 the low 16 bits. 2636 2637 print_insn_thumb32 recognizes the following format control codes: 2638 2639 %% % 2640 2641 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0] 2642 %M print a modified 12-bit immediate (same location) 2643 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0] 2644 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4] 2645 %H print a 16-bit immediate from hw2[3:0],hw1[11:0] 2646 %S print a possibly-shifted Rm 2647 2648 %L print address for a ldrd/strd instruction 2649 %a print the address of a plain load/store 2650 %w print the width and signedness of a core load/store 2651 %m print register mask for ldm/stm 2652 2653 %E print the lsb and width fields of a bfc/bfi instruction 2654 %F print the lsb and width fields of a sbfx/ubfx instruction 2655 %b print a conditional branch offset 2656 %B print an unconditional branch offset 2657 %s print the shift field of an SSAT instruction 2658 %R print the rotation field of an SXT instruction 2659 %U print barrier type. 2660 %P print address for pli instruction. 2661 %c print the condition code 2662 %x print warning if conditional an not at end of IT block" 2663 %X print "\t; unpredictable <IT:code>" if conditional 2664 2665 %<bitfield>d print bitfield in decimal 2666 %<bitfield>D print bitfield plus one in decimal 2667 %<bitfield>W print bitfield*4 in decimal 2668 %<bitfield>r print bitfield as an ARM register 2669 %<bitfield>R as %<>r but r15 is UNPREDICTABLE 2670 %<bitfield>S as %<>R but r13 is UNPREDICTABLE 2671 %<bitfield>c print bitfield as a condition code 2672 2673 %<bitfield>'c print specified char iff bitfield is all ones 2674 %<bitfield>`c print specified char iff bitfield is all zeroes 2675 %<bitfield>?ab... select from array of values in big endian order 2676 2677 With one exception at the bottom (done because BL and BLX(1) need 2678 to come dead last), this table was machine-sorted first in 2679 decreasing order of number of bits set in the mask, then in 2680 increasing numeric order of mask, then in increasing numeric order 2681 of opcode. This order is not the clearest for a human reader, but 2682 is guaranteed never to catch a special-case bit pattern with a more 2683 general mask, which is important, because this instruction encoding 2684 makes heavy use of special-case bit patterns. */ 2685 static const struct opcode32 thumb32_opcodes[] = 2686 { 2687 /* ARMv8-M and ARMv8-M Security Extensions instructions. */ 2688 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"}, 2689 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 2690 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"}, 2691 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 2692 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"}, 2693 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 2694 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"}, 2695 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 2696 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"}, 2697 2698 /* ARM V8.2 RAS extension instructions. */ 2699 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), 2700 0xf3af8010, 0xffffffff, "esb"}, 2701 2702 /* V8 instructions. */ 2703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2704 0xf3af8005, 0xffffffff, "sevl%c.w"}, 2705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2706 0xf78f8000, 0xfffffffc, "dcps%0-1d"}, 2707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2708 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"}, 2709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2710 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"}, 2711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2712 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"}, 2713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2714 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"}, 2715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2716 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"}, 2717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2718 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"}, 2719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2720 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"}, 2721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2722 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"}, 2723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2724 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"}, 2725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2726 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"}, 2727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2728 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, 2729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2730 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, 2731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2732 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, 2733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2734 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"}, 2735 2736 /* CRC32 instructions. */ 2737 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2738 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"}, 2739 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2740 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"}, 2741 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2742 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"}, 2743 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2744 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"}, 2745 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2746 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"}, 2747 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2748 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"}, 2749 2750 /* V7 instructions. */ 2751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"}, 2752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"}, 2753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"}, 2754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"}, 2755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"}, 2756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"}, 2757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"}, 2758 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), 2759 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"}, 2760 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), 2761 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"}, 2762 2763 /* Virtualization Extension instructions. */ 2764 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"}, 2765 /* We skip ERET as that is SUBS pc, lr, #0. */ 2766 2767 /* MP Extension instructions. */ 2768 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"}, 2769 2770 /* Security extension instructions. */ 2771 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"}, 2772 2773 /* Instructions defined in the basic V6T2 set. */ 2774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"}, 2775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"}, 2776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"}, 2777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"}, 2778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"}, 2779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2780 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"}, 2781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"}, 2782 2783 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2784 0xf3bf8f2f, 0xffffffff, "clrex%c"}, 2785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2786 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"}, 2787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2788 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"}, 2789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2790 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"}, 2791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2792 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"}, 2793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2794 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"}, 2795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2796 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"}, 2797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2798 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"}, 2799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2800 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"}, 2801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2802 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"}, 2803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2804 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"}, 2805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2806 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"}, 2807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2808 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"}, 2809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2810 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"}, 2811 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2812 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"}, 2813 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2814 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"}, 2815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2816 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"}, 2817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2818 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"}, 2819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2820 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"}, 2821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2822 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"}, 2823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2824 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"}, 2825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2826 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"}, 2827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2828 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"}, 2829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2830 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"}, 2831 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2832 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"}, 2833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2834 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"}, 2835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2836 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"}, 2837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2838 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"}, 2839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2840 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"}, 2841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2842 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"}, 2843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2844 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"}, 2845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2846 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"}, 2847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2848 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"}, 2849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2850 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"}, 2851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2852 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"}, 2853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2854 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"}, 2855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2856 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"}, 2857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2858 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"}, 2859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2860 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"}, 2861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2862 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"}, 2863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2864 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"}, 2865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2866 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"}, 2867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2868 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"}, 2869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2870 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"}, 2871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2872 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"}, 2873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2874 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"}, 2875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2876 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"}, 2877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2878 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"}, 2879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2880 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"}, 2881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2882 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"}, 2883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2884 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"}, 2885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2886 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"}, 2887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2888 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"}, 2889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2890 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"}, 2891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2892 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"}, 2893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2894 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"}, 2895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2896 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"}, 2897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2898 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"}, 2899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2900 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"}, 2901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2902 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"}, 2903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2904 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"}, 2905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2906 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"}, 2907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2908 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"}, 2909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2910 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"}, 2911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2912 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"}, 2913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2914 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"}, 2915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2916 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"}, 2917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2918 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"}, 2919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2920 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"}, 2921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2922 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"}, 2923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2924 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"}, 2925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2926 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"}, 2927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2928 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"}, 2929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2930 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"}, 2931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2932 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 2933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2934 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 2935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2936 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 2937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2938 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"}, 2939 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2940 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"}, 2941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2942 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"}, 2943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2944 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"}, 2945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2946 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"}, 2947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2948 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"}, 2949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2950 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"}, 2951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2952 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"}, 2953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2954 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"}, 2955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2956 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"}, 2957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2958 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, 2959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2960 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, 2961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2962 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"}, 2963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2964 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"}, 2965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2966 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"}, 2967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2968 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"}, 2969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2970 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"}, 2971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2972 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"}, 2973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2974 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"}, 2975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2976 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"}, 2977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2978 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"}, 2979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2980 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"}, 2981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2982 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"}, 2983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2984 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"}, 2985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2986 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"}, 2987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2988 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"}, 2989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2990 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"}, 2991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2992 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 2993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2994 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 2995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2996 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 2997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2998 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 2999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3000 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3002 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3004 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3006 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3007 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3008 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"}, 3009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3010 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"}, 3011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3012 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"}, 3013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3014 0xf810f000, 0xff70f000, "pld%c\t%a"}, 3015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3016 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3018 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3020 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3022 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3024 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3026 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3028 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3030 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"}, 3031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3032 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"}, 3033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3034 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"}, 3035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3036 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"}, 3037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3038 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"}, 3039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3040 0xfb100000, 0xfff000c0, 3041 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 3042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3043 0xfbc00080, 0xfff000c0, 3044 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, 3045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3046 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"}, 3047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3048 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"}, 3049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3050 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"}, 3051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3052 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"}, 3053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3054 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"}, 3055 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3056 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"}, 3057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3058 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"}, 3059 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3060 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"}, 3061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3062 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"}, 3063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3064 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"}, 3065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3066 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"}, 3067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3068 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"}, 3069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3070 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"}, 3071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3072 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"}, 3073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3074 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"}, 3075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3076 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"}, 3077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3078 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"}, 3079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3080 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"}, 3081 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3082 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"}, 3083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3084 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"}, 3085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3086 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"}, 3087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3088 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"}, 3089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3090 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"}, 3091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3092 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"}, 3093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3094 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"}, 3095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3096 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"}, 3097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3098 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"}, 3099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3100 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"}, 3101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3102 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"}, 3103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3104 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"}, 3105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3106 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"}, 3107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3108 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"}, 3109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3110 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"}, 3111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3112 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"}, 3113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3114 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"}, 3115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3116 0xe9400000, 0xff500000, 3117 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"}, 3118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3119 0xe9500000, 0xff500000, 3120 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"}, 3121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3122 0xe8600000, 0xff700000, 3123 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"}, 3124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3125 0xe8700000, 0xff700000, 3126 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"}, 3127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3128 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"}, 3129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3130 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"}, 3131 3132 /* Filter out Bcc with cond=E or F, which are used for other instructions. */ 3133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3134 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"}, 3135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3136 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"}, 3137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3138 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"}, 3139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3140 0xf0009000, 0xf800d000, "b%c.w\t%B%x"}, 3141 3142 /* These have been 32-bit since the invention of Thumb. */ 3143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 3144 0xf000c000, 0xf800d001, "blx%c\t%B%x"}, 3145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 3146 0xf000d000, 0xf800d000, "bl%c\t%B%x"}, 3147 3148 /* Fallback. */ 3149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3150 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, 3151 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 3152 }; 3153 3154 static const char *const arm_conditional[] = 3155 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", 3156 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""}; 3157 3158 static const char *const arm_fp_const[] = 3159 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; 3160 3161 static const char *const arm_shift[] = 3162 {"lsl", "lsr", "asr", "ror"}; 3163 3164 typedef struct 3165 { 3166 const char *name; 3167 const char *description; 3168 const char *reg_names[16]; 3169 } 3170 arm_regname; 3171 3172 static const arm_regname regnames[] = 3173 { 3174 { "raw" , "Select raw register names", 3175 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}}, 3176 { "gcc", "Select register names used by GCC", 3177 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }}, 3178 { "std", "Select register names used in ARM's ISA documentation", 3179 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }}, 3180 { "apcs", "Select register names used in the APCS", 3181 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }}, 3182 { "atpcs", "Select register names used in the ATPCS", 3183 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, 3184 { "special-atpcs", "Select special register names used in the ATPCS", 3185 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}, 3186 }; 3187 3188 static const char *const iwmmxt_wwnames[] = 3189 {"b", "h", "w", "d"}; 3190 3191 static const char *const iwmmxt_wwssnames[] = 3192 {"b", "bus", "bc", "bss", 3193 "h", "hus", "hc", "hss", 3194 "w", "wus", "wc", "wss", 3195 "d", "dus", "dc", "dss" 3196 }; 3197 3198 static const char *const iwmmxt_regnames[] = 3199 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7", 3200 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15" 3201 }; 3202 3203 static const char *const iwmmxt_cregnames[] = 3204 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved", 3205 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved" 3206 }; 3207 3208 /* Default to GCC register name set. */ 3209 static unsigned int regname_selected = 1; 3210 3211 #define NUM_ARM_REGNAMES NUM_ELEM (regnames) 3212 #define arm_regnames regnames[regname_selected].reg_names 3213 3214 static bfd_boolean force_thumb = FALSE; 3215 3216 /* Current IT instruction state. This contains the same state as the IT 3217 bits in the CPSR. */ 3218 static unsigned int ifthen_state; 3219 /* IT state for the next instruction. */ 3220 static unsigned int ifthen_next_state; 3221 /* The address of the insn for which the IT state is valid. */ 3222 static bfd_vma ifthen_address; 3223 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf) 3224 /* Indicates that the current Conditional state is unconditional or outside 3225 an IT block. */ 3226 #define COND_UNCOND 16 3227 3228 3229 /* Functions. */ 3231 int 3232 get_arm_regname_num_options (void) 3233 { 3234 return NUM_ARM_REGNAMES; 3235 } 3236 3237 int 3238 set_arm_regname_option (int option) 3239 { 3240 int old = regname_selected; 3241 regname_selected = option; 3242 return old; 3243 } 3244 3245 int 3246 get_arm_regnames (int option, 3247 const char **setname, 3248 const char **setdescription, 3249 const char *const **register_names) 3250 { 3251 *setname = regnames[option].name; 3252 *setdescription = regnames[option].description; 3253 *register_names = regnames[option].reg_names; 3254 return 16; 3255 } 3256 3257 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?. 3258 Returns pointer to following character of the format string and 3259 fills in *VALUEP and *WIDTHP with the extracted value and number of 3260 bits extracted. WIDTHP can be NULL. */ 3261 3262 static const char * 3263 arm_decode_bitfield (const char *ptr, 3264 unsigned long insn, 3265 unsigned long *valuep, 3266 int *widthp) 3267 { 3268 unsigned long value = 0; 3269 int width = 0; 3270 3271 do 3272 { 3273 int start, end; 3274 int bits; 3275 3276 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++) 3277 start = start * 10 + *ptr - '0'; 3278 if (*ptr == '-') 3279 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++) 3280 end = end * 10 + *ptr - '0'; 3281 else 3282 end = start; 3283 bits = end - start; 3284 if (bits < 0) 3285 abort (); 3286 value |= ((insn >> start) & ((2ul << bits) - 1)) << width; 3287 width += bits + 1; 3288 } 3289 while (*ptr++ == ','); 3290 *valuep = value; 3291 if (widthp) 3292 *widthp = width; 3293 return ptr - 1; 3294 } 3295 3296 static void 3297 arm_decode_shift (long given, fprintf_ftype func, void *stream, 3298 bfd_boolean print_shift) 3299 { 3300 func (stream, "%s", arm_regnames[given & 0xf]); 3301 3302 if ((given & 0xff0) != 0) 3303 { 3304 if ((given & 0x10) == 0) 3305 { 3306 int amount = (given & 0xf80) >> 7; 3307 int shift = (given & 0x60) >> 5; 3308 3309 if (amount == 0) 3310 { 3311 if (shift == 3) 3312 { 3313 func (stream, ", rrx"); 3314 return; 3315 } 3316 3317 amount = 32; 3318 } 3319 3320 if (print_shift) 3321 func (stream, ", %s #%d", arm_shift[shift], amount); 3322 else 3323 func (stream, ", #%d", amount); 3324 } 3325 else if ((given & 0x80) == 0x80) 3326 func (stream, "\t; <illegal shifter operand>"); 3327 else if (print_shift) 3328 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5], 3329 arm_regnames[(given & 0xf00) >> 8]); 3330 else 3331 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]); 3332 } 3333 } 3334 3335 #define W_BIT 21 3336 #define I_BIT 22 3337 #define U_BIT 23 3338 #define P_BIT 24 3339 3340 #define WRITEBACK_BIT_SET (given & (1 << W_BIT)) 3341 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT)) 3342 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0) 3343 #define PRE_BIT_SET (given & (1 << P_BIT)) 3344 3345 /* Print one coprocessor instruction on INFO->STREAM. 3346 Return TRUE if the instuction matched, FALSE if this is not a 3347 recognised coprocessor instruction. */ 3348 3349 static bfd_boolean 3350 print_insn_coprocessor (bfd_vma pc, 3351 struct disassemble_info *info, 3352 long given, 3353 bfd_boolean thumb) 3354 { 3355 const struct opcode32 *insn; 3356 void *stream = info->stream; 3357 fprintf_ftype func = info->fprintf_func; 3358 unsigned long mask; 3359 unsigned long value = 0; 3360 int cond; 3361 int cp_num; 3362 struct arm_private_data *private_data = info->private_data; 3363 arm_feature_set allowed_arches = ARM_ARCH_NONE; 3364 3365 ARM_FEATURE_COPY (allowed_arches, private_data->features); 3366 3367 for (insn = coprocessor_opcodes; insn->assembler; insn++) 3368 { 3369 unsigned long u_reg = 16; 3370 bfd_boolean is_unpredictable = FALSE; 3371 signed long value_in_comment = 0; 3372 const char *c; 3373 3374 if (ARM_FEATURE_ZERO (insn->arch)) 3375 switch (insn->value) 3376 { 3377 case SENTINEL_IWMMXT_START: 3378 if (info->mach != bfd_mach_arm_XScale 3379 && info->mach != bfd_mach_arm_iWMMXt 3380 && info->mach != bfd_mach_arm_iWMMXt2) 3381 do 3382 insn++; 3383 while ((! ARM_FEATURE_ZERO (insn->arch)) 3384 && insn->value != SENTINEL_IWMMXT_END); 3385 continue; 3386 3387 case SENTINEL_IWMMXT_END: 3388 continue; 3389 3390 case SENTINEL_GENERIC_START: 3391 ARM_FEATURE_COPY (allowed_arches, private_data->features); 3392 continue; 3393 3394 default: 3395 abort (); 3396 } 3397 3398 mask = insn->mask; 3399 value = insn->value; 3400 cp_num = (given >> 8) & 0xf; 3401 3402 if (thumb) 3403 { 3404 /* The high 4 bits are 0xe for Arm conditional instructions, and 3405 0xe for arm unconditional instructions. The rest of the 3406 encoding is the same. */ 3407 mask |= 0xf0000000; 3408 value |= 0xe0000000; 3409 if (ifthen_state) 3410 cond = IFTHEN_COND; 3411 else 3412 cond = COND_UNCOND; 3413 } 3414 else 3415 { 3416 /* Only match unconditional instuctions against unconditional 3417 patterns. */ 3418 if ((given & 0xf0000000) == 0xf0000000) 3419 { 3420 mask |= 0xf0000000; 3421 cond = COND_UNCOND; 3422 } 3423 else 3424 { 3425 cond = (given >> 28) & 0xf; 3426 if (cond == 0xe) 3427 cond = COND_UNCOND; 3428 } 3429 } 3430 3431 if ((given & mask) != value) 3432 continue; 3433 3434 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches)) 3435 continue; 3436 3437 if (insn->value == 0xfe000010 /* mcr2 */ 3438 || insn->value == 0xfe100010 /* mrc2 */ 3439 || insn->value == 0xfc100000 /* ldc2 */ 3440 || insn->value == 0xfc000000) /* stc2 */ 3441 { 3442 if (cp_num == 9 || cp_num == 10 || cp_num == 11) 3443 is_unpredictable = TRUE; 3444 } 3445 else if (insn->value == 0x0e000000 /* cdp */ 3446 || insn->value == 0xfe000000 /* cdp2 */ 3447 || insn->value == 0x0e000010 /* mcr */ 3448 || insn->value == 0x0e100010 /* mrc */ 3449 || insn->value == 0x0c100000 /* ldc */ 3450 || insn->value == 0x0c000000) /* stc */ 3451 { 3452 /* Floating-point instructions. */ 3453 if (cp_num == 9 || cp_num == 10 || cp_num == 11) 3454 continue; 3455 } 3456 3457 for (c = insn->assembler; *c; c++) 3458 { 3459 if (*c == '%') 3460 { 3461 switch (*++c) 3462 { 3463 case '%': 3464 func (stream, "%%"); 3465 break; 3466 3467 case 'A': 3468 { 3469 int rn = (given >> 16) & 0xf; 3470 bfd_vma offset = given & 0xff; 3471 3472 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 3473 3474 if (PRE_BIT_SET || WRITEBACK_BIT_SET) 3475 { 3476 /* Not unindexed. The offset is scaled. */ 3477 if (cp_num == 9) 3478 /* vldr.16/vstr.16 will shift the address 3479 left by 1 bit only. */ 3480 offset = offset * 2; 3481 else 3482 offset = offset * 4; 3483 3484 if (NEGATIVE_BIT_SET) 3485 offset = - offset; 3486 if (rn != 15) 3487 value_in_comment = offset; 3488 } 3489 3490 if (PRE_BIT_SET) 3491 { 3492 if (offset) 3493 func (stream, ", #%d]%s", 3494 (int) offset, 3495 WRITEBACK_BIT_SET ? "!" : ""); 3496 else if (NEGATIVE_BIT_SET) 3497 func (stream, ", #-0]"); 3498 else 3499 func (stream, "]"); 3500 } 3501 else 3502 { 3503 func (stream, "]"); 3504 3505 if (WRITEBACK_BIT_SET) 3506 { 3507 if (offset) 3508 func (stream, ", #%d", (int) offset); 3509 else if (NEGATIVE_BIT_SET) 3510 func (stream, ", #-0"); 3511 } 3512 else 3513 { 3514 func (stream, ", {%s%d}", 3515 (NEGATIVE_BIT_SET && !offset) ? "-" : "", 3516 (int) offset); 3517 value_in_comment = offset; 3518 } 3519 } 3520 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET)) 3521 { 3522 func (stream, "\t; "); 3523 /* For unaligned PCs, apply off-by-alignment 3524 correction. */ 3525 info->print_address_func (offset + pc 3526 + info->bytes_per_chunk * 2 3527 - (pc & 3), 3528 info); 3529 } 3530 } 3531 break; 3532 3533 case 'B': 3534 { 3535 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10); 3536 int offset = (given >> 1) & 0x3f; 3537 3538 if (offset == 1) 3539 func (stream, "{d%d}", regno); 3540 else if (regno + offset > 32) 3541 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1); 3542 else 3543 func (stream, "{d%d-d%d}", regno, regno + offset - 1); 3544 } 3545 break; 3546 3547 case 'u': 3548 if (cond != COND_UNCOND) 3549 is_unpredictable = TRUE; 3550 3551 /* Fall through. */ 3552 case 'c': 3553 if (cond != COND_UNCOND && cp_num == 9) 3554 is_unpredictable = TRUE; 3555 3556 func (stream, "%s", arm_conditional[cond]); 3557 break; 3558 3559 case 'I': 3560 /* Print a Cirrus/DSP shift immediate. */ 3561 /* Immediates are 7bit signed ints with bits 0..3 in 3562 bits 0..3 of opcode and bits 4..6 in bits 5..7 3563 of opcode. */ 3564 { 3565 int imm; 3566 3567 imm = (given & 0xf) | ((given & 0xe0) >> 1); 3568 3569 /* Is ``imm'' a negative number? */ 3570 if (imm & 0x40) 3571 imm -= 0x80; 3572 3573 func (stream, "%d", imm); 3574 } 3575 3576 break; 3577 3578 case 'F': 3579 switch (given & 0x00408000) 3580 { 3581 case 0: 3582 func (stream, "4"); 3583 break; 3584 case 0x8000: 3585 func (stream, "1"); 3586 break; 3587 case 0x00400000: 3588 func (stream, "2"); 3589 break; 3590 default: 3591 func (stream, "3"); 3592 } 3593 break; 3594 3595 case 'P': 3596 switch (given & 0x00080080) 3597 { 3598 case 0: 3599 func (stream, "s"); 3600 break; 3601 case 0x80: 3602 func (stream, "d"); 3603 break; 3604 case 0x00080000: 3605 func (stream, "e"); 3606 break; 3607 default: 3608 func (stream, _("<illegal precision>")); 3609 break; 3610 } 3611 break; 3612 3613 case 'Q': 3614 switch (given & 0x00408000) 3615 { 3616 case 0: 3617 func (stream, "s"); 3618 break; 3619 case 0x8000: 3620 func (stream, "d"); 3621 break; 3622 case 0x00400000: 3623 func (stream, "e"); 3624 break; 3625 default: 3626 func (stream, "p"); 3627 break; 3628 } 3629 break; 3630 3631 case 'R': 3632 switch (given & 0x60) 3633 { 3634 case 0: 3635 break; 3636 case 0x20: 3637 func (stream, "p"); 3638 break; 3639 case 0x40: 3640 func (stream, "m"); 3641 break; 3642 default: 3643 func (stream, "z"); 3644 break; 3645 } 3646 break; 3647 3648 case '0': case '1': case '2': case '3': case '4': 3649 case '5': case '6': case '7': case '8': case '9': 3650 { 3651 int width; 3652 3653 c = arm_decode_bitfield (c, given, &value, &width); 3654 3655 switch (*c) 3656 { 3657 case 'R': 3658 if (value == 15) 3659 is_unpredictable = TRUE; 3660 /* Fall through. */ 3661 case 'r': 3662 if (c[1] == 'u') 3663 { 3664 /* Eat the 'u' character. */ 3665 ++ c; 3666 3667 if (u_reg == value) 3668 is_unpredictable = TRUE; 3669 u_reg = value; 3670 } 3671 func (stream, "%s", arm_regnames[value]); 3672 break; 3673 case 'D': 3674 func (stream, "d%ld", value); 3675 break; 3676 case 'Q': 3677 if (value & 1) 3678 func (stream, "<illegal reg q%ld.5>", value >> 1); 3679 else 3680 func (stream, "q%ld", value >> 1); 3681 break; 3682 case 'd': 3683 func (stream, "%ld", value); 3684 value_in_comment = value; 3685 break; 3686 case 'E': 3687 { 3688 /* Converts immediate 8 bit back to float value. */ 3689 unsigned floatVal = (value & 0x80) << 24 3690 | (value & 0x3F) << 19 3691 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30)); 3692 3693 /* Quarter float have a maximum value of 31.0. 3694 Get floating point value multiplied by 1e7. 3695 The maximum value stays in limit of a 32-bit int. */ 3696 unsigned decVal = 3697 (78125 << (((floatVal >> 23) & 0xFF) - 124)) * 3698 (16 + (value & 0xF)); 3699 3700 if (!(decVal % 1000000)) 3701 func (stream, "%ld\t; 0x%08x %c%u.%01u", value, 3702 floatVal, value & 0x80 ? '-' : ' ', 3703 decVal / 10000000, 3704 decVal % 10000000 / 1000000); 3705 else if (!(decVal % 10000)) 3706 func (stream, "%ld\t; 0x%08x %c%u.%03u", value, 3707 floatVal, value & 0x80 ? '-' : ' ', 3708 decVal / 10000000, 3709 decVal % 10000000 / 10000); 3710 else 3711 func (stream, "%ld\t; 0x%08x %c%u.%07u", value, 3712 floatVal, value & 0x80 ? '-' : ' ', 3713 decVal / 10000000, decVal % 10000000); 3714 break; 3715 } 3716 case 'k': 3717 { 3718 int from = (given & (1 << 7)) ? 32 : 16; 3719 func (stream, "%ld", from - value); 3720 } 3721 break; 3722 3723 case 'f': 3724 if (value > 7) 3725 func (stream, "#%s", arm_fp_const[value & 7]); 3726 else 3727 func (stream, "f%ld", value); 3728 break; 3729 3730 case 'w': 3731 if (width == 2) 3732 func (stream, "%s", iwmmxt_wwnames[value]); 3733 else 3734 func (stream, "%s", iwmmxt_wwssnames[value]); 3735 break; 3736 3737 case 'g': 3738 func (stream, "%s", iwmmxt_regnames[value]); 3739 break; 3740 case 'G': 3741 func (stream, "%s", iwmmxt_cregnames[value]); 3742 break; 3743 3744 case 'x': 3745 func (stream, "0x%lx", (value & 0xffffffffUL)); 3746 break; 3747 3748 case 'c': 3749 switch (value) 3750 { 3751 case 0: 3752 func (stream, "eq"); 3753 break; 3754 3755 case 1: 3756 func (stream, "vs"); 3757 break; 3758 3759 case 2: 3760 func (stream, "ge"); 3761 break; 3762 3763 case 3: 3764 func (stream, "gt"); 3765 break; 3766 3767 default: 3768 func (stream, "??"); 3769 break; 3770 } 3771 break; 3772 3773 case '`': 3774 c++; 3775 if (value == 0) 3776 func (stream, "%c", *c); 3777 break; 3778 case '\'': 3779 c++; 3780 if (value == ((1ul << width) - 1)) 3781 func (stream, "%c", *c); 3782 break; 3783 case '?': 3784 func (stream, "%c", c[(1 << width) - (int) value]); 3785 c += 1 << width; 3786 break; 3787 default: 3788 abort (); 3789 } 3790 break; 3791 3792 case 'y': 3793 case 'z': 3794 { 3795 int single = *c++ == 'y'; 3796 int regno; 3797 3798 switch (*c) 3799 { 3800 case '4': /* Sm pair */ 3801 case '0': /* Sm, Dm */ 3802 regno = given & 0x0000000f; 3803 if (single) 3804 { 3805 regno <<= 1; 3806 regno += (given >> 5) & 1; 3807 } 3808 else 3809 regno += ((given >> 5) & 1) << 4; 3810 break; 3811 3812 case '1': /* Sd, Dd */ 3813 regno = (given >> 12) & 0x0000000f; 3814 if (single) 3815 { 3816 regno <<= 1; 3817 regno += (given >> 22) & 1; 3818 } 3819 else 3820 regno += ((given >> 22) & 1) << 4; 3821 break; 3822 3823 case '2': /* Sn, Dn */ 3824 regno = (given >> 16) & 0x0000000f; 3825 if (single) 3826 { 3827 regno <<= 1; 3828 regno += (given >> 7) & 1; 3829 } 3830 else 3831 regno += ((given >> 7) & 1) << 4; 3832 break; 3833 3834 case '3': /* List */ 3835 func (stream, "{"); 3836 regno = (given >> 12) & 0x0000000f; 3837 if (single) 3838 { 3839 regno <<= 1; 3840 regno += (given >> 22) & 1; 3841 } 3842 else 3843 regno += ((given >> 22) & 1) << 4; 3844 break; 3845 3846 default: 3847 abort (); 3848 } 3849 3850 func (stream, "%c%d", single ? 's' : 'd', regno); 3851 3852 if (*c == '3') 3853 { 3854 int count = given & 0xff; 3855 3856 if (single == 0) 3857 count >>= 1; 3858 3859 if (--count) 3860 { 3861 func (stream, "-%c%d", 3862 single ? 's' : 'd', 3863 regno + count); 3864 } 3865 3866 func (stream, "}"); 3867 } 3868 else if (*c == '4') 3869 func (stream, ", %c%d", single ? 's' : 'd', 3870 regno + 1); 3871 } 3872 break; 3873 3874 case 'L': 3875 switch (given & 0x00400100) 3876 { 3877 case 0x00000000: func (stream, "b"); break; 3878 case 0x00400000: func (stream, "h"); break; 3879 case 0x00000100: func (stream, "w"); break; 3880 case 0x00400100: func (stream, "d"); break; 3881 default: 3882 break; 3883 } 3884 break; 3885 3886 case 'Z': 3887 { 3888 /* given (20, 23) | given (0, 3) */ 3889 value = ((given >> 16) & 0xf0) | (given & 0xf); 3890 func (stream, "%d", (int) value); 3891 } 3892 break; 3893 3894 case 'l': 3895 /* This is like the 'A' operator, except that if 3896 the width field "M" is zero, then the offset is 3897 *not* multiplied by four. */ 3898 { 3899 int offset = given & 0xff; 3900 int multiplier = (given & 0x00000100) ? 4 : 1; 3901 3902 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 3903 3904 if (multiplier > 1) 3905 { 3906 value_in_comment = offset * multiplier; 3907 if (NEGATIVE_BIT_SET) 3908 value_in_comment = - value_in_comment; 3909 } 3910 3911 if (offset) 3912 { 3913 if (PRE_BIT_SET) 3914 func (stream, ", #%s%d]%s", 3915 NEGATIVE_BIT_SET ? "-" : "", 3916 offset * multiplier, 3917 WRITEBACK_BIT_SET ? "!" : ""); 3918 else 3919 func (stream, "], #%s%d", 3920 NEGATIVE_BIT_SET ? "-" : "", 3921 offset * multiplier); 3922 } 3923 else 3924 func (stream, "]"); 3925 } 3926 break; 3927 3928 case 'r': 3929 { 3930 int imm4 = (given >> 4) & 0xf; 3931 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1); 3932 int ubit = ! NEGATIVE_BIT_SET; 3933 const char *rm = arm_regnames [given & 0xf]; 3934 const char *rn = arm_regnames [(given >> 16) & 0xf]; 3935 3936 switch (puw_bits) 3937 { 3938 case 1: 3939 case 3: 3940 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm); 3941 if (imm4) 3942 func (stream, ", lsl #%d", imm4); 3943 break; 3944 3945 case 4: 3946 case 5: 3947 case 6: 3948 case 7: 3949 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm); 3950 if (imm4 > 0) 3951 func (stream, ", lsl #%d", imm4); 3952 func (stream, "]"); 3953 if (puw_bits == 5 || puw_bits == 7) 3954 func (stream, "!"); 3955 break; 3956 3957 default: 3958 func (stream, "INVALID"); 3959 } 3960 } 3961 break; 3962 3963 case 'i': 3964 { 3965 long imm5; 3966 imm5 = ((given & 0x100) >> 4) | (given & 0xf); 3967 func (stream, "%ld", (imm5 == 0) ? 32 : imm5); 3968 } 3969 break; 3970 3971 default: 3972 abort (); 3973 } 3974 } 3975 } 3976 else 3977 func (stream, "%c", *c); 3978 } 3979 3980 if (value_in_comment > 32 || value_in_comment < -16) 3981 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL)); 3982 3983 if (is_unpredictable) 3984 func (stream, UNPREDICTABLE_INSTRUCTION); 3985 3986 return TRUE; 3987 } 3988 return FALSE; 3989 } 3990 3991 /* Decodes and prints ARM addressing modes. Returns the offset 3992 used in the address, if any, if it is worthwhile printing the 3993 offset as a hexadecimal value in a comment at the end of the 3994 line of disassembly. */ 3995 3996 static signed long 3997 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) 3998 { 3999 void *stream = info->stream; 4000 fprintf_ftype func = info->fprintf_func; 4001 bfd_vma offset = 0; 4002 4003 if (((given & 0x000f0000) == 0x000f0000) 4004 && ((given & 0x02000000) == 0)) 4005 { 4006 offset = given & 0xfff; 4007 4008 func (stream, "[pc"); 4009 4010 if (PRE_BIT_SET) 4011 { 4012 /* Pre-indexed. Elide offset of positive zero when 4013 non-writeback. */ 4014 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) 4015 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4016 4017 if (NEGATIVE_BIT_SET) 4018 offset = -offset; 4019 4020 offset += pc + 8; 4021 4022 /* Cope with the possibility of write-back 4023 being used. Probably a very dangerous thing 4024 for the programmer to do, but who are we to 4025 argue ? */ 4026 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : ""); 4027 } 4028 else /* Post indexed. */ 4029 { 4030 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4031 4032 /* Ie ignore the offset. */ 4033 offset = pc + 8; 4034 } 4035 4036 func (stream, "\t; "); 4037 info->print_address_func (offset, info); 4038 offset = 0; 4039 } 4040 else 4041 { 4042 func (stream, "[%s", 4043 arm_regnames[(given >> 16) & 0xf]); 4044 4045 if (PRE_BIT_SET) 4046 { 4047 if ((given & 0x02000000) == 0) 4048 { 4049 /* Elide offset of positive zero when non-writeback. */ 4050 offset = given & 0xfff; 4051 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) 4052 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4053 } 4054 else 4055 { 4056 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : ""); 4057 arm_decode_shift (given, func, stream, TRUE); 4058 } 4059 4060 func (stream, "]%s", 4061 WRITEBACK_BIT_SET ? "!" : ""); 4062 } 4063 else 4064 { 4065 if ((given & 0x02000000) == 0) 4066 { 4067 /* Always show offset. */ 4068 offset = given & 0xfff; 4069 func (stream, "], #%s%d", 4070 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4071 } 4072 else 4073 { 4074 func (stream, "], %s", 4075 NEGATIVE_BIT_SET ? "-" : ""); 4076 arm_decode_shift (given, func, stream, TRUE); 4077 } 4078 } 4079 if (NEGATIVE_BIT_SET) 4080 offset = -offset; 4081 } 4082 4083 return (signed long) offset; 4084 } 4085 4086 /* Print one neon instruction on INFO->STREAM. 4087 Return TRUE if the instuction matched, FALSE if this is not a 4088 recognised neon instruction. */ 4089 4090 static bfd_boolean 4091 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) 4092 { 4093 const struct opcode32 *insn; 4094 void *stream = info->stream; 4095 fprintf_ftype func = info->fprintf_func; 4096 4097 if (thumb) 4098 { 4099 if ((given & 0xef000000) == 0xef000000) 4100 { 4101 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */ 4102 unsigned long bit28 = given & (1 << 28); 4103 4104 given &= 0x00ffffff; 4105 if (bit28) 4106 given |= 0xf3000000; 4107 else 4108 given |= 0xf2000000; 4109 } 4110 else if ((given & 0xff000000) == 0xf9000000) 4111 given ^= 0xf9000000 ^ 0xf4000000; 4112 else 4113 return FALSE; 4114 } 4115 4116 for (insn = neon_opcodes; insn->assembler; insn++) 4117 { 4118 if ((given & insn->mask) == insn->value) 4119 { 4120 signed long value_in_comment = 0; 4121 bfd_boolean is_unpredictable = FALSE; 4122 const char *c; 4123 4124 for (c = insn->assembler; *c; c++) 4125 { 4126 if (*c == '%') 4127 { 4128 switch (*++c) 4129 { 4130 case '%': 4131 func (stream, "%%"); 4132 break; 4133 4134 case 'u': 4135 if (thumb && ifthen_state) 4136 is_unpredictable = TRUE; 4137 4138 /* Fall through. */ 4139 case 'c': 4140 if (thumb && ifthen_state) 4141 func (stream, "%s", arm_conditional[IFTHEN_COND]); 4142 break; 4143 4144 case 'A': 4145 { 4146 static const unsigned char enc[16] = 4147 { 4148 0x4, 0x14, /* st4 0,1 */ 4149 0x4, /* st1 2 */ 4150 0x4, /* st2 3 */ 4151 0x3, /* st3 4 */ 4152 0x13, /* st3 5 */ 4153 0x3, /* st1 6 */ 4154 0x1, /* st1 7 */ 4155 0x2, /* st2 8 */ 4156 0x12, /* st2 9 */ 4157 0x2, /* st1 10 */ 4158 0, 0, 0, 0, 0 4159 }; 4160 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 4161 int rn = ((given >> 16) & 0xf); 4162 int rm = ((given >> 0) & 0xf); 4163 int align = ((given >> 4) & 0x3); 4164 int type = ((given >> 8) & 0xf); 4165 int n = enc[type] & 0xf; 4166 int stride = (enc[type] >> 4) + 1; 4167 int ix; 4168 4169 func (stream, "{"); 4170 if (stride > 1) 4171 for (ix = 0; ix != n; ix++) 4172 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride); 4173 else if (n == 1) 4174 func (stream, "d%d", rd); 4175 else 4176 func (stream, "d%d-d%d", rd, rd + n - 1); 4177 func (stream, "}, [%s", arm_regnames[rn]); 4178 if (align) 4179 func (stream, " :%d", 32 << align); 4180 func (stream, "]"); 4181 if (rm == 0xd) 4182 func (stream, "!"); 4183 else if (rm != 0xf) 4184 func (stream, ", %s", arm_regnames[rm]); 4185 } 4186 break; 4187 4188 case 'B': 4189 { 4190 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 4191 int rn = ((given >> 16) & 0xf); 4192 int rm = ((given >> 0) & 0xf); 4193 int idx_align = ((given >> 4) & 0xf); 4194 int align = 0; 4195 int size = ((given >> 10) & 0x3); 4196 int idx = idx_align >> (size + 1); 4197 int length = ((given >> 8) & 3) + 1; 4198 int stride = 1; 4199 int i; 4200 4201 if (length > 1 && size > 0) 4202 stride = (idx_align & (1 << size)) ? 2 : 1; 4203 4204 switch (length) 4205 { 4206 case 1: 4207 { 4208 int amask = (1 << size) - 1; 4209 if ((idx_align & (1 << size)) != 0) 4210 return FALSE; 4211 if (size > 0) 4212 { 4213 if ((idx_align & amask) == amask) 4214 align = 8 << size; 4215 else if ((idx_align & amask) != 0) 4216 return FALSE; 4217 } 4218 } 4219 break; 4220 4221 case 2: 4222 if (size == 2 && (idx_align & 2) != 0) 4223 return FALSE; 4224 align = (idx_align & 1) ? 16 << size : 0; 4225 break; 4226 4227 case 3: 4228 if ((size == 2 && (idx_align & 3) != 0) 4229 || (idx_align & 1) != 0) 4230 return FALSE; 4231 break; 4232 4233 case 4: 4234 if (size == 2) 4235 { 4236 if ((idx_align & 3) == 3) 4237 return FALSE; 4238 align = (idx_align & 3) * 64; 4239 } 4240 else 4241 align = (idx_align & 1) ? 32 << size : 0; 4242 break; 4243 4244 default: 4245 abort (); 4246 } 4247 4248 func (stream, "{"); 4249 for (i = 0; i < length; i++) 4250 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",", 4251 rd + i * stride, idx); 4252 func (stream, "}, [%s", arm_regnames[rn]); 4253 if (align) 4254 func (stream, " :%d", align); 4255 func (stream, "]"); 4256 if (rm == 0xd) 4257 func (stream, "!"); 4258 else if (rm != 0xf) 4259 func (stream, ", %s", arm_regnames[rm]); 4260 } 4261 break; 4262 4263 case 'C': 4264 { 4265 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 4266 int rn = ((given >> 16) & 0xf); 4267 int rm = ((given >> 0) & 0xf); 4268 int align = ((given >> 4) & 0x1); 4269 int size = ((given >> 6) & 0x3); 4270 int type = ((given >> 8) & 0x3); 4271 int n = type + 1; 4272 int stride = ((given >> 5) & 0x1); 4273 int ix; 4274 4275 if (stride && (n == 1)) 4276 n++; 4277 else 4278 stride++; 4279 4280 func (stream, "{"); 4281 if (stride > 1) 4282 for (ix = 0; ix != n; ix++) 4283 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride); 4284 else if (n == 1) 4285 func (stream, "d%d[]", rd); 4286 else 4287 func (stream, "d%d[]-d%d[]", rd, rd + n - 1); 4288 func (stream, "}, [%s", arm_regnames[rn]); 4289 if (align) 4290 { 4291 align = (8 * (type + 1)) << size; 4292 if (type == 3) 4293 align = (size > 1) ? align >> 1 : align; 4294 if (type == 2 || (type == 0 && !size)) 4295 func (stream, " :<bad align %d>", align); 4296 else 4297 func (stream, " :%d", align); 4298 } 4299 func (stream, "]"); 4300 if (rm == 0xd) 4301 func (stream, "!"); 4302 else if (rm != 0xf) 4303 func (stream, ", %s", arm_regnames[rm]); 4304 } 4305 break; 4306 4307 case 'D': 4308 { 4309 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10); 4310 int size = (given >> 20) & 3; 4311 int reg = raw_reg & ((4 << size) - 1); 4312 int ix = raw_reg >> size >> 2; 4313 4314 func (stream, "d%d[%d]", reg, ix); 4315 } 4316 break; 4317 4318 case 'E': 4319 /* Neon encoded constant for mov, mvn, vorr, vbic. */ 4320 { 4321 int bits = 0; 4322 int cmode = (given >> 8) & 0xf; 4323 int op = (given >> 5) & 0x1; 4324 unsigned long value = 0, hival = 0; 4325 unsigned shift; 4326 int size = 0; 4327 int isfloat = 0; 4328 4329 bits |= ((given >> 24) & 1) << 7; 4330 bits |= ((given >> 16) & 7) << 4; 4331 bits |= ((given >> 0) & 15) << 0; 4332 4333 if (cmode < 8) 4334 { 4335 shift = (cmode >> 1) & 3; 4336 value = (unsigned long) bits << (8 * shift); 4337 size = 32; 4338 } 4339 else if (cmode < 12) 4340 { 4341 shift = (cmode >> 1) & 1; 4342 value = (unsigned long) bits << (8 * shift); 4343 size = 16; 4344 } 4345 else if (cmode < 14) 4346 { 4347 shift = (cmode & 1) + 1; 4348 value = (unsigned long) bits << (8 * shift); 4349 value |= (1ul << (8 * shift)) - 1; 4350 size = 32; 4351 } 4352 else if (cmode == 14) 4353 { 4354 if (op) 4355 { 4356 /* Bit replication into bytes. */ 4357 int ix; 4358 unsigned long mask; 4359 4360 value = 0; 4361 hival = 0; 4362 for (ix = 7; ix >= 0; ix--) 4363 { 4364 mask = ((bits >> ix) & 1) ? 0xff : 0; 4365 if (ix <= 3) 4366 value = (value << 8) | mask; 4367 else 4368 hival = (hival << 8) | mask; 4369 } 4370 size = 64; 4371 } 4372 else 4373 { 4374 /* Byte replication. */ 4375 value = (unsigned long) bits; 4376 size = 8; 4377 } 4378 } 4379 else if (!op) 4380 { 4381 /* Floating point encoding. */ 4382 int tmp; 4383 4384 value = (unsigned long) (bits & 0x7f) << 19; 4385 value |= (unsigned long) (bits & 0x80) << 24; 4386 tmp = bits & 0x40 ? 0x3c : 0x40; 4387 value |= (unsigned long) tmp << 24; 4388 size = 32; 4389 isfloat = 1; 4390 } 4391 else 4392 { 4393 func (stream, "<illegal constant %.8x:%x:%x>", 4394 bits, cmode, op); 4395 size = 32; 4396 break; 4397 } 4398 switch (size) 4399 { 4400 case 8: 4401 func (stream, "#%ld\t; 0x%.2lx", value, value); 4402 break; 4403 4404 case 16: 4405 func (stream, "#%ld\t; 0x%.4lx", value, value); 4406 break; 4407 4408 case 32: 4409 if (isfloat) 4410 { 4411 unsigned char valbytes[4]; 4412 double fvalue; 4413 4414 /* Do this a byte at a time so we don't have to 4415 worry about the host's endianness. */ 4416 valbytes[0] = value & 0xff; 4417 valbytes[1] = (value >> 8) & 0xff; 4418 valbytes[2] = (value >> 16) & 0xff; 4419 valbytes[3] = (value >> 24) & 0xff; 4420 4421 floatformat_to_double 4422 (& floatformat_ieee_single_little, valbytes, 4423 & fvalue); 4424 4425 func (stream, "#%.7g\t; 0x%.8lx", fvalue, 4426 value); 4427 } 4428 else 4429 func (stream, "#%ld\t; 0x%.8lx", 4430 (long) (((value & 0x80000000L) != 0) 4431 ? value | ~0xffffffffL : value), 4432 value); 4433 break; 4434 4435 case 64: 4436 func (stream, "#0x%.8lx%.8lx", hival, value); 4437 break; 4438 4439 default: 4440 abort (); 4441 } 4442 } 4443 break; 4444 4445 case 'F': 4446 { 4447 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10); 4448 int num = (given >> 8) & 0x3; 4449 4450 if (!num) 4451 func (stream, "{d%d}", regno); 4452 else if (num + regno >= 32) 4453 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num); 4454 else 4455 func (stream, "{d%d-d%d}", regno, regno + num); 4456 } 4457 break; 4458 4459 4460 case '0': case '1': case '2': case '3': case '4': 4461 case '5': case '6': case '7': case '8': case '9': 4462 { 4463 int width; 4464 unsigned long value; 4465 4466 c = arm_decode_bitfield (c, given, &value, &width); 4467 4468 switch (*c) 4469 { 4470 case 'r': 4471 func (stream, "%s", arm_regnames[value]); 4472 break; 4473 case 'd': 4474 func (stream, "%ld", value); 4475 value_in_comment = value; 4476 break; 4477 case 'e': 4478 func (stream, "%ld", (1ul << width) - value); 4479 break; 4480 4481 case 'S': 4482 case 'T': 4483 case 'U': 4484 /* Various width encodings. */ 4485 { 4486 int base = 8 << (*c - 'S'); /* 8,16 or 32 */ 4487 int limit; 4488 unsigned low, high; 4489 4490 c++; 4491 if (*c >= '0' && *c <= '9') 4492 limit = *c - '0'; 4493 else if (*c >= 'a' && *c <= 'f') 4494 limit = *c - 'a' + 10; 4495 else 4496 abort (); 4497 low = limit >> 2; 4498 high = limit & 3; 4499 4500 if (value < low || value > high) 4501 func (stream, "<illegal width %d>", base << value); 4502 else 4503 func (stream, "%d", base << value); 4504 } 4505 break; 4506 case 'R': 4507 if (given & (1 << 6)) 4508 goto Q; 4509 /* FALLTHROUGH */ 4510 case 'D': 4511 func (stream, "d%ld", value); 4512 break; 4513 case 'Q': 4514 Q: 4515 if (value & 1) 4516 func (stream, "<illegal reg q%ld.5>", value >> 1); 4517 else 4518 func (stream, "q%ld", value >> 1); 4519 break; 4520 4521 case '`': 4522 c++; 4523 if (value == 0) 4524 func (stream, "%c", *c); 4525 break; 4526 case '\'': 4527 c++; 4528 if (value == ((1ul << width) - 1)) 4529 func (stream, "%c", *c); 4530 break; 4531 case '?': 4532 func (stream, "%c", c[(1 << width) - (int) value]); 4533 c += 1 << width; 4534 break; 4535 default: 4536 abort (); 4537 } 4538 break; 4539 4540 default: 4541 abort (); 4542 } 4543 } 4544 } 4545 else 4546 func (stream, "%c", *c); 4547 } 4548 4549 if (value_in_comment > 32 || value_in_comment < -16) 4550 func (stream, "\t; 0x%lx", value_in_comment); 4551 4552 if (is_unpredictable) 4553 func (stream, UNPREDICTABLE_INSTRUCTION); 4554 4555 return TRUE; 4556 } 4557 } 4558 return FALSE; 4559 } 4560 4561 /* Return the name of a v7A special register. */ 4562 4563 static const char * 4564 banked_regname (unsigned reg) 4565 { 4566 switch (reg) 4567 { 4568 case 15: return "CPSR"; 4569 case 32: return "R8_usr"; 4570 case 33: return "R9_usr"; 4571 case 34: return "R10_usr"; 4572 case 35: return "R11_usr"; 4573 case 36: return "R12_usr"; 4574 case 37: return "SP_usr"; 4575 case 38: return "LR_usr"; 4576 case 40: return "R8_fiq"; 4577 case 41: return "R9_fiq"; 4578 case 42: return "R10_fiq"; 4579 case 43: return "R11_fiq"; 4580 case 44: return "R12_fiq"; 4581 case 45: return "SP_fiq"; 4582 case 46: return "LR_fiq"; 4583 case 48: return "LR_irq"; 4584 case 49: return "SP_irq"; 4585 case 50: return "LR_svc"; 4586 case 51: return "SP_svc"; 4587 case 52: return "LR_abt"; 4588 case 53: return "SP_abt"; 4589 case 54: return "LR_und"; 4590 case 55: return "SP_und"; 4591 case 60: return "LR_mon"; 4592 case 61: return "SP_mon"; 4593 case 62: return "ELR_hyp"; 4594 case 63: return "SP_hyp"; 4595 case 79: return "SPSR"; 4596 case 110: return "SPSR_fiq"; 4597 case 112: return "SPSR_irq"; 4598 case 114: return "SPSR_svc"; 4599 case 116: return "SPSR_abt"; 4600 case 118: return "SPSR_und"; 4601 case 124: return "SPSR_mon"; 4602 case 126: return "SPSR_hyp"; 4603 default: return NULL; 4604 } 4605 } 4606 4607 /* Return the name of the DMB/DSB option. */ 4608 static const char * 4609 data_barrier_option (unsigned option) 4610 { 4611 switch (option & 0xf) 4612 { 4613 case 0xf: return "sy"; 4614 case 0xe: return "st"; 4615 case 0xd: return "ld"; 4616 case 0xb: return "ish"; 4617 case 0xa: return "ishst"; 4618 case 0x9: return "ishld"; 4619 case 0x7: return "un"; 4620 case 0x6: return "unst"; 4621 case 0x5: return "nshld"; 4622 case 0x3: return "osh"; 4623 case 0x2: return "oshst"; 4624 case 0x1: return "oshld"; 4625 default: return NULL; 4626 } 4627 } 4628 4629 /* Print one ARM instruction from PC on INFO->STREAM. */ 4630 4631 static void 4632 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) 4633 { 4634 const struct opcode32 *insn; 4635 void *stream = info->stream; 4636 fprintf_ftype func = info->fprintf_func; 4637 struct arm_private_data *private_data = info->private_data; 4638 4639 if (print_insn_coprocessor (pc, info, given, FALSE)) 4640 return; 4641 4642 if (print_insn_neon (info, given, FALSE)) 4643 return; 4644 4645 for (insn = arm_opcodes; insn->assembler; insn++) 4646 { 4647 if ((given & insn->mask) != insn->value) 4648 continue; 4649 4650 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features)) 4651 continue; 4652 4653 /* Special case: an instruction with all bits set in the condition field 4654 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask, 4655 or by the catchall at the end of the table. */ 4656 if ((given & 0xF0000000) != 0xF0000000 4657 || (insn->mask & 0xF0000000) == 0xF0000000 4658 || (insn->mask == 0 && insn->value == 0)) 4659 { 4660 unsigned long u_reg = 16; 4661 unsigned long U_reg = 16; 4662 bfd_boolean is_unpredictable = FALSE; 4663 signed long value_in_comment = 0; 4664 const char *c; 4665 4666 for (c = insn->assembler; *c; c++) 4667 { 4668 if (*c == '%') 4669 { 4670 bfd_boolean allow_unpredictable = FALSE; 4671 4672 switch (*++c) 4673 { 4674 case '%': 4675 func (stream, "%%"); 4676 break; 4677 4678 case 'a': 4679 value_in_comment = print_arm_address (pc, info, given); 4680 break; 4681 4682 case 'P': 4683 /* Set P address bit and use normal address 4684 printing routine. */ 4685 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT)); 4686 break; 4687 4688 case 'S': 4689 allow_unpredictable = TRUE; 4690 case 's': 4691 if ((given & 0x004f0000) == 0x004f0000) 4692 { 4693 /* PC relative with immediate offset. */ 4694 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf); 4695 4696 if (PRE_BIT_SET) 4697 { 4698 /* Elide positive zero offset. */ 4699 if (offset || NEGATIVE_BIT_SET) 4700 func (stream, "[pc, #%s%d]\t; ", 4701 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4702 else 4703 func (stream, "[pc]\t; "); 4704 if (NEGATIVE_BIT_SET) 4705 offset = -offset; 4706 info->print_address_func (offset + pc + 8, info); 4707 } 4708 else 4709 { 4710 /* Always show the offset. */ 4711 func (stream, "[pc], #%s%d", 4712 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4713 if (! allow_unpredictable) 4714 is_unpredictable = TRUE; 4715 } 4716 } 4717 else 4718 { 4719 int offset = ((given & 0xf00) >> 4) | (given & 0xf); 4720 4721 func (stream, "[%s", 4722 arm_regnames[(given >> 16) & 0xf]); 4723 4724 if (PRE_BIT_SET) 4725 { 4726 if (IMMEDIATE_BIT_SET) 4727 { 4728 /* Elide offset for non-writeback 4729 positive zero. */ 4730 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET 4731 || offset) 4732 func (stream, ", #%s%d", 4733 NEGATIVE_BIT_SET ? "-" : "", offset); 4734 4735 if (NEGATIVE_BIT_SET) 4736 offset = -offset; 4737 4738 value_in_comment = offset; 4739 } 4740 else 4741 { 4742 /* Register Offset or Register Pre-Indexed. */ 4743 func (stream, ", %s%s", 4744 NEGATIVE_BIT_SET ? "-" : "", 4745 arm_regnames[given & 0xf]); 4746 4747 /* Writing back to the register that is the source/ 4748 destination of the load/store is unpredictable. */ 4749 if (! allow_unpredictable 4750 && WRITEBACK_BIT_SET 4751 && ((given & 0xf) == ((given >> 12) & 0xf))) 4752 is_unpredictable = TRUE; 4753 } 4754 4755 func (stream, "]%s", 4756 WRITEBACK_BIT_SET ? "!" : ""); 4757 } 4758 else 4759 { 4760 if (IMMEDIATE_BIT_SET) 4761 { 4762 /* Immediate Post-indexed. */ 4763 /* PR 10924: Offset must be printed, even if it is zero. */ 4764 func (stream, "], #%s%d", 4765 NEGATIVE_BIT_SET ? "-" : "", offset); 4766 if (NEGATIVE_BIT_SET) 4767 offset = -offset; 4768 value_in_comment = offset; 4769 } 4770 else 4771 { 4772 /* Register Post-indexed. */ 4773 func (stream, "], %s%s", 4774 NEGATIVE_BIT_SET ? "-" : "", 4775 arm_regnames[given & 0xf]); 4776 4777 /* Writing back to the register that is the source/ 4778 destination of the load/store is unpredictable. */ 4779 if (! allow_unpredictable 4780 && (given & 0xf) == ((given >> 12) & 0xf)) 4781 is_unpredictable = TRUE; 4782 } 4783 4784 if (! allow_unpredictable) 4785 { 4786 /* Writeback is automatically implied by post- addressing. 4787 Setting the W bit is unnecessary and ARM specify it as 4788 being unpredictable. */ 4789 if (WRITEBACK_BIT_SET 4790 /* Specifying the PC register as the post-indexed 4791 registers is also unpredictable. */ 4792 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf))) 4793 is_unpredictable = TRUE; 4794 } 4795 } 4796 } 4797 break; 4798 4799 case 'b': 4800 { 4801 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000); 4802 info->print_address_func (disp * 4 + pc + 8, info); 4803 } 4804 break; 4805 4806 case 'c': 4807 if (((given >> 28) & 0xf) != 0xe) 4808 func (stream, "%s", 4809 arm_conditional [(given >> 28) & 0xf]); 4810 break; 4811 4812 case 'm': 4813 { 4814 int started = 0; 4815 int reg; 4816 4817 func (stream, "{"); 4818 for (reg = 0; reg < 16; reg++) 4819 if ((given & (1 << reg)) != 0) 4820 { 4821 if (started) 4822 func (stream, ", "); 4823 started = 1; 4824 func (stream, "%s", arm_regnames[reg]); 4825 } 4826 func (stream, "}"); 4827 if (! started) 4828 is_unpredictable = TRUE; 4829 } 4830 break; 4831 4832 case 'q': 4833 arm_decode_shift (given, func, stream, FALSE); 4834 break; 4835 4836 case 'o': 4837 if ((given & 0x02000000) != 0) 4838 { 4839 unsigned int rotate = (given & 0xf00) >> 7; 4840 unsigned int immed = (given & 0xff); 4841 unsigned int a, i; 4842 4843 a = (((immed << (32 - rotate)) 4844 | (immed >> rotate)) & 0xffffffff); 4845 /* If there is another encoding with smaller rotate, 4846 the rotate should be specified directly. */ 4847 for (i = 0; i < 32; i += 2) 4848 if ((a << i | a >> (32 - i)) <= 0xff) 4849 break; 4850 4851 if (i != rotate) 4852 func (stream, "#%d, %d", immed, rotate); 4853 else 4854 func (stream, "#%d", a); 4855 value_in_comment = a; 4856 } 4857 else 4858 arm_decode_shift (given, func, stream, TRUE); 4859 break; 4860 4861 case 'p': 4862 if ((given & 0x0000f000) == 0x0000f000) 4863 { 4864 arm_feature_set arm_ext_v6 = 4865 ARM_FEATURE_CORE_LOW (ARM_EXT_V6); 4866 4867 /* The p-variants of tst/cmp/cmn/teq are the pre-V6 4868 mechanism for setting PSR flag bits. They are 4869 obsolete in V6 onwards. */ 4870 if (! ARM_CPU_HAS_FEATURE (private_data->features, \ 4871 arm_ext_v6)) 4872 func (stream, "p"); 4873 else 4874 is_unpredictable = TRUE; 4875 } 4876 break; 4877 4878 case 't': 4879 if ((given & 0x01200000) == 0x00200000) 4880 func (stream, "t"); 4881 break; 4882 4883 case 'A': 4884 { 4885 int offset = given & 0xff; 4886 4887 value_in_comment = offset * 4; 4888 if (NEGATIVE_BIT_SET) 4889 value_in_comment = - value_in_comment; 4890 4891 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 4892 4893 if (PRE_BIT_SET) 4894 { 4895 if (offset) 4896 func (stream, ", #%d]%s", 4897 (int) value_in_comment, 4898 WRITEBACK_BIT_SET ? "!" : ""); 4899 else 4900 func (stream, "]"); 4901 } 4902 else 4903 { 4904 func (stream, "]"); 4905 4906 if (WRITEBACK_BIT_SET) 4907 { 4908 if (offset) 4909 func (stream, ", #%d", (int) value_in_comment); 4910 } 4911 else 4912 { 4913 func (stream, ", {%d}", (int) offset); 4914 value_in_comment = offset; 4915 } 4916 } 4917 } 4918 break; 4919 4920 case 'B': 4921 /* Print ARM V5 BLX(1) address: pc+25 bits. */ 4922 { 4923 bfd_vma address; 4924 bfd_vma offset = 0; 4925 4926 if (! NEGATIVE_BIT_SET) 4927 /* Is signed, hi bits should be ones. */ 4928 offset = (-1) ^ 0x00ffffff; 4929 4930 /* Offset is (SignExtend(offset field)<<2). */ 4931 offset += given & 0x00ffffff; 4932 offset <<= 2; 4933 address = offset + pc + 8; 4934 4935 if (given & 0x01000000) 4936 /* H bit allows addressing to 2-byte boundaries. */ 4937 address += 2; 4938 4939 info->print_address_func (address, info); 4940 } 4941 break; 4942 4943 case 'C': 4944 if ((given & 0x02000200) == 0x200) 4945 { 4946 const char * name; 4947 unsigned sysm = (given & 0x004f0000) >> 16; 4948 4949 sysm |= (given & 0x300) >> 4; 4950 name = banked_regname (sysm); 4951 4952 if (name != NULL) 4953 func (stream, "%s", name); 4954 else 4955 func (stream, "(UNDEF: %lu)", (unsigned long) sysm); 4956 } 4957 else 4958 { 4959 func (stream, "%cPSR_", 4960 (given & 0x00400000) ? 'S' : 'C'); 4961 if (given & 0x80000) 4962 func (stream, "f"); 4963 if (given & 0x40000) 4964 func (stream, "s"); 4965 if (given & 0x20000) 4966 func (stream, "x"); 4967 if (given & 0x10000) 4968 func (stream, "c"); 4969 } 4970 break; 4971 4972 case 'U': 4973 if ((given & 0xf0) == 0x60) 4974 { 4975 switch (given & 0xf) 4976 { 4977 case 0xf: func (stream, "sy"); break; 4978 default: 4979 func (stream, "#%d", (int) given & 0xf); 4980 break; 4981 } 4982 } 4983 else 4984 { 4985 const char * opt = data_barrier_option (given & 0xf); 4986 if (opt != NULL) 4987 func (stream, "%s", opt); 4988 else 4989 func (stream, "#%d", (int) given & 0xf); 4990 } 4991 break; 4992 4993 case '0': case '1': case '2': case '3': case '4': 4994 case '5': case '6': case '7': case '8': case '9': 4995 { 4996 int width; 4997 unsigned long value; 4998 4999 c = arm_decode_bitfield (c, given, &value, &width); 5000 5001 switch (*c) 5002 { 5003 case 'R': 5004 if (value == 15) 5005 is_unpredictable = TRUE; 5006 /* Fall through. */ 5007 case 'r': 5008 case 'T': 5009 /* We want register + 1 when decoding T. */ 5010 if (*c == 'T') 5011 ++value; 5012 5013 if (c[1] == 'u') 5014 { 5015 /* Eat the 'u' character. */ 5016 ++ c; 5017 5018 if (u_reg == value) 5019 is_unpredictable = TRUE; 5020 u_reg = value; 5021 } 5022 if (c[1] == 'U') 5023 { 5024 /* Eat the 'U' character. */ 5025 ++ c; 5026 5027 if (U_reg == value) 5028 is_unpredictable = TRUE; 5029 U_reg = value; 5030 } 5031 func (stream, "%s", arm_regnames[value]); 5032 break; 5033 case 'd': 5034 func (stream, "%ld", value); 5035 value_in_comment = value; 5036 break; 5037 case 'b': 5038 func (stream, "%ld", value * 8); 5039 value_in_comment = value * 8; 5040 break; 5041 case 'W': 5042 func (stream, "%ld", value + 1); 5043 value_in_comment = value + 1; 5044 break; 5045 case 'x': 5046 func (stream, "0x%08lx", value); 5047 5048 /* Some SWI instructions have special 5049 meanings. */ 5050 if ((given & 0x0fffffff) == 0x0FF00000) 5051 func (stream, "\t; IMB"); 5052 else if ((given & 0x0fffffff) == 0x0FF00001) 5053 func (stream, "\t; IMBRange"); 5054 break; 5055 case 'X': 5056 func (stream, "%01lx", value & 0xf); 5057 value_in_comment = value; 5058 break; 5059 case '`': 5060 c++; 5061 if (value == 0) 5062 func (stream, "%c", *c); 5063 break; 5064 case '\'': 5065 c++; 5066 if (value == ((1ul << width) - 1)) 5067 func (stream, "%c", *c); 5068 break; 5069 case '?': 5070 func (stream, "%c", c[(1 << width) - (int) value]); 5071 c += 1 << width; 5072 break; 5073 default: 5074 abort (); 5075 } 5076 break; 5077 5078 case 'e': 5079 { 5080 int imm; 5081 5082 imm = (given & 0xf) | ((given & 0xfff00) >> 4); 5083 func (stream, "%d", imm); 5084 value_in_comment = imm; 5085 } 5086 break; 5087 5088 case 'E': 5089 /* LSB and WIDTH fields of BFI or BFC. The machine- 5090 language instruction encodes LSB and MSB. */ 5091 { 5092 long msb = (given & 0x001f0000) >> 16; 5093 long lsb = (given & 0x00000f80) >> 7; 5094 long w = msb - lsb + 1; 5095 5096 if (w > 0) 5097 func (stream, "#%lu, #%lu", lsb, w); 5098 else 5099 func (stream, "(invalid: %lu:%lu)", lsb, msb); 5100 } 5101 break; 5102 5103 case 'R': 5104 /* Get the PSR/banked register name. */ 5105 { 5106 const char * name; 5107 unsigned sysm = (given & 0x004f0000) >> 16; 5108 5109 sysm |= (given & 0x300) >> 4; 5110 name = banked_regname (sysm); 5111 5112 if (name != NULL) 5113 func (stream, "%s", name); 5114 else 5115 func (stream, "(UNDEF: %lu)", (unsigned long) sysm); 5116 } 5117 break; 5118 5119 case 'V': 5120 /* 16-bit unsigned immediate from a MOVT or MOVW 5121 instruction, encoded in bits 0:11 and 15:19. */ 5122 { 5123 long hi = (given & 0x000f0000) >> 4; 5124 long lo = (given & 0x00000fff); 5125 long imm16 = hi | lo; 5126 5127 func (stream, "#%lu", imm16); 5128 value_in_comment = imm16; 5129 } 5130 break; 5131 5132 default: 5133 abort (); 5134 } 5135 } 5136 } 5137 else 5138 func (stream, "%c", *c); 5139 } 5140 5141 if (value_in_comment > 32 || value_in_comment < -16) 5142 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL)); 5143 5144 if (is_unpredictable) 5145 func (stream, UNPREDICTABLE_INSTRUCTION); 5146 5147 return; 5148 } 5149 } 5150 abort (); 5151 } 5152 5153 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */ 5154 5155 static void 5156 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) 5157 { 5158 const struct opcode16 *insn; 5159 void *stream = info->stream; 5160 fprintf_ftype func = info->fprintf_func; 5161 5162 for (insn = thumb_opcodes; insn->assembler; insn++) 5163 if ((given & insn->mask) == insn->value) 5164 { 5165 signed long value_in_comment = 0; 5166 const char *c = insn->assembler; 5167 5168 for (; *c; c++) 5169 { 5170 int domaskpc = 0; 5171 int domasklr = 0; 5172 5173 if (*c != '%') 5174 { 5175 func (stream, "%c", *c); 5176 continue; 5177 } 5178 5179 switch (*++c) 5180 { 5181 case '%': 5182 func (stream, "%%"); 5183 break; 5184 5185 case 'c': 5186 if (ifthen_state) 5187 func (stream, "%s", arm_conditional[IFTHEN_COND]); 5188 break; 5189 5190 case 'C': 5191 if (ifthen_state) 5192 func (stream, "%s", arm_conditional[IFTHEN_COND]); 5193 else 5194 func (stream, "s"); 5195 break; 5196 5197 case 'I': 5198 { 5199 unsigned int tmp; 5200 5201 ifthen_next_state = given & 0xff; 5202 for (tmp = given << 1; tmp & 0xf; tmp <<= 1) 5203 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t"); 5204 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]); 5205 } 5206 break; 5207 5208 case 'x': 5209 if (ifthen_next_state) 5210 func (stream, "\t; unpredictable branch in IT block\n"); 5211 break; 5212 5213 case 'X': 5214 if (ifthen_state) 5215 func (stream, "\t; unpredictable <IT:%s>", 5216 arm_conditional[IFTHEN_COND]); 5217 break; 5218 5219 case 'S': 5220 { 5221 long reg; 5222 5223 reg = (given >> 3) & 0x7; 5224 if (given & (1 << 6)) 5225 reg += 8; 5226 5227 func (stream, "%s", arm_regnames[reg]); 5228 } 5229 break; 5230 5231 case 'D': 5232 { 5233 long reg; 5234 5235 reg = given & 0x7; 5236 if (given & (1 << 7)) 5237 reg += 8; 5238 5239 func (stream, "%s", arm_regnames[reg]); 5240 } 5241 break; 5242 5243 case 'N': 5244 if (given & (1 << 8)) 5245 domasklr = 1; 5246 /* Fall through. */ 5247 case 'O': 5248 if (*c == 'O' && (given & (1 << 8))) 5249 domaskpc = 1; 5250 /* Fall through. */ 5251 case 'M': 5252 { 5253 int started = 0; 5254 int reg; 5255 5256 func (stream, "{"); 5257 5258 /* It would be nice if we could spot 5259 ranges, and generate the rS-rE format: */ 5260 for (reg = 0; (reg < 8); reg++) 5261 if ((given & (1 << reg)) != 0) 5262 { 5263 if (started) 5264 func (stream, ", "); 5265 started = 1; 5266 func (stream, "%s", arm_regnames[reg]); 5267 } 5268 5269 if (domasklr) 5270 { 5271 if (started) 5272 func (stream, ", "); 5273 started = 1; 5274 func (stream, "%s", arm_regnames[14] /* "lr" */); 5275 } 5276 5277 if (domaskpc) 5278 { 5279 if (started) 5280 func (stream, ", "); 5281 func (stream, "%s", arm_regnames[15] /* "pc" */); 5282 } 5283 5284 func (stream, "}"); 5285 } 5286 break; 5287 5288 case 'W': 5289 /* Print writeback indicator for a LDMIA. We are doing a 5290 writeback if the base register is not in the register 5291 mask. */ 5292 if ((given & (1 << ((given & 0x0700) >> 8))) == 0) 5293 func (stream, "!"); 5294 break; 5295 5296 case 'b': 5297 /* Print ARM V6T2 CZB address: pc+4+6 bits. */ 5298 { 5299 bfd_vma address = (pc + 4 5300 + ((given & 0x00f8) >> 2) 5301 + ((given & 0x0200) >> 3)); 5302 info->print_address_func (address, info); 5303 } 5304 break; 5305 5306 case 's': 5307 /* Right shift immediate -- bits 6..10; 1-31 print 5308 as themselves, 0 prints as 32. */ 5309 { 5310 long imm = (given & 0x07c0) >> 6; 5311 if (imm == 0) 5312 imm = 32; 5313 func (stream, "#%ld", imm); 5314 } 5315 break; 5316 5317 case '0': case '1': case '2': case '3': case '4': 5318 case '5': case '6': case '7': case '8': case '9': 5319 { 5320 int bitstart = *c++ - '0'; 5321 int bitend = 0; 5322 5323 while (*c >= '0' && *c <= '9') 5324 bitstart = (bitstart * 10) + *c++ - '0'; 5325 5326 switch (*c) 5327 { 5328 case '-': 5329 { 5330 bfd_vma reg; 5331 5332 c++; 5333 while (*c >= '0' && *c <= '9') 5334 bitend = (bitend * 10) + *c++ - '0'; 5335 if (!bitend) 5336 abort (); 5337 reg = given >> bitstart; 5338 reg &= (2 << (bitend - bitstart)) - 1; 5339 5340 switch (*c) 5341 { 5342 case 'r': 5343 func (stream, "%s", arm_regnames[reg]); 5344 break; 5345 5346 case 'd': 5347 func (stream, "%ld", (long) reg); 5348 value_in_comment = reg; 5349 break; 5350 5351 case 'H': 5352 func (stream, "%ld", (long) (reg << 1)); 5353 value_in_comment = reg << 1; 5354 break; 5355 5356 case 'W': 5357 func (stream, "%ld", (long) (reg << 2)); 5358 value_in_comment = reg << 2; 5359 break; 5360 5361 case 'a': 5362 /* PC-relative address -- the bottom two 5363 bits of the address are dropped 5364 before the calculation. */ 5365 info->print_address_func 5366 (((pc + 4) & ~3) + (reg << 2), info); 5367 value_in_comment = 0; 5368 break; 5369 5370 case 'x': 5371 func (stream, "0x%04lx", (long) reg); 5372 break; 5373 5374 case 'B': 5375 reg = ((reg ^ (1 << bitend)) - (1 << bitend)); 5376 info->print_address_func (reg * 2 + pc + 4, info); 5377 value_in_comment = 0; 5378 break; 5379 5380 case 'c': 5381 func (stream, "%s", arm_conditional [reg]); 5382 break; 5383 5384 default: 5385 abort (); 5386 } 5387 } 5388 break; 5389 5390 case '\'': 5391 c++; 5392 if ((given & (1 << bitstart)) != 0) 5393 func (stream, "%c", *c); 5394 break; 5395 5396 case '?': 5397 ++c; 5398 if ((given & (1 << bitstart)) != 0) 5399 func (stream, "%c", *c++); 5400 else 5401 func (stream, "%c", *++c); 5402 break; 5403 5404 default: 5405 abort (); 5406 } 5407 } 5408 break; 5409 5410 default: 5411 abort (); 5412 } 5413 } 5414 5415 if (value_in_comment > 32 || value_in_comment < -16) 5416 func (stream, "\t; 0x%lx", value_in_comment); 5417 return; 5418 } 5419 5420 /* No match. */ 5421 abort (); 5422 } 5423 5424 /* Return the name of an V7M special register. */ 5425 5426 static const char * 5427 psr_name (int regno) 5428 { 5429 switch (regno) 5430 { 5431 case 0: return "APSR"; 5432 case 1: return "IAPSR"; 5433 case 2: return "EAPSR"; 5434 case 3: return "PSR"; 5435 case 5: return "IPSR"; 5436 case 6: return "EPSR"; 5437 case 7: return "IEPSR"; 5438 case 8: return "MSP"; 5439 case 9: return "PSP"; 5440 case 16: return "PRIMASK"; 5441 case 17: return "BASEPRI"; 5442 case 18: return "BASEPRI_MAX"; 5443 case 19: return "FAULTMASK"; 5444 case 20: return "CONTROL"; 5445 case 0x88: return "MSP_NS"; 5446 case 0x89: return "PSP_NS"; 5447 default: return "<unknown>"; 5448 } 5449 } 5450 5451 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */ 5452 5453 static void 5454 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) 5455 { 5456 const struct opcode32 *insn; 5457 void *stream = info->stream; 5458 fprintf_ftype func = info->fprintf_func; 5459 5460 if (print_insn_coprocessor (pc, info, given, TRUE)) 5461 return; 5462 5463 if (print_insn_neon (info, given, TRUE)) 5464 return; 5465 5466 for (insn = thumb32_opcodes; insn->assembler; insn++) 5467 if ((given & insn->mask) == insn->value) 5468 { 5469 bfd_boolean is_unpredictable = FALSE; 5470 signed long value_in_comment = 0; 5471 const char *c = insn->assembler; 5472 5473 for (; *c; c++) 5474 { 5475 if (*c != '%') 5476 { 5477 func (stream, "%c", *c); 5478 continue; 5479 } 5480 5481 switch (*++c) 5482 { 5483 case '%': 5484 func (stream, "%%"); 5485 break; 5486 5487 case 'c': 5488 if (ifthen_state) 5489 func (stream, "%s", arm_conditional[IFTHEN_COND]); 5490 break; 5491 5492 case 'x': 5493 if (ifthen_next_state) 5494 func (stream, "\t; unpredictable branch in IT block\n"); 5495 break; 5496 5497 case 'X': 5498 if (ifthen_state) 5499 func (stream, "\t; unpredictable <IT:%s>", 5500 arm_conditional[IFTHEN_COND]); 5501 break; 5502 5503 case 'I': 5504 { 5505 unsigned int imm12 = 0; 5506 5507 imm12 |= (given & 0x000000ffu); 5508 imm12 |= (given & 0x00007000u) >> 4; 5509 imm12 |= (given & 0x04000000u) >> 15; 5510 func (stream, "#%u", imm12); 5511 value_in_comment = imm12; 5512 } 5513 break; 5514 5515 case 'M': 5516 { 5517 unsigned int bits = 0, imm, imm8, mod; 5518 5519 bits |= (given & 0x000000ffu); 5520 bits |= (given & 0x00007000u) >> 4; 5521 bits |= (given & 0x04000000u) >> 15; 5522 imm8 = (bits & 0x0ff); 5523 mod = (bits & 0xf00) >> 8; 5524 switch (mod) 5525 { 5526 case 0: imm = imm8; break; 5527 case 1: imm = ((imm8 << 16) | imm8); break; 5528 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break; 5529 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break; 5530 default: 5531 mod = (bits & 0xf80) >> 7; 5532 imm8 = (bits & 0x07f) | 0x80; 5533 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff); 5534 } 5535 func (stream, "#%u", imm); 5536 value_in_comment = imm; 5537 } 5538 break; 5539 5540 case 'J': 5541 { 5542 unsigned int imm = 0; 5543 5544 imm |= (given & 0x000000ffu); 5545 imm |= (given & 0x00007000u) >> 4; 5546 imm |= (given & 0x04000000u) >> 15; 5547 imm |= (given & 0x000f0000u) >> 4; 5548 func (stream, "#%u", imm); 5549 value_in_comment = imm; 5550 } 5551 break; 5552 5553 case 'K': 5554 { 5555 unsigned int imm = 0; 5556 5557 imm |= (given & 0x000f0000u) >> 16; 5558 imm |= (given & 0x00000ff0u) >> 0; 5559 imm |= (given & 0x0000000fu) << 12; 5560 func (stream, "#%u", imm); 5561 value_in_comment = imm; 5562 } 5563 break; 5564 5565 case 'H': 5566 { 5567 unsigned int imm = 0; 5568 5569 imm |= (given & 0x000f0000u) >> 4; 5570 imm |= (given & 0x00000fffu) >> 0; 5571 func (stream, "#%u", imm); 5572 value_in_comment = imm; 5573 } 5574 break; 5575 5576 case 'V': 5577 { 5578 unsigned int imm = 0; 5579 5580 imm |= (given & 0x00000fffu); 5581 imm |= (given & 0x000f0000u) >> 4; 5582 func (stream, "#%u", imm); 5583 value_in_comment = imm; 5584 } 5585 break; 5586 5587 case 'S': 5588 { 5589 unsigned int reg = (given & 0x0000000fu); 5590 unsigned int stp = (given & 0x00000030u) >> 4; 5591 unsigned int imm = 0; 5592 imm |= (given & 0x000000c0u) >> 6; 5593 imm |= (given & 0x00007000u) >> 10; 5594 5595 func (stream, "%s", arm_regnames[reg]); 5596 switch (stp) 5597 { 5598 case 0: 5599 if (imm > 0) 5600 func (stream, ", lsl #%u", imm); 5601 break; 5602 5603 case 1: 5604 if (imm == 0) 5605 imm = 32; 5606 func (stream, ", lsr #%u", imm); 5607 break; 5608 5609 case 2: 5610 if (imm == 0) 5611 imm = 32; 5612 func (stream, ", asr #%u", imm); 5613 break; 5614 5615 case 3: 5616 if (imm == 0) 5617 func (stream, ", rrx"); 5618 else 5619 func (stream, ", ror #%u", imm); 5620 } 5621 } 5622 break; 5623 5624 case 'a': 5625 { 5626 unsigned int Rn = (given & 0x000f0000) >> 16; 5627 unsigned int U = ! NEGATIVE_BIT_SET; 5628 unsigned int op = (given & 0x00000f00) >> 8; 5629 unsigned int i12 = (given & 0x00000fff); 5630 unsigned int i8 = (given & 0x000000ff); 5631 bfd_boolean writeback = FALSE, postind = FALSE; 5632 bfd_vma offset = 0; 5633 5634 func (stream, "[%s", arm_regnames[Rn]); 5635 if (U) /* 12-bit positive immediate offset. */ 5636 { 5637 offset = i12; 5638 if (Rn != 15) 5639 value_in_comment = offset; 5640 } 5641 else if (Rn == 15) /* 12-bit negative immediate offset. */ 5642 offset = - (int) i12; 5643 else if (op == 0x0) /* Shifted register offset. */ 5644 { 5645 unsigned int Rm = (i8 & 0x0f); 5646 unsigned int sh = (i8 & 0x30) >> 4; 5647 5648 func (stream, ", %s", arm_regnames[Rm]); 5649 if (sh) 5650 func (stream, ", lsl #%u", sh); 5651 func (stream, "]"); 5652 break; 5653 } 5654 else switch (op) 5655 { 5656 case 0xE: /* 8-bit positive immediate offset. */ 5657 offset = i8; 5658 break; 5659 5660 case 0xC: /* 8-bit negative immediate offset. */ 5661 offset = -i8; 5662 break; 5663 5664 case 0xF: /* 8-bit + preindex with wb. */ 5665 offset = i8; 5666 writeback = TRUE; 5667 break; 5668 5669 case 0xD: /* 8-bit - preindex with wb. */ 5670 offset = -i8; 5671 writeback = TRUE; 5672 break; 5673 5674 case 0xB: /* 8-bit + postindex. */ 5675 offset = i8; 5676 postind = TRUE; 5677 break; 5678 5679 case 0x9: /* 8-bit - postindex. */ 5680 offset = -i8; 5681 postind = TRUE; 5682 break; 5683 5684 default: 5685 func (stream, ", <undefined>]"); 5686 goto skip; 5687 } 5688 5689 if (postind) 5690 func (stream, "], #%d", (int) offset); 5691 else 5692 { 5693 if (offset) 5694 func (stream, ", #%d", (int) offset); 5695 func (stream, writeback ? "]!" : "]"); 5696 } 5697 5698 if (Rn == 15) 5699 { 5700 func (stream, "\t; "); 5701 info->print_address_func (((pc + 4) & ~3) + offset, info); 5702 } 5703 } 5704 skip: 5705 break; 5706 5707 case 'A': 5708 { 5709 unsigned int U = ! NEGATIVE_BIT_SET; 5710 unsigned int W = WRITEBACK_BIT_SET; 5711 unsigned int Rn = (given & 0x000f0000) >> 16; 5712 unsigned int off = (given & 0x000000ff); 5713 5714 func (stream, "[%s", arm_regnames[Rn]); 5715 5716 if (PRE_BIT_SET) 5717 { 5718 if (off || !U) 5719 { 5720 func (stream, ", #%c%u", U ? '+' : '-', off * 4); 5721 value_in_comment = off * 4 * U ? 1 : -1; 5722 } 5723 func (stream, "]"); 5724 if (W) 5725 func (stream, "!"); 5726 } 5727 else 5728 { 5729 func (stream, "], "); 5730 if (W) 5731 { 5732 func (stream, "#%c%u", U ? '+' : '-', off * 4); 5733 value_in_comment = off * 4 * U ? 1 : -1; 5734 } 5735 else 5736 { 5737 func (stream, "{%u}", off); 5738 value_in_comment = off; 5739 } 5740 } 5741 } 5742 break; 5743 5744 case 'w': 5745 { 5746 unsigned int Sbit = (given & 0x01000000) >> 24; 5747 unsigned int type = (given & 0x00600000) >> 21; 5748 5749 switch (type) 5750 { 5751 case 0: func (stream, Sbit ? "sb" : "b"); break; 5752 case 1: func (stream, Sbit ? "sh" : "h"); break; 5753 case 2: 5754 if (Sbit) 5755 func (stream, "??"); 5756 break; 5757 case 3: 5758 func (stream, "??"); 5759 break; 5760 } 5761 } 5762 break; 5763 5764 case 'm': 5765 { 5766 int started = 0; 5767 int reg; 5768 5769 func (stream, "{"); 5770 for (reg = 0; reg < 16; reg++) 5771 if ((given & (1 << reg)) != 0) 5772 { 5773 if (started) 5774 func (stream, ", "); 5775 started = 1; 5776 func (stream, "%s", arm_regnames[reg]); 5777 } 5778 func (stream, "}"); 5779 } 5780 break; 5781 5782 case 'E': 5783 { 5784 unsigned int msb = (given & 0x0000001f); 5785 unsigned int lsb = 0; 5786 5787 lsb |= (given & 0x000000c0u) >> 6; 5788 lsb |= (given & 0x00007000u) >> 10; 5789 func (stream, "#%u, #%u", lsb, msb - lsb + 1); 5790 } 5791 break; 5792 5793 case 'F': 5794 { 5795 unsigned int width = (given & 0x0000001f) + 1; 5796 unsigned int lsb = 0; 5797 5798 lsb |= (given & 0x000000c0u) >> 6; 5799 lsb |= (given & 0x00007000u) >> 10; 5800 func (stream, "#%u, #%u", lsb, width); 5801 } 5802 break; 5803 5804 case 'b': 5805 { 5806 unsigned int S = (given & 0x04000000u) >> 26; 5807 unsigned int J1 = (given & 0x00002000u) >> 13; 5808 unsigned int J2 = (given & 0x00000800u) >> 11; 5809 bfd_vma offset = 0; 5810 5811 offset |= !S << 20; 5812 offset |= J2 << 19; 5813 offset |= J1 << 18; 5814 offset |= (given & 0x003f0000) >> 4; 5815 offset |= (given & 0x000007ff) << 1; 5816 offset -= (1 << 20); 5817 5818 info->print_address_func (pc + 4 + offset, info); 5819 } 5820 break; 5821 5822 case 'B': 5823 { 5824 unsigned int S = (given & 0x04000000u) >> 26; 5825 unsigned int I1 = (given & 0x00002000u) >> 13; 5826 unsigned int I2 = (given & 0x00000800u) >> 11; 5827 bfd_vma offset = 0; 5828 5829 offset |= !S << 24; 5830 offset |= !(I1 ^ S) << 23; 5831 offset |= !(I2 ^ S) << 22; 5832 offset |= (given & 0x03ff0000u) >> 4; 5833 offset |= (given & 0x000007ffu) << 1; 5834 offset -= (1 << 24); 5835 offset += pc + 4; 5836 5837 /* BLX target addresses are always word aligned. */ 5838 if ((given & 0x00001000u) == 0) 5839 offset &= ~2u; 5840 5841 info->print_address_func (offset, info); 5842 } 5843 break; 5844 5845 case 's': 5846 { 5847 unsigned int shift = 0; 5848 5849 shift |= (given & 0x000000c0u) >> 6; 5850 shift |= (given & 0x00007000u) >> 10; 5851 if (WRITEBACK_BIT_SET) 5852 func (stream, ", asr #%u", shift); 5853 else if (shift) 5854 func (stream, ", lsl #%u", shift); 5855 /* else print nothing - lsl #0 */ 5856 } 5857 break; 5858 5859 case 'R': 5860 { 5861 unsigned int rot = (given & 0x00000030) >> 4; 5862 5863 if (rot) 5864 func (stream, ", ror #%u", rot * 8); 5865 } 5866 break; 5867 5868 case 'U': 5869 if ((given & 0xf0) == 0x60) 5870 { 5871 switch (given & 0xf) 5872 { 5873 case 0xf: func (stream, "sy"); break; 5874 default: 5875 func (stream, "#%d", (int) given & 0xf); 5876 break; 5877 } 5878 } 5879 else 5880 { 5881 const char * opt = data_barrier_option (given & 0xf); 5882 if (opt != NULL) 5883 func (stream, "%s", opt); 5884 else 5885 func (stream, "#%d", (int) given & 0xf); 5886 } 5887 break; 5888 5889 case 'C': 5890 if ((given & 0xff) == 0) 5891 { 5892 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C'); 5893 if (given & 0x800) 5894 func (stream, "f"); 5895 if (given & 0x400) 5896 func (stream, "s"); 5897 if (given & 0x200) 5898 func (stream, "x"); 5899 if (given & 0x100) 5900 func (stream, "c"); 5901 } 5902 else if ((given & 0x20) == 0x20) 5903 { 5904 char const* name; 5905 unsigned sysm = (given & 0xf00) >> 8; 5906 5907 sysm |= (given & 0x30); 5908 sysm |= (given & 0x00100000) >> 14; 5909 name = banked_regname (sysm); 5910 5911 if (name != NULL) 5912 func (stream, "%s", name); 5913 else 5914 func (stream, "(UNDEF: %lu)", (unsigned long) sysm); 5915 } 5916 else 5917 { 5918 func (stream, "%s", psr_name (given & 0xff)); 5919 } 5920 break; 5921 5922 case 'D': 5923 if (((given & 0xff) == 0) 5924 || ((given & 0x20) == 0x20)) 5925 { 5926 char const* name; 5927 unsigned sm = (given & 0xf0000) >> 16; 5928 5929 sm |= (given & 0x30); 5930 sm |= (given & 0x00100000) >> 14; 5931 name = banked_regname (sm); 5932 5933 if (name != NULL) 5934 func (stream, "%s", name); 5935 else 5936 func (stream, "(UNDEF: %lu)", (unsigned long) sm); 5937 } 5938 else 5939 func (stream, "%s", psr_name (given & 0xff)); 5940 break; 5941 5942 case '0': case '1': case '2': case '3': case '4': 5943 case '5': case '6': case '7': case '8': case '9': 5944 { 5945 int width; 5946 unsigned long val; 5947 5948 c = arm_decode_bitfield (c, given, &val, &width); 5949 5950 switch (*c) 5951 { 5952 case 'd': 5953 func (stream, "%lu", val); 5954 value_in_comment = val; 5955 break; 5956 5957 case 'D': 5958 func (stream, "%lu", val + 1); 5959 value_in_comment = val + 1; 5960 break; 5961 5962 case 'W': 5963 func (stream, "%lu", val * 4); 5964 value_in_comment = val * 4; 5965 break; 5966 5967 case 'S': 5968 if (val == 13) 5969 is_unpredictable = TRUE; 5970 /* Fall through. */ 5971 case 'R': 5972 if (val == 15) 5973 is_unpredictable = TRUE; 5974 /* Fall through. */ 5975 case 'r': 5976 func (stream, "%s", arm_regnames[val]); 5977 break; 5978 5979 case 'c': 5980 func (stream, "%s", arm_conditional[val]); 5981 break; 5982 5983 case '\'': 5984 c++; 5985 if (val == ((1ul << width) - 1)) 5986 func (stream, "%c", *c); 5987 break; 5988 5989 case '`': 5990 c++; 5991 if (val == 0) 5992 func (stream, "%c", *c); 5993 break; 5994 5995 case '?': 5996 func (stream, "%c", c[(1 << width) - (int) val]); 5997 c += 1 << width; 5998 break; 5999 6000 case 'x': 6001 func (stream, "0x%lx", val & 0xffffffffUL); 6002 break; 6003 6004 default: 6005 abort (); 6006 } 6007 } 6008 break; 6009 6010 case 'L': 6011 /* PR binutils/12534 6012 If we have a PC relative offset in an LDRD or STRD 6013 instructions then display the decoded address. */ 6014 if (((given >> 16) & 0xf) == 0xf) 6015 { 6016 bfd_vma offset = (given & 0xff) * 4; 6017 6018 if ((given & (1 << 23)) == 0) 6019 offset = - offset; 6020 func (stream, "\t; "); 6021 info->print_address_func ((pc & ~3) + 4 + offset, info); 6022 } 6023 break; 6024 6025 default: 6026 abort (); 6027 } 6028 } 6029 6030 if (value_in_comment > 32 || value_in_comment < -16) 6031 func (stream, "\t; 0x%lx", value_in_comment); 6032 6033 if (is_unpredictable) 6034 func (stream, UNPREDICTABLE_INSTRUCTION); 6035 6036 return; 6037 } 6038 6039 /* No match. */ 6040 abort (); 6041 } 6042 6043 /* Print data bytes on INFO->STREAM. */ 6044 6045 static void 6046 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, 6047 struct disassemble_info *info, 6048 long given) 6049 { 6050 switch (info->bytes_per_chunk) 6051 { 6052 case 1: 6053 info->fprintf_func (info->stream, ".byte\t0x%02lx", given); 6054 break; 6055 case 2: 6056 info->fprintf_func (info->stream, ".short\t0x%04lx", given); 6057 break; 6058 case 4: 6059 info->fprintf_func (info->stream, ".word\t0x%08lx", given); 6060 break; 6061 default: 6062 abort (); 6063 } 6064 } 6065 6066 /* Disallow mapping symbols ($a, $b, $d, $t etc) from 6067 being displayed in symbol relative addresses. 6068 6069 Also disallow private symbol, with __tagsym$$ prefix, 6070 from ARM RVCT toolchain being displayed. */ 6071 6072 bfd_boolean 6073 arm_symbol_is_valid (asymbol * sym, 6074 struct disassemble_info * info ATTRIBUTE_UNUSED) 6075 { 6076 const char * name; 6077 6078 if (sym == NULL) 6079 return FALSE; 6080 6081 name = bfd_asymbol_name (sym); 6082 6083 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10)); 6084 } 6085 6086 /* Parse an individual disassembler option. */ 6087 6088 void 6089 parse_arm_disassembler_option (char *option) 6090 { 6091 if (option == NULL) 6092 return; 6093 6094 if (CONST_STRNEQ (option, "reg-names-")) 6095 { 6096 int i; 6097 6098 option += 10; 6099 6100 for (i = NUM_ARM_REGNAMES; i--;) 6101 if (strneq (option, regnames[i].name, strlen (regnames[i].name))) 6102 { 6103 regname_selected = i; 6104 break; 6105 } 6106 6107 if (i < 0) 6108 /* XXX - should break 'option' at following delimiter. */ 6109 fprintf (stderr, _("Unrecognised register name set: %s\n"), option); 6110 } 6111 else if (CONST_STRNEQ (option, "force-thumb")) 6112 force_thumb = 1; 6113 else if (CONST_STRNEQ (option, "no-force-thumb")) 6114 force_thumb = 0; 6115 else 6116 /* XXX - should break 'option' at following delimiter. */ 6117 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option); 6118 6119 return; 6120 } 6121 6122 /* Parse the string of disassembler options, spliting it at whitespaces 6123 or commas. (Whitespace separators supported for backwards compatibility). */ 6124 6125 static void 6126 parse_disassembler_options (char *options) 6127 { 6128 if (options == NULL) 6129 return; 6130 6131 while (*options) 6132 { 6133 parse_arm_disassembler_option (options); 6134 6135 /* Skip forward to next seperator. */ 6136 while ((*options) && (! ISSPACE (*options)) && (*options != ',')) 6137 ++ options; 6138 /* Skip forward past seperators. */ 6139 while (ISSPACE (*options) || (*options == ',')) 6140 ++ options; 6141 } 6142 } 6143 6144 static bfd_boolean 6145 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info, 6146 enum map_type *map_symbol); 6147 6148 /* Search back through the insn stream to determine if this instruction is 6149 conditionally executed. */ 6150 6151 static void 6152 find_ifthen_state (bfd_vma pc, 6153 struct disassemble_info *info, 6154 bfd_boolean little) 6155 { 6156 unsigned char b[2]; 6157 unsigned int insn; 6158 int status; 6159 /* COUNT is twice the number of instructions seen. It will be odd if we 6160 just crossed an instruction boundary. */ 6161 int count; 6162 int it_count; 6163 unsigned int seen_it; 6164 bfd_vma addr; 6165 6166 ifthen_address = pc; 6167 ifthen_state = 0; 6168 6169 addr = pc; 6170 count = 1; 6171 it_count = 0; 6172 seen_it = 0; 6173 /* Scan backwards looking for IT instructions, keeping track of where 6174 instruction boundaries are. We don't know if something is actually an 6175 IT instruction until we find a definite instruction boundary. */ 6176 for (;;) 6177 { 6178 if (addr == 0 || info->symbol_at_address_func (addr, info)) 6179 { 6180 /* A symbol must be on an instruction boundary, and will not 6181 be within an IT block. */ 6182 if (seen_it && (count & 1)) 6183 break; 6184 6185 return; 6186 } 6187 addr -= 2; 6188 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info); 6189 if (status) 6190 return; 6191 6192 if (little) 6193 insn = (b[0]) | (b[1] << 8); 6194 else 6195 insn = (b[1]) | (b[0] << 8); 6196 if (seen_it) 6197 { 6198 if ((insn & 0xf800) < 0xe800) 6199 { 6200 /* Addr + 2 is an instruction boundary. See if this matches 6201 the expected boundary based on the position of the last 6202 IT candidate. */ 6203 if (count & 1) 6204 break; 6205 seen_it = 0; 6206 } 6207 } 6208 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0) 6209 { 6210 enum map_type type = MAP_ARM; 6211 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type); 6212 6213 if (!found || (found && type == MAP_THUMB)) 6214 { 6215 /* This could be an IT instruction. */ 6216 seen_it = insn; 6217 it_count = count >> 1; 6218 } 6219 } 6220 if ((insn & 0xf800) >= 0xe800) 6221 count++; 6222 else 6223 count = (count + 2) | 1; 6224 /* IT blocks contain at most 4 instructions. */ 6225 if (count >= 8 && !seen_it) 6226 return; 6227 } 6228 /* We found an IT instruction. */ 6229 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f); 6230 if ((ifthen_state & 0xf) == 0) 6231 ifthen_state = 0; 6232 } 6233 6234 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a 6235 mapping symbol. */ 6236 6237 static int 6238 is_mapping_symbol (struct disassemble_info *info, int n, 6239 enum map_type *map_type) 6240 { 6241 const char *name; 6242 6243 name = bfd_asymbol_name (info->symtab[n]); 6244 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd') 6245 && (name[2] == 0 || name[2] == '.')) 6246 { 6247 *map_type = ((name[1] == 'a') ? MAP_ARM 6248 : (name[1] == 't') ? MAP_THUMB 6249 : MAP_DATA); 6250 return TRUE; 6251 } 6252 6253 return FALSE; 6254 } 6255 6256 /* Try to infer the code type (ARM or Thumb) from a mapping symbol. 6257 Returns nonzero if *MAP_TYPE was set. */ 6258 6259 static int 6260 get_map_sym_type (struct disassemble_info *info, 6261 int n, 6262 enum map_type *map_type) 6263 { 6264 /* If the symbol is in a different section, ignore it. */ 6265 if (info->section != NULL && info->section != info->symtab[n]->section) 6266 return FALSE; 6267 6268 return is_mapping_symbol (info, n, map_type); 6269 } 6270 6271 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol. 6272 Returns nonzero if *MAP_TYPE was set. */ 6273 6274 static int 6275 get_sym_code_type (struct disassemble_info *info, 6276 int n, 6277 enum map_type *map_type) 6278 { 6279 elf_symbol_type *es; 6280 unsigned int type; 6281 6282 /* If the symbol is in a different section, ignore it. */ 6283 if (info->section != NULL && info->section != info->symtab[n]->section) 6284 return FALSE; 6285 6286 es = *(elf_symbol_type **)(info->symtab + n); 6287 type = ELF_ST_TYPE (es->internal_elf_sym.st_info); 6288 6289 /* If the symbol has function type then use that. */ 6290 if (type == STT_FUNC || type == STT_GNU_IFUNC) 6291 { 6292 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal) 6293 == ST_BRANCH_TO_THUMB) 6294 *map_type = MAP_THUMB; 6295 else 6296 *map_type = MAP_ARM; 6297 return TRUE; 6298 } 6299 6300 return FALSE; 6301 } 6302 6303 /* Search the mapping symbol state for instruction at pc. This is only 6304 applicable for elf target. 6305 6306 There is an assumption Here, info->private_data contains the correct AND 6307 up-to-date information about current scan process. The information will be 6308 used to speed this search process. 6309 6310 Return TRUE if the mapping state can be determined, and map_symbol 6311 will be updated accordingly. Otherwise, return FALSE. */ 6312 6313 static bfd_boolean 6314 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info, 6315 enum map_type *map_symbol) 6316 { 6317 bfd_vma addr; 6318 int n, start = 0; 6319 bfd_boolean found = FALSE; 6320 enum map_type type = MAP_ARM; 6321 struct arm_private_data *private_data; 6322 6323 if (info->private_data == NULL || info->symtab_size == 0 6324 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour) 6325 return FALSE; 6326 6327 private_data = info->private_data; 6328 if (pc == 0) 6329 start = 0; 6330 else 6331 start = private_data->last_mapping_sym; 6332 6333 start = (start == -1)? 0 : start; 6334 addr = bfd_asymbol_value (info->symtab[start]); 6335 6336 if (pc >= addr) 6337 { 6338 if (get_map_sym_type (info, start, &type)) 6339 found = TRUE; 6340 } 6341 else 6342 { 6343 for (n = start - 1; n >= 0; n--) 6344 { 6345 if (get_map_sym_type (info, n, &type)) 6346 { 6347 found = TRUE; 6348 break; 6349 } 6350 } 6351 } 6352 6353 /* No mapping symbols were found. A leading $d may be 6354 omitted for sections which start with data; but for 6355 compatibility with legacy and stripped binaries, only 6356 assume the leading $d if there is at least one mapping 6357 symbol in the file. */ 6358 if (!found && private_data->has_mapping_symbols == 1) 6359 { 6360 type = MAP_DATA; 6361 found = TRUE; 6362 } 6363 6364 *map_symbol = type; 6365 return found; 6366 } 6367 6368 /* Given a bfd_mach_arm_XXX value, this function fills in the fields 6369 of the supplied arm_feature_set structure with bitmasks indicating 6370 the support base architectures and coprocessor extensions. 6371 6372 FIXME: This could more efficiently implemented as a constant array, 6373 although it would also be less robust. */ 6374 6375 static void 6376 select_arm_features (unsigned long mach, 6377 arm_feature_set * features) 6378 { 6379 #undef ARM_SET_FEATURES 6380 #define ARM_SET_FEATURES(FSET) \ 6381 { \ 6382 const arm_feature_set fset = FSET; \ 6383 arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \ 6384 ARM_MERGE_FEATURE_SETS (*features, tmp, fset); \ 6385 } 6386 6387 switch (mach) 6388 { 6389 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break; 6390 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break; 6391 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break; 6392 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break; 6393 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break; 6394 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break; 6395 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break; 6396 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break; 6397 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break; 6398 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break; 6399 case bfd_mach_arm_ep9312: 6400 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T, 6401 ARM_CEXT_MAVERICK | FPU_MAVERICK)); 6402 break; 6403 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break; 6404 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break; 6405 /* If the machine type is unknown allow all 6406 architecture types and all extensions. */ 6407 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break; 6408 default: 6409 abort (); 6410 } 6411 6412 #undef ARM_SET_FEATURES 6413 } 6414 6415 6416 /* NOTE: There are no checks in these routines that 6417 the relevant number of data bytes exist. */ 6418 6419 static int 6420 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) 6421 { 6422 unsigned char b[4]; 6423 long given; 6424 int status; 6425 int is_thumb = FALSE; 6426 int is_data = FALSE; 6427 int little_code; 6428 unsigned int size = 4; 6429 void (*printer) (bfd_vma, struct disassemble_info *, long); 6430 bfd_boolean found = FALSE; 6431 struct arm_private_data *private_data; 6432 6433 if (info->disassembler_options) 6434 { 6435 parse_disassembler_options (info->disassembler_options); 6436 6437 /* To avoid repeated parsing of these options, we remove them here. */ 6438 info->disassembler_options = NULL; 6439 } 6440 6441 /* PR 10288: Control which instructions will be disassembled. */ 6442 if (info->private_data == NULL) 6443 { 6444 static struct arm_private_data private; 6445 6446 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0) 6447 /* If the user did not use the -m command line switch then default to 6448 disassembling all types of ARM instruction. 6449 6450 The info->mach value has to be ignored as this will be based on 6451 the default archictecture for the target and/or hints in the notes 6452 section, but it will never be greater than the current largest arm 6453 machine value (iWMMXt2), which is only equivalent to the V5TE 6454 architecture. ARM architectures have advanced beyond the machine 6455 value encoding, and these newer architectures would be ignored if 6456 the machine value was used. 6457 6458 Ie the -m switch is used to restrict which instructions will be 6459 disassembled. If it is necessary to use the -m switch to tell 6460 objdump that an ARM binary is being disassembled, eg because the 6461 input is a raw binary file, but it is also desired to disassemble 6462 all ARM instructions then use "-marm". This will select the 6463 "unknown" arm architecture which is compatible with any ARM 6464 instruction. */ 6465 info->mach = bfd_mach_arm_unknown; 6466 6467 /* Compute the architecture bitmask from the machine number. 6468 Note: This assumes that the machine number will not change 6469 during disassembly.... */ 6470 select_arm_features (info->mach, & private.features); 6471 6472 private.has_mapping_symbols = -1; 6473 private.last_mapping_sym = -1; 6474 private.last_mapping_addr = 0; 6475 6476 info->private_data = & private; 6477 } 6478 6479 private_data = info->private_data; 6480 6481 /* Decide if our code is going to be little-endian, despite what the 6482 function argument might say. */ 6483 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little); 6484 6485 /* For ELF, consult the symbol table to determine what kind of code 6486 or data we have. */ 6487 if (info->symtab_size != 0 6488 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour) 6489 { 6490 bfd_vma addr; 6491 int n, start; 6492 int last_sym = -1; 6493 enum map_type type = MAP_ARM; 6494 6495 /* Start scanning at the start of the function, or wherever 6496 we finished last time. */ 6497 /* PR 14006. When the address is 0 we are either at the start of the 6498 very first function, or else the first function in a new, unlinked 6499 executable section (eg because of -ffunction-sections). Either way 6500 start scanning from the beginning of the symbol table, not where we 6501 left off last time. */ 6502 if (pc == 0) 6503 start = 0; 6504 else 6505 { 6506 start = info->symtab_pos + 1; 6507 if (start < private_data->last_mapping_sym) 6508 start = private_data->last_mapping_sym; 6509 } 6510 found = FALSE; 6511 6512 /* First, look for mapping symbols. */ 6513 if (private_data->has_mapping_symbols != 0) 6514 { 6515 /* Scan up to the location being disassembled. */ 6516 for (n = start; n < info->symtab_size; n++) 6517 { 6518 addr = bfd_asymbol_value (info->symtab[n]); 6519 if (addr > pc) 6520 break; 6521 if (get_map_sym_type (info, n, &type)) 6522 { 6523 last_sym = n; 6524 found = TRUE; 6525 } 6526 } 6527 6528 if (!found) 6529 { 6530 /* No mapping symbol found at this address. Look backwards 6531 for a preceding one. */ 6532 for (n = start - 1; n >= 0; n--) 6533 { 6534 if (get_map_sym_type (info, n, &type)) 6535 { 6536 last_sym = n; 6537 found = TRUE; 6538 break; 6539 } 6540 } 6541 } 6542 6543 if (found) 6544 private_data->has_mapping_symbols = 1; 6545 6546 /* No mapping symbols were found. A leading $d may be 6547 omitted for sections which start with data; but for 6548 compatibility with legacy and stripped binaries, only 6549 assume the leading $d if there is at least one mapping 6550 symbol in the file. */ 6551 if (!found && private_data->has_mapping_symbols == -1) 6552 { 6553 /* Look for mapping symbols, in any section. */ 6554 for (n = 0; n < info->symtab_size; n++) 6555 if (is_mapping_symbol (info, n, &type)) 6556 { 6557 private_data->has_mapping_symbols = 1; 6558 break; 6559 } 6560 if (private_data->has_mapping_symbols == -1) 6561 private_data->has_mapping_symbols = 0; 6562 } 6563 6564 if (!found && private_data->has_mapping_symbols == 1) 6565 { 6566 type = MAP_DATA; 6567 found = TRUE; 6568 } 6569 } 6570 6571 /* Next search for function symbols to separate ARM from Thumb 6572 in binaries without mapping symbols. */ 6573 if (!found) 6574 { 6575 /* Scan up to the location being disassembled. */ 6576 for (n = start; n < info->symtab_size; n++) 6577 { 6578 addr = bfd_asymbol_value (info->symtab[n]); 6579 if (addr > pc) 6580 break; 6581 if (get_sym_code_type (info, n, &type)) 6582 { 6583 last_sym = n; 6584 found = TRUE; 6585 } 6586 } 6587 6588 if (!found) 6589 { 6590 /* No mapping symbol found at this address. Look backwards 6591 for a preceding one. */ 6592 for (n = start - 1; n >= 0; n--) 6593 { 6594 if (get_sym_code_type (info, n, &type)) 6595 { 6596 last_sym = n; 6597 found = TRUE; 6598 break; 6599 } 6600 } 6601 } 6602 } 6603 6604 private_data->last_mapping_sym = last_sym; 6605 private_data->last_type = type; 6606 is_thumb = (private_data->last_type == MAP_THUMB); 6607 is_data = (private_data->last_type == MAP_DATA); 6608 6609 /* Look a little bit ahead to see if we should print out 6610 two or four bytes of data. If there's a symbol, 6611 mapping or otherwise, after two bytes then don't 6612 print more. */ 6613 if (is_data) 6614 { 6615 size = 4 - (pc & 3); 6616 for (n = last_sym + 1; n < info->symtab_size; n++) 6617 { 6618 addr = bfd_asymbol_value (info->symtab[n]); 6619 if (addr > pc 6620 && (info->section == NULL 6621 || info->section == info->symtab[n]->section)) 6622 { 6623 if (addr - pc < size) 6624 size = addr - pc; 6625 break; 6626 } 6627 } 6628 /* If the next symbol is after three bytes, we need to 6629 print only part of the data, so that we can use either 6630 .byte or .short. */ 6631 if (size == 3) 6632 size = (pc & 1) ? 1 : 2; 6633 } 6634 } 6635 6636 if (info->symbols != NULL) 6637 { 6638 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour) 6639 { 6640 coff_symbol_type * cs; 6641 6642 cs = coffsymbol (*info->symbols); 6643 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT 6644 || cs->native->u.syment.n_sclass == C_THUMBSTAT 6645 || cs->native->u.syment.n_sclass == C_THUMBLABEL 6646 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC 6647 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC); 6648 } 6649 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour 6650 && !found) 6651 { 6652 /* If no mapping symbol has been found then fall back to the type 6653 of the function symbol. */ 6654 elf_symbol_type * es; 6655 unsigned int type; 6656 6657 es = *(elf_symbol_type **)(info->symbols); 6658 type = ELF_ST_TYPE (es->internal_elf_sym.st_info); 6659 6660 is_thumb = 6661 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal) 6662 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT); 6663 } 6664 else if (bfd_asymbol_flavour (*info->symbols) 6665 == bfd_target_mach_o_flavour) 6666 { 6667 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols; 6668 6669 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF); 6670 } 6671 } 6672 6673 if (force_thumb) 6674 is_thumb = TRUE; 6675 6676 if (is_data) 6677 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 6678 else 6679 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 6680 6681 info->bytes_per_line = 4; 6682 6683 /* PR 10263: Disassemble data if requested to do so by the user. */ 6684 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0)) 6685 { 6686 int i; 6687 6688 /* Size was already set above. */ 6689 info->bytes_per_chunk = size; 6690 printer = print_insn_data; 6691 6692 status = info->read_memory_func (pc, (bfd_byte *) b, size, info); 6693 given = 0; 6694 if (little) 6695 for (i = size - 1; i >= 0; i--) 6696 given = b[i] | (given << 8); 6697 else 6698 for (i = 0; i < (int) size; i++) 6699 given = b[i] | (given << 8); 6700 } 6701 else if (!is_thumb) 6702 { 6703 /* In ARM mode endianness is a straightforward issue: the instruction 6704 is four bytes long and is either ordered 0123 or 3210. */ 6705 printer = print_insn_arm; 6706 info->bytes_per_chunk = 4; 6707 size = 4; 6708 6709 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info); 6710 if (little_code) 6711 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); 6712 else 6713 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24); 6714 } 6715 else 6716 { 6717 /* In Thumb mode we have the additional wrinkle of two 6718 instruction lengths. Fortunately, the bits that determine 6719 the length of the current instruction are always to be found 6720 in the first two bytes. */ 6721 printer = print_insn_thumb16; 6722 info->bytes_per_chunk = 2; 6723 size = 2; 6724 6725 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); 6726 if (little_code) 6727 given = (b[0]) | (b[1] << 8); 6728 else 6729 given = (b[1]) | (b[0] << 8); 6730 6731 if (!status) 6732 { 6733 /* These bit patterns signal a four-byte Thumb 6734 instruction. */ 6735 if ((given & 0xF800) == 0xF800 6736 || (given & 0xF800) == 0xF000 6737 || (given & 0xF800) == 0xE800) 6738 { 6739 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info); 6740 if (little_code) 6741 given = (b[0]) | (b[1] << 8) | (given << 16); 6742 else 6743 given = (b[1]) | (b[0] << 8) | (given << 16); 6744 6745 printer = print_insn_thumb32; 6746 size = 4; 6747 } 6748 } 6749 6750 if (ifthen_address != pc) 6751 find_ifthen_state (pc, info, little_code); 6752 6753 if (ifthen_state) 6754 { 6755 if ((ifthen_state & 0xf) == 0x8) 6756 ifthen_next_state = 0; 6757 else 6758 ifthen_next_state = (ifthen_state & 0xe0) 6759 | ((ifthen_state & 0xf) << 1); 6760 } 6761 } 6762 6763 if (status) 6764 { 6765 info->memory_error_func (status, pc, info); 6766 return -1; 6767 } 6768 if (info->flags & INSN_HAS_RELOC) 6769 /* If the instruction has a reloc associated with it, then 6770 the offset field in the instruction will actually be the 6771 addend for the reloc. (We are using REL type relocs). 6772 In such cases, we can ignore the pc when computing 6773 addresses, since the addend is not currently pc-relative. */ 6774 pc = 0; 6775 6776 printer (pc, info, given); 6777 6778 if (is_thumb) 6779 { 6780 ifthen_state = ifthen_next_state; 6781 ifthen_address += size; 6782 } 6783 return size; 6784 } 6785 6786 int 6787 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info) 6788 { 6789 /* Detect BE8-ness and record it in the disassembler info. */ 6790 if (info->flavour == bfd_target_elf_flavour 6791 && info->section != NULL 6792 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8)) 6793 info->endian_code = BFD_ENDIAN_LITTLE; 6794 6795 return print_insn (pc, info, FALSE); 6796 } 6797 6798 int 6799 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info) 6800 { 6801 return print_insn (pc, info, TRUE); 6802 } 6803 6804 void 6805 print_arm_disassembler_options (FILE *stream) 6806 { 6807 int i; 6808 6809 fprintf (stream, _("\n\ 6810 The following ARM specific disassembler options are supported for use with\n\ 6811 the -M switch:\n")); 6812 6813 for (i = NUM_ARM_REGNAMES; i--;) 6814 fprintf (stream, " reg-names-%s %*c%s\n", 6815 regnames[i].name, 6816 (int)(14 - strlen (regnames[i].name)), ' ', 6817 regnames[i].description); 6818 6819 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n"); 6820 fprintf (stream, " no-force-thumb Examine preceding label to determine an insn's type\n\n"); 6821 } 6822
