1 /* 2 * Copyright 2016 Red Hat. 3 * Copyright 2016 Bas Nieuwenhuizen 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 22 * IN THE SOFTWARE. 23 */ 24 25 #ifndef RADV_CS_H 26 #define RADV_CS_H 27 28 #include <string.h> 29 #include <stdint.h> 30 #include <assert.h> 31 #include "r600d_common.h" 32 33 static inline unsigned radeon_check_space(struct radeon_winsys *ws, 34 struct radeon_winsys_cs *cs, 35 unsigned needed) 36 { 37 if (cs->max_dw - cs->cdw < needed) 38 ws->cs_grow(cs, needed); 39 return cs->cdw + needed; 40 } 41 42 static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 43 { 44 assert(reg < R600_CONTEXT_REG_OFFSET); 45 assert(cs->cdw + 2 + num <= cs->max_dw); 46 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0)); 47 radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2); 48 } 49 50 static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 51 { 52 radeon_set_config_reg_seq(cs, reg, 1); 53 radeon_emit(cs, value); 54 } 55 56 static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 57 { 58 assert(reg >= R600_CONTEXT_REG_OFFSET); 59 assert(cs->cdw + 2 + num <= cs->max_dw); 60 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0)); 61 radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2); 62 } 63 64 static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 65 { 66 radeon_set_context_reg_seq(cs, reg, 1); 67 radeon_emit(cs, value); 68 } 69 70 71 static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs, 72 unsigned reg, unsigned idx, 73 unsigned value) 74 { 75 assert(reg >= R600_CONTEXT_REG_OFFSET); 76 assert(cs->cdw + 3 <= cs->max_dw); 77 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); 78 radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2 | (idx << 28)); 79 radeon_emit(cs, value); 80 } 81 82 static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 83 { 84 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END); 85 assert(cs->cdw + 2 + num <= cs->max_dw); 86 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0)); 87 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2); 88 } 89 90 static inline void radeon_set_sh_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 91 { 92 radeon_set_sh_reg_seq(cs, reg, 1); 93 radeon_emit(cs, value); 94 } 95 96 static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 97 { 98 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); 99 assert(cs->cdw + 2 + num <= cs->max_dw); 100 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0)); 101 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2); 102 } 103 104 static inline void radeon_set_uconfig_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 105 { 106 radeon_set_uconfig_reg_seq(cs, reg, 1); 107 radeon_emit(cs, value); 108 } 109 110 static inline void radeon_set_uconfig_reg_idx(struct radeon_winsys_cs *cs, 111 unsigned reg, unsigned idx, 112 unsigned value) 113 { 114 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); 115 assert(cs->cdw + 3 <= cs->max_dw); 116 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0)); 117 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28)); 118 radeon_emit(cs, value); 119 } 120 121 #endif /* RADV_CS_H */ 122
