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      1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file implements the AArch64 specific subclass of TargetSubtarget.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "AArch64Subtarget.h"
     15 #include "AArch64InstrInfo.h"
     16 #include "AArch64PBQPRegAlloc.h"
     17 #include "llvm/CodeGen/MachineScheduler.h"
     18 #include "llvm/IR/GlobalValue.h"
     19 #include "llvm/Support/TargetRegistry.h"
     20 
     21 using namespace llvm;
     22 
     23 #define DEBUG_TYPE "aarch64-subtarget"
     24 
     25 #define GET_SUBTARGETINFO_CTOR
     26 #define GET_SUBTARGETINFO_TARGET_DESC
     27 #include "AArch64GenSubtargetInfo.inc"
     28 
     29 static cl::opt<bool>
     30 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
     31                      "converter pass"), cl::init(true), cl::Hidden);
     32 
     33 // If OS supports TBI, use this flag to enable it.
     34 static cl::opt<bool>
     35 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
     36                          "an address is ignored"), cl::init(false), cl::Hidden);
     37 
     38 AArch64Subtarget &
     39 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS) {
     40   // Determine default and user-specified characteristics
     41 
     42   if (CPUString.empty())
     43     CPUString = "generic";
     44 
     45   ParseSubtargetFeatures(CPUString, FS);
     46   initializeProperties();
     47 
     48   return *this;
     49 }
     50 
     51 void AArch64Subtarget::initializeProperties() {
     52   // Initialize CPU specific properties. We should add a tablegen feature for
     53   // this in the future so we can specify it together with the subtarget
     54   // features.
     55   switch (ARMProcFamily) {
     56   case Cyclone:
     57     CacheLineSize = 64;
     58     PrefetchDistance = 280;
     59     MinPrefetchStride = 2048;
     60     MaxPrefetchIterationsAhead = 3;
     61     break;
     62   case CortexA57:
     63     MaxInterleaveFactor = 4;
     64     break;
     65   case ExynosM1:
     66     PrefFunctionAlignment = 4;
     67     PrefLoopAlignment = 3;
     68     break;
     69   case Kryo:
     70     MaxInterleaveFactor = 4;
     71     VectorInsertExtractBaseCost = 2;
     72     CacheLineSize = 128;
     73     PrefetchDistance = 740;
     74     MinPrefetchStride = 1024;
     75     MaxPrefetchIterationsAhead = 11;
     76     break;
     77   case Vulcan:
     78     MaxInterleaveFactor = 4;
     79     break;
     80   case CortexA35: break;
     81   case CortexA53: break;
     82   case CortexA72: break;
     83   case CortexA73: break;
     84   case Others: break;
     85   }
     86 }
     87 
     88 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
     89                                    const std::string &FS,
     90                                    const TargetMachine &TM, bool LittleEndian)
     91     : AArch64GenSubtargetInfo(TT, CPU, FS), ReserveX18(TT.isOSDarwin()),
     92       IsLittle(LittleEndian), CPUString(CPU), TargetTriple(TT), FrameLowering(),
     93       InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(),
     94       TLInfo(TM, *this), GISel() {}
     95 
     96 const CallLowering *AArch64Subtarget::getCallLowering() const {
     97   assert(GISel && "Access to GlobalISel APIs not set");
     98   return GISel->getCallLowering();
     99 }
    100 
    101 const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {
    102   assert(GISel && "Access to GlobalISel APIs not set");
    103   return GISel->getRegBankInfo();
    104 }
    105 
    106 /// Find the target operand flags that describe how a global value should be
    107 /// referenced for the current subtarget.
    108 unsigned char
    109 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
    110                                           const TargetMachine &TM) const {
    111   // MachO large model always goes via a GOT, simply to get a single 8-byte
    112   // absolute relocation on all global addresses.
    113   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
    114     return AArch64II::MO_GOT;
    115 
    116   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
    117     return AArch64II::MO_GOT;
    118 
    119   // The small code mode's direct accesses use ADRP, which cannot necessarily
    120   // produce the value 0 (if the code is above 4GB).
    121   if (TM.getCodeModel() == CodeModel::Small && GV->hasExternalWeakLinkage())
    122     return AArch64II::MO_GOT;
    123 
    124   return AArch64II::MO_NO_FLAG;
    125 }
    126 
    127 /// This function returns the name of a function which has an interface
    128 /// like the non-standard bzero function, if such a function exists on
    129 /// the current subtarget and it is considered prefereable over
    130 /// memset with zero passed as the second argument. Otherwise it
    131 /// returns null.
    132 const char *AArch64Subtarget::getBZeroEntry() const {
    133   // Prefer bzero on Darwin only.
    134   if(isTargetDarwin())
    135     return "bzero";
    136 
    137   return nullptr;
    138 }
    139 
    140 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
    141                                            unsigned NumRegionInstrs) const {
    142   // LNT run (at least on Cyclone) showed reasonably significant gains for
    143   // bi-directional scheduling. 253.perlbmk.
    144   Policy.OnlyTopDown = false;
    145   Policy.OnlyBottomUp = false;
    146   // Enabling or Disabling the latency heuristic is a close call: It seems to
    147   // help nearly no benchmark on out-of-order architectures, on the other hand
    148   // it regresses register pressure on a few benchmarking.
    149   Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
    150 }
    151 
    152 bool AArch64Subtarget::enableEarlyIfConversion() const {
    153   return EnableEarlyIfConvert;
    154 }
    155 
    156 bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
    157   if (!UseAddressTopByteIgnored)
    158     return false;
    159 
    160   if (TargetTriple.isiOS()) {
    161     unsigned Major, Minor, Micro;
    162     TargetTriple.getiOSVersion(Major, Minor, Micro);
    163     return Major >= 8;
    164   }
    165 
    166   return false;
    167 }
    168 
    169 std::unique_ptr<PBQPRAConstraint>
    170 AArch64Subtarget::getCustomPBQPConstraints() const {
    171   return balanceFPOps() ? llvm::make_unique<A57ChainingConstraint>() : nullptr;
    172 }
    173