1 /* 2 * Copyright (c) 2011 Intel Corporation. All Rights Reserved. 3 * Copyright (c) Imagination Technologies Limited, UK 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 /* 27 * Authors: 28 * Mingruo Sun <mingruo.sun (at) intel.com> 29 * Li Zeng <li.zeng (at) intel.com> 30 * 31 */ 32 #include "tng_VP8.h" 33 #include "tng_vld_dec.h" 34 #include "psb_def.h" 35 #include "psb_drv_debug.h" 36 37 #include "hwdefs/reg_io2.h" 38 #include "hwdefs/msvdx_offsets.h" 39 #include "hwdefs/msvdx_cmds_io2.h" 40 #include "hwdefs/msvdx_core_regs_io2.h" 41 #include "hwdefs/msvdx_vec_reg_io2.h" 42 #include "hwdefs/msvdx_vec_vp8_line_store_mem_io2.h" 43 #include "hwdefs/msvdx_vec_vp8_reg_io2.h" 44 #include "hwdefs/dxva_fw_ctrl.h" 45 46 #include <stdlib.h> 47 #include <stdint.h> 48 #include <string.h> 49 50 #include "pnw_rotate.h" 51 52 #define VEC_MODE_VP8 11 53 54 #define HW_SUPPORTED_MAX_PICTURE_WIDTH_VP8 1920 55 #define HW_SUPPORTED_MAX_PICTURE_HEIGHT_VP8 1088 56 57 #define RENDEC_REGISTER_OFFSET(__group__, __reg__ ) ( (__group__##_##__reg__##_OFFSET) + ( REG_##__group__##_OFFSET ) ) 58 59 const Probability b_mode_prob[10][10][9] = 60 { 61 { 62 { 231, 120, 48, 89, 115, 113, 120, 152, 112}, 63 { 152, 179, 64, 126, 170, 118, 46, 70, 95}, 64 { 175, 69, 143, 80, 85, 82, 72, 155, 103}, 65 { 56, 58, 10, 171, 218, 189, 17, 13, 152}, 66 { 144, 71, 10, 38, 171, 213, 144, 34, 26}, 67 { 114, 26, 17, 163, 44, 195, 21, 10, 173}, 68 { 121, 24, 80, 195, 26, 62, 44, 64, 85}, 69 { 170, 46, 55, 19, 136, 160, 33, 206, 71}, 70 { 63, 20, 8, 114, 114, 208, 12, 9, 226}, 71 { 81, 40, 11, 96, 182, 84, 29, 16, 36} 72 }, 73 { 74 { 134, 183, 89, 137, 98, 101, 106, 165, 148}, 75 { 72, 187, 100, 130, 157, 111, 32, 75, 80}, 76 { 66, 102, 167, 99, 74, 62, 40, 234, 128}, 77 { 41, 53, 9, 178, 241, 141, 26, 8, 107}, 78 { 104, 79, 12, 27, 217, 255, 87, 17, 7}, 79 { 74, 43, 26, 146, 73, 166, 49, 23, 157}, 80 { 65, 38, 105, 160, 51, 52, 31, 115, 128}, 81 { 87, 68, 71, 44, 114, 51, 15, 186, 23}, 82 { 47, 41, 14, 110, 182, 183, 21, 17, 194}, 83 { 66, 45, 25, 102, 197, 189, 23, 18, 22} 84 }, 85 { 86 { 88, 88, 147, 150, 42, 46, 45, 196, 205}, 87 { 43, 97, 183, 117, 85, 38, 35, 179, 61}, 88 { 39, 53, 200, 87, 26, 21, 43, 232, 171}, 89 { 56, 34, 51, 104, 114, 102, 29, 93, 77}, 90 { 107, 54, 32, 26, 51, 1, 81, 43, 31}, 91 { 39, 28, 85, 171, 58, 165, 90, 98, 64}, 92 { 34, 22, 116, 206, 23, 34, 43, 166, 73}, 93 { 68, 25, 106, 22, 64, 171, 36, 225, 114}, 94 { 34, 19, 21, 102, 132, 188, 16, 76, 124}, 95 { 62, 18, 78, 95, 85, 57, 50, 48, 51} 96 }, 97 { 98 { 193, 101, 35, 159, 215, 111, 89, 46, 111}, 99 { 60, 148, 31, 172, 219, 228, 21, 18, 111}, 100 { 112, 113, 77, 85, 179, 255, 38, 120, 114}, 101 { 40, 42, 1, 196, 245, 209, 10, 25, 109}, 102 { 100, 80, 8, 43, 154, 1, 51, 26, 71}, 103 { 88, 43, 29, 140, 166, 213, 37, 43, 154}, 104 { 61, 63, 30, 155, 67, 45, 68, 1, 209}, 105 { 142, 78, 78, 16, 255, 128, 34, 197, 171}, 106 { 41, 40, 5, 102, 211, 183, 4, 1, 221}, 107 { 51, 50, 17, 168, 209, 192, 23, 25, 82} 108 }, 109 { 110 { 125, 98, 42, 88, 104, 85, 117, 175, 82}, 111 { 95, 84, 53, 89, 128, 100, 113, 101, 45}, 112 { 75, 79, 123, 47, 51, 128, 81, 171, 1}, 113 { 57, 17, 5, 71, 102, 57, 53, 41, 49}, 114 { 115, 21, 2, 10, 102, 255, 166, 23, 6}, 115 { 38, 33, 13, 121, 57, 73, 26, 1, 85}, 116 { 41, 10, 67, 138, 77, 110, 90, 47, 114}, 117 { 101, 29, 16, 10, 85, 128, 101, 196, 26}, 118 { 57, 18, 10, 102, 102, 213, 34, 20, 43}, 119 { 117, 20, 15, 36, 163, 128, 68, 1, 26} 120 }, 121 { 122 { 138, 31, 36, 171, 27, 166, 38, 44, 229}, 123 { 67, 87, 58, 169, 82, 115, 26, 59, 179}, 124 { 63, 59, 90, 180, 59, 166, 93, 73, 154}, 125 { 40, 40, 21, 116, 143, 209, 34, 39, 175}, 126 { 57, 46, 22, 24, 128, 1, 54, 17, 37}, 127 { 47, 15, 16, 183, 34, 223, 49, 45, 183}, 128 { 46, 17, 33, 183, 6, 98, 15, 32, 183}, 129 { 65, 32, 73, 115, 28, 128, 23, 128, 205}, 130 { 40, 3, 9, 115, 51, 192, 18, 6, 223}, 131 { 87, 37, 9, 115, 59, 77, 64, 21, 47} 132 }, 133 { 134 { 104, 55, 44, 218, 9, 54, 53, 130, 226}, 135 { 64, 90, 70, 205, 40, 41, 23, 26, 57}, 136 { 54, 57, 112, 184, 5, 41, 38, 166, 213}, 137 { 30, 34, 26, 133, 152, 116, 10, 32, 134}, 138 { 75, 32, 12, 51, 192, 255, 160, 43, 51}, 139 { 39, 19, 53, 221, 26, 114, 32, 73, 255}, 140 { 31, 9, 65, 234, 2, 15, 1, 118, 73}, 141 { 88, 31, 35, 67, 102, 85, 55, 186, 85}, 142 { 56, 21, 23, 111, 59, 205, 45, 37, 192}, 143 { 55, 38, 70, 124, 73, 102, 1, 34, 98} 144 }, 145 { 146 { 102, 61, 71, 37, 34, 53, 31, 243, 192}, 147 { 69, 60, 71, 38, 73, 119, 28, 222, 37}, 148 { 68, 45, 128, 34, 1, 47, 11, 245, 171}, 149 { 62, 17, 19, 70, 146, 85, 55, 62, 70}, 150 { 75, 15, 9, 9, 64, 255, 184, 119, 16}, 151 { 37, 43, 37, 154, 100, 163, 85, 160, 1}, 152 { 63, 9, 92, 136, 28, 64, 32, 201, 85}, 153 { 86, 6, 28, 5, 64, 255, 25, 248, 1}, 154 { 56, 8, 17, 132, 137, 255, 55, 116, 128}, 155 { 58, 15, 20, 82, 135, 57, 26, 121, 40} 156 }, 157 { 158 { 164, 50, 31, 137, 154, 133, 25, 35, 218}, 159 { 51, 103, 44, 131, 131, 123, 31, 6, 158}, 160 { 86, 40, 64, 135, 148, 224, 45, 183, 128}, 161 { 22, 26, 17, 131, 240, 154, 14, 1, 209}, 162 { 83, 12, 13, 54, 192, 255, 68, 47, 28}, 163 { 45, 16, 21, 91, 64, 222, 7, 1, 197}, 164 { 56, 21, 39, 155, 60, 138, 23, 102, 213}, 165 { 85, 26, 85, 85, 128, 128, 32, 146, 171}, 166 { 18, 11, 7, 63, 144, 171, 4, 4, 246}, 167 { 35, 27, 10, 146, 174, 171, 12, 26, 128} 168 }, 169 { 170 { 190, 80, 35, 99, 180, 80, 126, 54, 45}, 171 { 85, 126, 47, 87, 176, 51, 41, 20, 32}, 172 { 101, 75, 128, 139, 118, 146, 116, 128, 85}, 173 { 56, 41, 15, 176, 236, 85, 37, 9, 62}, 174 { 146, 36, 19, 30, 171, 255, 97, 27, 20}, 175 { 71, 30, 17, 119, 118, 255, 17, 18, 138}, 176 { 101, 38, 60, 138, 55, 70, 43, 26, 142}, 177 { 138, 45, 61, 62, 219, 1, 81, 188, 64}, 178 { 32, 41, 20, 117, 151, 142, 20, 21, 163}, 179 { 112, 19, 12, 61, 195, 128, 48, 4, 24} 180 } 181 }; 182 183 static const uint32_t RegEntdecFeControl = ( (VEC_MODE_VP8 & 0x7) << MSVDX_VEC_CR_VEC_ENTDEC_FE_CONTROL_ENTDEC_FE_MODE_SHIFT ) 184 | ( (VEC_MODE_VP8 >> 3) << MSVDX_VEC_CR_VEC_ENTDEC_FE_CONTROL_ENTDEC_FE_EXTENDED_MODE_SHIFT ); 185 186 #define GET_SURFACE_INFO_picture_coding_type(psb_surface) ((int) (psb_surface->extra_info[2])) 187 #define SET_SURFACE_INFO_picture_coding_type(psb_surface, val) psb_surface->extra_info[2] = (uint32_t) val; 188 #define SET_SURFACE_INFO_rotate(psb_surface, rotate) psb_surface->extra_info[5] = (uint32_t) rotate; 189 #define GET_SURFACE_INFO_rotate(psb_surface) ((int) psb_surface->extra_info[5]) 190 191 /* Truncates a signed integer to 17 bits */ 192 #define SIGNTRUNC( x ) ((( (x) >> 15) & 0x10000) | ( (x) & 0xffff)) 193 194 #define MSVDX_VEC_REGS_BASE_MTX 0x0800 195 #define MSVDX_COMMANDS_BASE_MTX 0x1000 196 #define MSVDX_IQRAM_BASE_MTX 0x700 197 198 #define SLICEDATA_BUFFER_TYPE(type) ((type==VASliceDataBufferType)?"VASliceDataBufferType":"VAProtectedSliceDataBufferType") 199 200 #define VP8_BYTES_PER_MB (128) 201 #define VLR_OFFSET_VP8_PARSER (0x0920) 202 #define INTRA_BUFFER_SIZE (32768) 203 #define DECODECONTROL_BUFFER_SIZE (1024*12) 204 #define DECODECONTROL_BUFFER_LLDMA_OFFSET (1024*8) 205 // AuxLineBuffer is 256k 206 #define AUX_LINE_BUFFER_SIZE (1024*256) 207 208 #define VP8_BUFFOFFSET_MASK (0x00ffffff) 209 #define VP8_PARTITIONSCOUNT_MASK (0x0f000000) 210 #define VP8_PARTITIONSCOUNT_SHIFT (24) 211 212 #define VP8_FRAMETYPE_MASK (0x08000000) 213 #define VP8_FRAMETYPE_SHIFT (27) 214 215 #define MAX_MB_SEGMENTS 4 216 #define SEGMENT_DELTADATA 0 217 #define SEGMENT_ABSDATA 1 218 #define MAX_LOOP_FILTER 63 219 #define MAX_QINDEX 127 220 221 #define CABAC_LSR_ProbsBaseOffset 0x000 222 223 const uint32_t CABAC_LSR_KeyFrame_BModeProb_Address = CABAC_LSR_ProbsBaseOffset; 224 const uint32_t CABAC_LSR_KeyFrame_BModeProb_Stride = 12; 225 const uint32_t CABAC_LSR_KeyFrame_BModeProb_Valid = 9; 226 const uint32_t CABAC_LSR_KeyFrame_BModeProb_ToIdxMap[] = {0, 1, 2, 3, 4, 6, 5, 0/*ignored value here*/, 7, 8, 0/*ignored value here*/, 0/*ignored value here*/}; 227 228 const uint32_t CABAC_LSR_InterFrame_YModeProb_Address = CABAC_LSR_ProbsBaseOffset; 229 const uint32_t CABAC_LSR_InterFrame_YModeProb_Stride = 4; 230 const uint32_t CABAC_LSR_InterFrame_YModeProb_Valid = 4; 231 const uint32_t CABAC_LSR_InterFrame_YModeProb_ToIdxMap[] = {0, 1, 2, 3}; 232 233 const uint32_t CABAC_LSR_InterFrame_UVModeProb_Address = CABAC_LSR_ProbsBaseOffset + 0x04; 234 const uint32_t CABAC_LSR_InterFrame_UVModeProb_Stride = 4; 235 const uint32_t CABAC_LSR_InterFrame_UVModeProb_Valid = 3; 236 const uint32_t CABAC_LSR_InterFrame_UVModeProb_ToIdxMap[] = {0, 1, 2, 0/*ignored value here*/}; 237 238 const uint32_t CABAC_LSR_InterFrame_MVContextProb_Address = CABAC_LSR_ProbsBaseOffset + 0x08; 239 const uint32_t CABAC_LSR_InterFrame_MVContextProb_Stride = 20; 240 const uint32_t CABAC_LSR_InterFrame_MVContextProb_Valid = 19; 241 const uint32_t CABAC_LSR_InterFrame_MVContextProb_ToIdxMap[] = {0, 2, 3, 6, 4, 5, 7, 8, 9, 10, 11, 18, 17, 16, 15, 14, 13, 12, 1, 0/*ignored value here*/}; 242 /* this unusual table as it moves coefficient for sgn from idx1 to idx 18 as well as arranges the rest */ 243 244 const uint32_t CABAC_LSR_CoefficientProb_Address = CABAC_LSR_ProbsBaseOffset; 245 const uint32_t CABAC_LSR_CoefficientProb_Stride = 12; 246 const uint32_t CABAC_LSR_CoefficientProb_Valid = 11; 247 const uint32_t CABAC_LSR_CoefficientProb_ToIdxMap[] = {0, 1, 2, 3, 4, 6, 0/*ignored value here*/, 5, 7, 8, 9, 10}; 248 249 250 typedef enum 251 { 252 Level_AltQuant = 0, 253 Level_AltLoopFilter, 254 Level_Max 255 } LevelFeatures; 256 257 struct context_VP8_s { 258 struct context_DEC_s dec_ctx; 259 object_context_p obj_context; /* back reference */ 260 261 uint32_t display_picture_size; 262 uint32_t coded_picture_size; 263 264 /* Picture parameters */ 265 VAPictureParameterBufferVP8 *pic_params; 266 267 /* Probability tables */ 268 VAProbabilityDataBufferVP8 *probs_params; 269 270 /* VP8 Inverse Quantization Matrix Buffer */ 271 VAIQMatrixBufferVP8 *iq_params; 272 273 VASliceParameterBufferVP8 *slice_params; 274 275 object_surface_p golden_ref_picture; 276 object_surface_p alt_ref_picture; 277 object_surface_p last_ref_picture; 278 /* VP8_FRAME_TYPE picture_coding_mode; */ 279 280 int8_t baseline_filter[MAX_MB_SEGMENTS]; 281 282 uint32_t size_mb; /* in macroblocks */ 283 uint32_t slice_count; 284 285 /* uint32_t FE_MB_segment_probs; */ 286 /* uint32_t FE_MB_flags_probs; */ 287 uint32_t DCT_Base_Address_Offset; 288 289 uint32_t operating_mode; 290 291 uint16_t cache_ref_offset; 292 uint16_t cache_row_offset; 293 294 uint32_t buffer_size; 295 uint32_t segid_size; 296 297 int8_t q_index[MAX_MB_SEGMENTS]; 298 299 /* Registers */ 300 /* 301 uint32_t reg_FE_PIC0; 302 uint32_t reg_FE_PIC1; 303 uint32_t reg_FE_PIC2; 304 uint32_t reg_BE_PIC0; 305 uint32_t reg_BE_PIC1; 306 uint32_t reg_BE_PIC2; 307 uint32_t reg_BE_BaseAdr1stPartPic; 308 */ 309 310 uint32_t cmd_slice_params; 311 312 /* VP8 features */ 313 /* MB Flags Buffer */ 314 struct psb_buffer_s MB_flags_buffer; 315 316 /* Cur Pic Buffer */ 317 struct psb_buffer_s cur_pic_buffer; 318 319 /* 1 St Part Buffer */ 320 struct psb_buffer_s buffer_1st_part; 321 322 struct psb_buffer_s segID_buffer; 323 324 /* Probability tables */ 325 uint32_t probability_data_buffer_size; 326 struct psb_buffer_s probability_data_buffer; 327 328 uint32_t probability_data_1st_part_size; 329 struct psb_buffer_s probability_data_1st_part; 330 331 uint32_t probability_data_2nd_part_size; 332 struct psb_buffer_s probability_data_2nd_part; 333 334 struct psb_buffer_s intra_buffer; 335 }; 336 337 typedef struct context_VP8_s *context_VP8_p; 338 339 #define INIT_CONTEXT_VP8 context_VP8_p ctx = (context_VP8_p) obj_context->format_data; 340 341 #define SURFACE(id) ((object_surface_p) object_heap_lookup( &ctx->obj_context->driver_data->surface_heap, id )) 342 343 static psb_surface_stride_t get_opp_mode_stride(context_VP8_p ctx, const unsigned int uiStride) { 344 psb_surface_p target_surface = ctx->obj_context->current_render_target->psb_surface; 345 psb_surface_stride_t eOppModeStride = target_surface->stride_mode; 346 switch (uiStride) { 347 case 4096: 348 eOppModeStride = STRIDE_4096; 349 break; 350 case 2048: 351 eOppModeStride = STRIDE_2048; 352 break; 353 case 1280: 354 eOppModeStride = STRIDE_1280; 355 break; 356 case 1920: 357 eOppModeStride = STRIDE_1920; 358 break; 359 case 1024: 360 eOppModeStride = STRIDE_1024; 361 break; 362 case 512: 363 eOppModeStride = STRIDE_512; 364 break; 365 case 352: 366 eOppModeStride = STRIDE_352; 367 break; 368 default: 369 eOppModeStride = STRIDE_UNDEFINED;/* Assume Extended stride is used */ 370 break; 371 } 372 373 return eOppModeStride; 374 } 375 376 static int get_inloop_opmod(context_VP8_p ctx) { 377 ctx->obj_context->operating_mode = 0; 378 psb_surface_p target_surface = ctx->obj_context->current_render_target->psb_surface; 379 psb_surface_stride_t eOppModeStride = get_opp_mode_stride(ctx,target_surface->stride); 380 381 if (eOppModeStride == STRIDE_UNDEFINED) { 382 REGIO_WRITE_FIELD_LITE(ctx->obj_context->operating_mode, MSVDX_CMDS, OPERATING_MODE, USE_EXT_ROW_STRIDE, 1); 383 } else { 384 REGIO_WRITE_FIELD_LITE(ctx->obj_context->operating_mode, MSVDX_CMDS, OPERATING_MODE, ROW_STRIDE, eOppModeStride); 385 } 386 387 REGIO_WRITE_FIELD_LITE(ctx->obj_context->operating_mode, MSVDX_CMDS, OPERATING_MODE, CHROMA_INTERLEAVED, 0); 388 389 return ctx->obj_context->operating_mode; 390 } 391 392 static void tng_VP8_QueryConfigAttributes( 393 VAProfile profile, 394 VAEntrypoint entrypoint, 395 VAConfigAttrib *attrib_list, 396 int num_attribs) { 397 398 int i; 399 drv_debug_msg(VIDEO_DEBUG_GENERAL, "tng_VP8_QueryConfigAttributes\n"); 400 401 for (i = 0; i < num_attribs; i++) { 402 switch (attrib_list[i].type) { 403 case VAConfigAttribMaxPictureWidth: 404 if ((entrypoint == VAEntrypointVLD) && 405 (profile == VAProfileVP8Version0_3)) 406 attrib_list[i].value = HW_SUPPORTED_MAX_PICTURE_WIDTH_VP8; 407 else 408 attrib_list[i].value = VA_ATTRIB_NOT_SUPPORTED; 409 break; 410 case VAConfigAttribMaxPictureHeight: 411 if ((entrypoint == VAEntrypointVLD) && 412 (profile == VAProfileVP8Version0_3)) 413 attrib_list[i].value = HW_SUPPORTED_MAX_PICTURE_HEIGHT_VP8; 414 else 415 attrib_list[i].value = VA_ATTRIB_NOT_SUPPORTED; 416 break; 417 default: 418 break; 419 } 420 } 421 422 } 423 424 static VAStatus tng_VP8_ValidateConfig( 425 object_config_p obj_config) { 426 int i; 427 /* Check all attributes */ 428 for (i = 0; i < obj_config->attrib_count; i++) { 429 switch (obj_config->attrib_list[i].type) { 430 case VAConfigAttribRTFormat: 431 /* Ignore */ 432 break; 433 434 default: 435 return VA_STATUS_ERROR_ATTR_NOT_SUPPORTED; 436 } 437 } 438 439 return VA_STATUS_SUCCESS; 440 } 441 442 443 static void tng_VP8_DestroyContext(object_context_p obj_context); 444 445 static void tng__VP8_process_slice_data(context_DEC_p dec_ctx, VASliceParameterBufferBase *vld_slice_param); 446 static void tng__VP8_end_slice(context_DEC_p dec_ctx); 447 static void tng__VP8_begin_slice(context_DEC_p dec_ctx, VASliceParameterBufferBase *vld_slice_param); 448 static VAStatus tng_VP8_process_buffer(context_DEC_p dec_ctx, object_buffer_p buffer); 449 450 static VAStatus tng_VP8_CreateContext( 451 object_context_p obj_context, 452 object_config_p __maybe_unused obj_config) { 453 VAStatus vaStatus = VA_STATUS_SUCCESS; 454 context_VP8_p ctx; 455 456 ctx = (context_VP8_p) calloc(1,sizeof(struct context_VP8_s)); 457 458 if (NULL == ctx) { 459 vaStatus = VA_STATUS_ERROR_ALLOCATION_FAILED; 460 DEBUG_FAILURE; 461 return vaStatus; 462 } 463 464 obj_context->format_data = (void *) ctx; 465 ctx->obj_context = obj_context; 466 ctx->pic_params = NULL; 467 468 ctx->dec_ctx.begin_slice = tng__VP8_begin_slice; 469 ctx->dec_ctx.process_slice = tng__VP8_process_slice_data; 470 ctx->dec_ctx.end_slice = tng__VP8_end_slice; 471 ctx->dec_ctx.process_buffer = tng_VP8_process_buffer; 472 473 /* ctx->cache_ref_offset = 72; */ 474 /* ctx->cache_row_offset = 4; */ 475 ctx->cache_ref_offset = 144; 476 ctx->cache_row_offset = 8; 477 478 //uint32_t TotalMBs = ((obj_context->picture_width + 19) * obj_context->picture_height) / (16*16); 479 uint32_t total_mbs = (((obj_context->picture_height + 15) >> 4) + 4) * ((obj_context->picture_width + 15) >> 4); 480 ctx->buffer_size = total_mbs * 64; // 64 bytes per MB 481 ctx->segid_size = total_mbs / 4; // 2 bits per MB 482 //ctx->segid_size = (ctx->buffer_size + 0xfff) & ~0xfff; 483 ctx->segid_size = (ctx->segid_size + 0xfff) & ~0xfff; 484 485 /* Create mem resource for current picture macroblock data to be stored */ 486 if (vaStatus == VA_STATUS_SUCCESS) { 487 vaStatus = psb_buffer_create(obj_context->driver_data, 488 ctx->buffer_size, 489 psb_bt_cpu_vpu, 490 &ctx->cur_pic_buffer); 491 DEBUG_FAILURE; 492 } 493 494 /* Create mem resource for storing 1st partition .*/ 495 if (vaStatus == VA_STATUS_SUCCESS) { 496 vaStatus = psb_buffer_create(obj_context->driver_data, 497 ctx->buffer_size, 498 psb_bt_cpu_vpu, 499 &ctx->buffer_1st_part); 500 DEBUG_FAILURE; 501 } 502 503 if (vaStatus == VA_STATUS_SUCCESS) { 504 vaStatus = psb_buffer_create(obj_context->driver_data, 505 ctx->segid_size, 506 psb_bt_cpu_vpu, 507 &ctx->segID_buffer); 508 DEBUG_FAILURE; 509 } 510 511 /* Create mem resource for PIC MB Flags .*/ 512 /* one MB would take 2 bits to store Y2 flag and mb_skip_coeff flag, so size would be same as ui32segidsize */ 513 if (vaStatus == VA_STATUS_SUCCESS) { 514 vaStatus = psb_buffer_create(obj_context->driver_data, 515 ctx->segid_size, 516 psb_bt_cpu_vpu, 517 &ctx->MB_flags_buffer); 518 DEBUG_FAILURE; 519 } 520 521 /* calculate the size of prbability buffer size for both the partitions */ 522 ctx->probability_data_1st_part_size = 1200; 523 ctx->probability_data_2nd_part_size = 1200; 524 525 /* allocate device memory for prbability table for the both the partitions.*/ 526 if (vaStatus == VA_STATUS_SUCCESS) { 527 vaStatus = psb_buffer_create(obj_context->driver_data, 528 ctx->probability_data_1st_part_size, 529 psb_bt_cpu_vpu, 530 &ctx->probability_data_1st_part); 531 DEBUG_FAILURE; 532 } 533 534 /* allocate device memory for prbability table for the both the partitions.*/ 535 if (vaStatus == VA_STATUS_SUCCESS) { 536 vaStatus = psb_buffer_create(obj_context->driver_data, 537 ctx->probability_data_2nd_part_size, 538 psb_bt_cpu_vpu, 539 &ctx->probability_data_2nd_part); 540 DEBUG_FAILURE; 541 } 542 ctx->dec_ctx.preload_buffer = &ctx->probability_data_2nd_part; 543 544 if (vaStatus == VA_STATUS_SUCCESS) { 545 vaStatus = psb_buffer_create(obj_context->driver_data, 546 INTRA_BUFFER_SIZE, 547 psb_bt_cpu_vpu, 548 &ctx->intra_buffer); 549 DEBUG_FAILURE; 550 } 551 552 if (vaStatus == VA_STATUS_SUCCESS) { 553 vaStatus = vld_dec_CreateContext(&ctx->dec_ctx, obj_context); 554 DEBUG_FAILURE; 555 } 556 557 if (vaStatus != VA_STATUS_SUCCESS) { 558 tng_VP8_DestroyContext(obj_context); 559 } 560 561 return vaStatus; 562 } 563 564 static void tng_VP8_DestroyContext( 565 object_context_p obj_context) { 566 INIT_CONTEXT_VP8 567 uint32_t i; 568 569 vld_dec_DestroyContext(&ctx->dec_ctx); 570 571 psb_buffer_destroy(&ctx->cur_pic_buffer); 572 psb_buffer_destroy(&ctx->buffer_1st_part); 573 psb_buffer_destroy(&ctx->segID_buffer); 574 psb_buffer_destroy(&ctx->MB_flags_buffer); 575 psb_buffer_destroy(&ctx->probability_data_1st_part); 576 psb_buffer_destroy(&ctx->probability_data_2nd_part); 577 psb_buffer_destroy(&ctx->intra_buffer); 578 579 if (ctx->pic_params) { 580 free(ctx->pic_params); 581 ctx->pic_params = NULL; 582 } 583 584 if (ctx->probs_params) { 585 free(ctx->probs_params); 586 ctx->probs_params = NULL; 587 } 588 589 free(obj_context->format_data); 590 obj_context->format_data = NULL; 591 } 592 593 #ifdef DEBUG_TRACE 594 #define P(x) psb__trace_message("PARAMS: " #x "\t= %08x (%d)\n", p->x, p->x) 595 static void tng__VP8_trace_pic_params(VAPictureParameterBufferVP8 *p) { 596 P(prob_skip_false); 597 P(prob_intra); 598 P(prob_last); 599 P(prob_gf); 600 } 601 static void tng__VP8_trace_slc_params(VASliceParameterBufferVP8 *p) { 602 P(num_of_partitions); 603 P(macroblock_offset); 604 } 605 #endif 606 607 static VAStatus tng__VP8_process_picture_param(context_VP8_p ctx, object_buffer_p obj_buffer) { 608 object_surface_p obj_surface = ctx->obj_context->current_render_target; 609 psb_surface_p target_surface = obj_surface->psb_surface; 610 uint32_t reg_value; 611 VAStatus vaStatus; 612 613 ASSERT(obj_buffer->type == VAPictureParameterBufferType); 614 ASSERT(obj_buffer->num_elements == 1); 615 ASSERT(obj_buffer->size == sizeof(VAPictureParameterBufferVP8)); 616 ASSERT(target_surface); 617 618 if ((obj_buffer->num_elements != 1) || 619 (obj_buffer->size != sizeof(VAPictureParameterBufferVP8)) || 620 (NULL == target_surface)) { 621 return VA_STATUS_ERROR_UNKNOWN; 622 } 623 624 /* Transfer ownership of VAPictureParameterBufferVP8 data */ 625 VAPictureParameterBufferVP8 *pic_params = (VAPictureParameterBufferVP8 *) obj_buffer->buffer_data; 626 if (ctx->pic_params) { 627 free(ctx->pic_params); 628 } 629 630 ctx->pic_params = pic_params; 631 obj_buffer->buffer_data = NULL; 632 obj_buffer->size = 0; 633 634 #ifdef DEBUG_TRACE 635 tng__VP8_trace_pic_params(pic_params); 636 #endif 637 638 if (obj_surface->share_info) { 639 obj_surface->share_info->coded_width = ctx->pic_params->frame_width; 640 obj_surface->share_info->coded_height = ctx->pic_params->frame_height; 641 } 642 643 ctx->size_mb = ((ctx->pic_params->frame_width) * (ctx->pic_params->frame_height)) >> 8; 644 /* port DDK D3DDDIFMT_PICTUREPARAMSDATA -> */ 645 /* 646 SetCodedWidth ( ((PicParam.FrameWidth + 15) / 16) * 16 ); 647 SetCodedHeight( ((PicParam.FrameHeight + 15) / 16) * 16 ); 648 SetDisplayWidth( PicParam.FrameWidth); 649 SetDisplayHeight( PicParam.FrameHeight); 650 */ 651 /* 652 { 653 object_surface_p obj_surface = SURFACE(pic_params->current_picture); 654 if(obj_surface != ctx->obj_context->current_render_target) 655 return VA_STATUS_ERROR_INVALID_SURFACE; 656 } 657 */ 658 659 /*ASYN_MODE would depend upon certain condition, VDEB module would be activated on the condition basis*/ 660 // uint32_t bdeblock = IMG_FALSE; 661 /* // move to vp8vld to calculate loop_filter_disable 662 if((pic_params->pic_fields.bits.version == 0) || (pic_params->pic_fields.bits.version == 1)) 663 { 664 // bdeblock = (pic_params->loop_filter_level > 0 )? IMG_TRUE : IMG_FALSE ; 665 pic_params->pic_fields.bits.loop_filter_disable = (pic_params->loop_filter_level[0] > 0 )? IMG_TRUE : IMG_FALSE ; 666 } 667 */ 668 669 ctx->obj_context->operating_mode = get_inloop_opmod(ctx); /* port from ui32OperatingMode = mpDestFrame->GetInloopOpMode() */ 670 REGIO_WRITE_FIELD_LITE(ctx->obj_context->operating_mode, MSVDX_CMDS, OPERATING_MODE, CHROMA_FORMAT, 1); 671 REGIO_WRITE_FIELD_LITE(ctx->obj_context->operating_mode, MSVDX_CMDS, OPERATING_MODE, ASYNC_MODE, (pic_params->pic_fields.bits.loop_filter_disable == 0)? 0:1);/* 0 = VDMC and VDEB active. 1 = VDEB pass-thru. */ 672 REGIO_WRITE_FIELD_LITE(ctx->obj_context->operating_mode, MSVDX_CMDS, OPERATING_MODE, CODEC_MODE, VEC_MODE_VP8); 673 REGIO_WRITE_FIELD_LITE(ctx->obj_context->operating_mode, MSVDX_CMDS, OPERATING_MODE, CODEC_PROFILE, pic_params->pic_fields.bits.version); 674 675 if (pic_params->last_ref_frame != VA_INVALID_SURFACE) { 676 ctx->last_ref_picture = SURFACE(pic_params->last_ref_frame); 677 } else { 678 /* for mmu fault protection */ 679 ctx->last_ref_picture = ctx->obj_context->current_render_target; 680 } 681 682 if (pic_params->golden_ref_frame != VA_INVALID_SURFACE) { 683 ctx->golden_ref_picture = SURFACE(pic_params->golden_ref_frame); 684 } else { 685 /* for mmu fault protection */ 686 ctx->golden_ref_picture = ctx->obj_context->current_render_target; 687 } 688 689 if (pic_params->alt_ref_frame != VA_INVALID_SURFACE) { 690 ctx->alt_ref_picture = SURFACE(pic_params->alt_ref_frame); 691 } else { 692 /* for mmu fault protection */ 693 ctx->alt_ref_picture = ctx->obj_context->current_render_target; 694 } 695 696 /* TODO Add VP8 support in this function */ 697 psb_CheckInterlaceRotate(ctx->obj_context, (unsigned char *)pic_params); 698 699 return VA_STATUS_SUCCESS; 700 } 701 702 static VAStatus tng__VP8_process_probility_param(context_VP8_p ctx, object_buffer_p obj_buffer) { 703 ASSERT(obj_buffer->type == VAProbabilityBufferType); 704 ASSERT(obj_buffer->num_elements == 1); 705 ASSERT(obj_buffer->size == sizeof(VANodeProbabilityBufferVP8)); 706 707 if ((obj_buffer->num_elements != 1) || 708 (obj_buffer->size != sizeof(VAProbabilityDataBufferVP8))) { 709 return VA_STATUS_ERROR_UNKNOWN; 710 } 711 712 if (ctx->probs_params) { 713 free(ctx->probs_params); 714 } 715 716 /* Transfer ownership of VANodeProbabilityBufferVP8 data */ 717 ctx->probs_params = (VAProbabilityDataBufferVP8 *) obj_buffer->buffer_data; 718 obj_buffer->buffer_data = NULL; 719 obj_buffer->size = 0; 720 721 return VA_STATUS_SUCCESS; 722 } 723 724 static VAStatus tng__VP8_process_iq_matrix(context_VP8_p ctx, object_buffer_p obj_buffer) { 725 ASSERT(obj_buffer->type == VAIQMatrixBufferType); 726 ASSERT(obj_buffer->num_elements == 1); 727 ASSERT(obj_buffer->size == sizeof(VAIQMatrixBufferVP8)); 728 if ((obj_buffer->num_elements != 1) || 729 (obj_buffer->size != sizeof(VAIQMatrixBufferVP8))) { 730 return VA_STATUS_ERROR_UNKNOWN; 731 } 732 733 /* Transfer ownership of VAIQMatrixBufferVP8 data */ 734 if (ctx->iq_params) { 735 free(ctx->iq_params); 736 } 737 738 ctx->iq_params = (VAIQMatrixBufferVP8 *) obj_buffer->buffer_data; 739 obj_buffer->buffer_data = NULL; 740 obj_buffer->size = 0; 741 742 return VA_STATUS_SUCCESS; 743 744 } 745 746 /* 747 static void tng__VP8_set_operation_target(context_VP8_p ctx) 748 { 749 psb_cmdbuf_p cmdbuf = ctx->obj_context->cmdbuf; 750 psb_surface_p target_surface = ctx->obj_context->current_render_target->psb_surface; 751 752 psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_CMDS, DISPLAY_PICTURE_SIZE)); 753 754 psb_cmdbuf_rendec_write(cmdbuf, ctx->display_picture_size); 755 psb_cmdbuf_rendec_write(cmdbuf, ctx->coded_picture_size); 756 psb_cmdbuf_rendec_write(cmdbuf, ctx->obj_context->operating_mode); 757 758 psb_cmdbuf_rendec_write_address(cmdbuf, &target_surface->buf, target_surface->buf.buffer_ofs); 759 psb_cmdbuf_rendec_write_address(cmdbuf, &target_surface->buf, target_surface->buf.buffer_ofs + target_surface->chroma_offset); 760 psb_cmdbuf_rendec_end(cmdbuf); 761 762 tng__VP8_setup_alternative_frame(ctx); 763 } 764 */ 765 766 static void tng__VP8_set_target_picture(context_VP8_p ctx) { 767 psb_cmdbuf_p cmdbuf = ctx->obj_context->cmdbuf; 768 psb_surface_p target_surface = ctx->obj_context->current_render_target->psb_surface; 769 psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_CMDS, LUMA_RECONSTRUCTED_PICTURE_BASE_ADDRESSES)); 770 771 psb_cmdbuf_rendec_write_address(cmdbuf, &target_surface->buf, target_surface->buf.buffer_ofs + target_surface->luma_offset); 772 psb_cmdbuf_rendec_write_address(cmdbuf, &target_surface->buf, target_surface->buf.buffer_ofs + target_surface->chroma_offset); 773 psb_cmdbuf_rendec_end(cmdbuf); 774 775 } 776 777 /* Set Reference pictures address */ 778 static void tng__VP8_set_reference_picture(context_VP8_p ctx) { 779 /* Reference pictures base addresses */ 780 psb_cmdbuf_p cmdbuf = ctx->obj_context->cmdbuf; 781 psb_surface_p last_ref_surface = ctx->last_ref_picture->psb_surface; 782 psb_surface_p golden_ref_surface = ctx->golden_ref_picture->psb_surface; 783 psb_surface_p alt_ref_surface = ctx->alt_ref_picture->psb_surface; 784 785 psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_CMDS, REFERENCE_PICTURE_BASE_ADDRESSES)); 786 787 /* write last refernce picture address */ 788 psb_cmdbuf_rendec_write_address(cmdbuf, &last_ref_surface->buf, last_ref_surface->buf.buffer_ofs); 789 psb_cmdbuf_rendec_write_address(cmdbuf, &last_ref_surface->buf, last_ref_surface->buf.buffer_ofs + last_ref_surface->chroma_offset); 790 791 /* write Golden refernce picture address */ 792 psb_cmdbuf_rendec_write_address(cmdbuf, &golden_ref_surface->buf, golden_ref_surface->buf.buffer_ofs); 793 psb_cmdbuf_rendec_write_address(cmdbuf, &golden_ref_surface->buf, golden_ref_surface->buf.buffer_ofs + golden_ref_surface->chroma_offset); 794 795 /* write Alternate refernce picture address */ 796 psb_cmdbuf_rendec_write_address(cmdbuf, &alt_ref_surface->buf, alt_ref_surface->buf.buffer_ofs); 797 psb_cmdbuf_rendec_write_address(cmdbuf, &alt_ref_surface->buf, alt_ref_surface->buf.buffer_ofs + alt_ref_surface->chroma_offset); 798 799 psb_cmdbuf_rendec_end(cmdbuf); 800 } 801 802 /* 803 static void tng__VP8_set_picture_header_data(context_VP8_p ctx) 804 { 805 psb_cmdbuf_p cmdbuf = ctx->obj_context->cmdbuf; 806 uint32_t reg_value; 807 808 psb_cmdbuf_reg_start_block(cmdbuf, 0); 809 810 psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC0), ctx->reg_FE_PIC0); 811 psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC1), ctx->reg_FE_PIC1); 812 psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC2), ctx->reg_FE_PIC2); 813 814 psb_cmdbuf_reg_end_block(cmdbuf); 815 816 psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_CMDS, VP8_FILTER_SELECT)); 817 psb_cmdbuf_rendec_write(cmdbuf, ctx->reg_filter_param); 818 psb_cmdbuf_rendec_end(cmdbuf); 819 820 // BE Section 821 { 822 psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_BE_PIC0)); 823 824 psb_cmdbuf_rendec_write(cmdbuf, ctx->reg_BE_PIC0 ); 825 psb_cmdbuf_rendec_write(cmdbuf, ctx->reg_BE_PIC1 ); 826 827 psb_cmdbuf_rendec_end(cmdbuf); 828 } 829 830 { 831 psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_BE_PIC2)); 832 833 psb_cmdbuf_rendec_write(cmdbuf, ctx->reg_BE_PIC2 ); 834 835 psb_cmdbuf_rendec_end(cmdbuf); 836 } 837 838 { 839 psb_cmdbuf_rendec_start(cmdbuf , RENDEC_REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_BE_BASE_ADDR_1STPART_PIC)); 840 841 psb_cmdbuf_rendec_write_address(cmdbuf, &ctx->base_addr_1st_pic_buffer, ctx->base_addr_1st_pic_buffer.buffer_ofs); 842 843 psb_cmdbuf_rendec_end(cmdbuf); 844 } 845 //rendec block 846 { 847 psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_CMDS, MC_CACHE_CONFIGURATION)); 848 849 reg_value = 0; 850 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, MC_CACHE_CONFIGURATION, CONFIG_REF_OFFSET, ctx->cache_ref_offset ); 851 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, MC_CACHE_CONFIGURATION, CONFIG_ROW_OFFSET, ctx->cache_row_offset ); 852 853 psb_cmdbuf_rendec_write(cmdbuf, reg_value); 854 855 psb_cmdbuf_rendec_end(cmdbuf); 856 } 857 } 858 */ 859 860 static void tng__VP8_compile_baseline_filter_data(context_VP8_p ctx) { 861 uint32_t i; 862 863 for (i = 0; i < MAX_MB_SEGMENTS; i++) { 864 ctx->baseline_filter[i] = ctx->pic_params->loop_filter_level[i]; 865 } 866 } 867 868 static void tng__VP8_compile_qindex_data(context_VP8_p ctx) { 869 uint32_t i; 870 for (i = 0; i < MAX_MB_SEGMENTS; i++) { 871 ctx->q_index[i] = ctx->iq_params->quantization_index[i][0]; 872 } 873 } 874 875 static void tng__CMDS_registers_write(context_VP8_p ctx) { 876 psb_cmdbuf_p cmdbuf = ctx->obj_context->cmdbuf; 877 uint32_t reg_value; 878 879 // psb_cmdbuf_reg_start_block(cmdbuf, 0); 880 881 // psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC0), ctx->reg_FE_PIC0); 882 // psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC1), ctx->reg_FE_PIC1); 883 // psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC2), ctx->reg_FE_PIC2); 884 885 // psb_cmdbuf_reg_end_block(cmdbuf); 886 887 psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_CMDS, DISPLAY_PICTURE_SIZE)); 888 889 /* DISPLAY_PICTURE_SIZE */ 890 //ctx->display_picture_size = 0; 891 reg_value = 0; 892 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, DISPLAY_PICTURE_SIZE, DISPLAY_PICTURE_WIDTH, (((ctx->pic_params->frame_width + 15) / 16) * 16) - 1); 893 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, DISPLAY_PICTURE_SIZE, DISPLAY_PICTURE_HEIGHT, (((ctx->pic_params->frame_height + 15) / 16) * 16) - 1); 894 psb_cmdbuf_rendec_write(cmdbuf, reg_value); 895 // psb_cmdbuf_rendec_end(cmdbuf); 896 897 // psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_CMDS, CODED_PICTURE_SIZE)); 898 /* CODED_PICTURE_SIZE */ 899 //ctx->coded_picture_size = 0; 900 reg_value = 0; 901 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, CODED_PICTURE_SIZE, CODED_PICTURE_WIDTH, (((ctx->pic_params->frame_width + 15) / 16) * 16) - 1); 902 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, CODED_PICTURE_SIZE, CODED_PICTURE_HEIGHT, (((ctx->pic_params->frame_height + 15) / 16) * 16) - 1); 903 psb_cmdbuf_rendec_write(cmdbuf, reg_value); 904 905 /* Set operating mode */ 906 psb_cmdbuf_rendec_write(cmdbuf, ctx->obj_context->operating_mode); 907 908 psb_cmdbuf_rendec_end(cmdbuf); 909 910 /* VP8_LOOP_FILTER_CONTROL */ 911 psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_CMDS, VP8_LOOP_FILTER_CONTROL)); 912 913 reg_value = 0; 914 REGIO_WRITE_FIELD_LITE( reg_value, MSVDX_CMDS, VP8_LOOP_FILTER_CONTROL, VP8_MODE_REF_LF_DELTA_ENABLED, ctx->pic_params->pic_fields.bits.loop_filter_adj_enable); 915 REGIO_WRITE_FIELD_LITE( reg_value, MSVDX_CMDS, VP8_LOOP_FILTER_CONTROL, VP8_SHARPNESS_LEVEL, ctx->pic_params->pic_fields.bits.sharpness_level); 916 psb_cmdbuf_rendec_write(cmdbuf, reg_value); 917 psb_cmdbuf_rendec_end(cmdbuf); 918 919 /* VP8_LOOP_FILTER_BASELINE_LEVEL */ 920 psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_CMDS, VP8_LOOP_FILTER_BASELINE_LEVEL)); 921 reg_value = 0; 922 tng__VP8_compile_baseline_filter_data(ctx); 923 REGIO_WRITE_FIELD( reg_value, MSVDX_CMDS, VP8_LOOP_FILTER_BASELINE_LEVEL, VP8_LF_BASLINE3, ctx->baseline_filter[3] ); 924 REGIO_WRITE_FIELD( reg_value, MSVDX_CMDS, VP8_LOOP_FILTER_BASELINE_LEVEL, VP8_LF_BASLINE2, ctx->baseline_filter[2]); 925 REGIO_WRITE_FIELD( reg_value, MSVDX_CMDS, VP8_LOOP_FILTER_BASELINE_LEVEL, VP8_LF_BASLINE1, ctx->baseline_filter[1]); 926 REGIO_WRITE_FIELD( reg_value, MSVDX_CMDS, VP8_LOOP_FILTER_BASELINE_LEVEL, VP8_LF_BASLINE0, ctx->baseline_filter[0]); 927 psb_cmdbuf_rendec_write(cmdbuf, reg_value); 928 psb_cmdbuf_rendec_end(cmdbuf); 929 930 /* VP8_LOOP_FILTER_REFERENCE_DELTAS */ 931 psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_CMDS, VP8_LOOP_FILTER_REFERENCE_DELTAS)); 932 reg_value = 0; 933 REGIO_WRITE_FIELD(reg_value, MSVDX_CMDS, VP8_LOOP_FILTER_REFERENCE_DELTAS, VP8_REF_LF_DELTA3, ctx->pic_params->loop_filter_deltas_ref_frame[3]); 934 REGIO_WRITE_FIELD(reg_value, MSVDX_CMDS, VP8_LOOP_FILTER_REFERENCE_DELTAS, VP8_REF_LF_DELTA2, ctx->pic_params->loop_filter_deltas_ref_frame[2]); 935 REGIO_WRITE_FIELD(reg_value, MSVDX_CMDS, VP8_LOOP_FILTER_REFERENCE_DELTAS, VP8_REF_LF_DELTA1, ctx->pic_params->loop_filter_deltas_ref_frame[1]); 936 REGIO_WRITE_FIELD(reg_value, MSVDX_CMDS, VP8_LOOP_FILTER_REFERENCE_DELTAS, VP8_REF_LF_DELTA0, ctx->pic_params->loop_filter_deltas_ref_frame[0]); 937 psb_cmdbuf_rendec_write(cmdbuf, reg_value); 938 psb_cmdbuf_rendec_end(cmdbuf); 939 940 /* VP8_LOOP_FILTER_MODE_DELTAS */ 941 psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_CMDS, VP8_LOOP_FILTER_MODE_DELTAS)); 942 reg_value = 0; 943 REGIO_WRITE_FIELD( reg_value, MSVDX_CMDS, VP8_LOOP_FILTER_MODE_DELTAS, VP8_MODE_LF_DELTA3, ctx->pic_params->loop_filter_deltas_mode[3]); 944 REGIO_WRITE_FIELD( reg_value, MSVDX_CMDS, VP8_LOOP_FILTER_MODE_DELTAS, VP8_MODE_LF_DELTA2, ctx->pic_params->loop_filter_deltas_mode[2]); 945 REGIO_WRITE_FIELD( reg_value, MSVDX_CMDS, VP8_LOOP_FILTER_MODE_DELTAS, VP8_MODE_LF_DELTA1, ctx->pic_params->loop_filter_deltas_mode[1]); 946 REGIO_WRITE_FIELD( reg_value, MSVDX_CMDS, VP8_LOOP_FILTER_MODE_DELTAS, VP8_MODE_LF_DELTA0, ctx->pic_params->loop_filter_deltas_mode[0]); 947 psb_cmdbuf_rendec_write(cmdbuf, reg_value); 948 psb_cmdbuf_rendec_end(cmdbuf); 949 950 psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_CMDS, MC_CACHE_CONFIGURATION)); 951 reg_value = 0; 952 REGIO_WRITE_FIELD_LITE( reg_value, MSVDX_CMDS, MC_CACHE_CONFIGURATION, CONFIG_REF_OFFSET, ctx->cache_ref_offset); 953 REGIO_WRITE_FIELD_LITE( reg_value, MSVDX_CMDS, MC_CACHE_CONFIGURATION, CONFIG_ROW_OFFSET, ctx->cache_row_offset); 954 psb_cmdbuf_rendec_write(cmdbuf, reg_value); 955 psb_cmdbuf_rendec_end(cmdbuf); 956 957 /* psb_surface_p forward_ref_surface = ctx->forward_ref_picture->psb_surface; */ 958 /* psb_surface_p golden_ref_surface = ctx->golden_ref_picture->psb_surface; */ 959 960 /* rendec block */ 961 psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_CMDS, INTRA_BUFFER_BASE_ADDRESS)); 962 // psb_cmdbuf_rendec_write_address(cmdbuf, &ctx->MB_flags_buffer, ctx->MB_flags_buffer.buffer_ofs); 963 psb_cmdbuf_rendec_write_address(cmdbuf, &ctx->intra_buffer, ctx->intra_buffer.buffer_ofs); 964 // psb_cmdbuf_rendec_write_address(cmdbuf, &forward_ref_surface->buf, forward_ref_surface->buf.buffer_ofs + forward_ref_surface->chroma_offset); 965 psb_cmdbuf_rendec_end(cmdbuf); 966 967 vld_dec_setup_alternative_frame(ctx->obj_context); /* port from CVldDecoder::ProgramOutputModeRegisters */ 968 } 969 970 static void tng__VP8_set_slice_param(context_VP8_p ctx) { 971 psb_cmdbuf_p cmdbuf = ctx->obj_context->cmdbuf; 972 973 { 974 psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_CMDS, SLICE_PARAMS) ); 975 976 ctx->cmd_slice_params = 0; 977 REGIO_WRITE_FIELD_LITE( ctx->cmd_slice_params, MSVDX_CMDS, SLICE_PARAMS, SLICE_FIELD_TYPE, 0x02 ); // always a frame 978 REGIO_WRITE_FIELD_LITE( ctx->cmd_slice_params, MSVDX_CMDS, SLICE_PARAMS, SLICE_CODE_TYPE, (ctx->pic_params->pic_fields.bits.key_frame == 0)? 0 : 1 ); 979 980 psb_cmdbuf_rendec_write(cmdbuf, ctx->cmd_slice_params); 981 psb_cmdbuf_rendec_end(cmdbuf); 982 } 983 984 *ctx->dec_ctx.p_slice_params = ctx->cmd_slice_params; 985 986 { 987 uint32_t last_mb_row = ((ctx->pic_params->frame_height + 15) / 16) - 1; 988 unsigned int pic_last_mb_xy = (last_mb_row << 8) | (((ctx->pic_params->frame_width + 15) / 16) - 1); 989 unsigned int slice_first_mb_xy = 0; /* NA */ 990 *ctx->dec_ctx.slice_first_pic_last = (slice_first_mb_xy << 16) | pic_last_mb_xy; 991 //ctx->cmd_header->uiSliceFirstMbYX_uiPicLastMbYX = (slice_first_mb_xy << 16) | pic_last_mb_xy; 992 } 993 994 /* if VP8 bitstream is multi-partitioned then convey all the info including buffer offest information for 2nd partition to the firmware */ 995 //ctx->cmd_header->ui32Cmd_AdditionalParams |= ((ctx->pic_params->partition_size[0] + ((ctx->pic_params->pic_fields.bits.key_frame == 0) ? 10 : 3)) & VP8_BUFFOFFSET_MASK) ; 996 //ctx->cmd_header->ui32Cmd_AdditionalParams |= ((ctx->pic_params->num_of_partitions << VP8_PARTITIONSCOUNT_SHIFT) & VP8_PARTITIONSCOUNT_MASK) ; /* if the bistream is multistream */ 997 998 (*ctx->dec_ctx.cmd_params) |= ((ctx->slice_params->partition_size[0] + (ctx->pic_params->bool_coder_ctx.count & 0x07 ? 1 : 0) + (ctx->slice_params->macroblock_offset >> 3)) & VP8_BUFFOFFSET_MASK); 999 (*ctx->dec_ctx.cmd_params) |= (((ctx->slice_params->num_of_partitions - 1) << VP8_PARTITIONSCOUNT_SHIFT) & VP8_PARTITIONSCOUNT_MASK) ; /* if the bistream is multistream */ 1000 // not used in fw ctx->cmd_header->ui32Cmd_AdditionalParams |= ((ctx->pic_params->frame_type << VP8_FRAMETYPE_SHIFT) & VP8_BUFFOFFSET_MASK) ; 1001 } 1002 1003 static void tng__VP8_FE_Registers_Write(context_VP8_p ctx) { 1004 psb_cmdbuf_p cmdbuf = ctx->obj_context->cmdbuf; 1005 uint32_t reg_value; 1006 1007 { 1008 /* set entdec control to a valid codec before accessing SR */ 1009 psb_cmdbuf_reg_start_block(cmdbuf, 0); 1010 1011 psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET (MSVDX_VEC, CR_VEC_ENTDEC_FE_CONTROL), RegEntdecFeControl); 1012 psb_cmdbuf_reg_end_block(cmdbuf); 1013 } 1014 1015 { 1016 psb_cmdbuf_reg_start_block(cmdbuf, 0); 1017 reg_value=0; 1018 1019 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC0, VP8_FE_FRAME_TYPE, (ctx->pic_params->pic_fields.bits.key_frame == 0)? 0 : 1 ); 1020 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC0, VP8_FE_UPDATE_SEGMENTATION_MAP, (ctx->pic_params->pic_fields.bits.update_mb_segmentation_map == 0 )? 0 : 1 ); 1021 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC0, VP8_FE_NUM_PARTITION_MINUS1, ctx->slice_params->num_of_partitions - 2); 1022 1023 /* SEGMENTATION ID CONTROL */ 1024 if(ctx->pic_params->pic_fields.bits.segmentation_enabled) { 1025 if(ctx->pic_params->pic_fields.bits.update_segment_feature_data) { 1026 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC0, VP8_FE_SEG_ID_CTRL, 2); // current 1027 } else { 1028 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC0, VP8_FE_SEG_ID_CTRL, 1); // previous 1029 } 1030 } else { 1031 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC0, VP8_FE_SEG_ID_CTRL, 0); // none 1032 } 1033 1034 psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC0), reg_value); 1035 1036 reg_value=0; 1037 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC1, VP8_FE_PIC_HEIGHT_IN_MBS_LESS1,((ctx->pic_params->frame_height + 15 )>> 4) - 1); 1038 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC1, VP8_FE_PIC_WIDTH_IN_MBS_LESS1, ((ctx->pic_params->frame_width + 15) >> 4) - 1 ); 1039 psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC1), reg_value); 1040 1041 reg_value=0; 1042 /* Important for VP8_FE_DECODE_PRED_NOT_COEFFS. First partition always has macroblock level data. See PDF, p. 34. */ 1043 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC2, VP8_FE_DECODE_PRED_NOT_COEFFS, 1); 1044 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC2, VP8_FE_MB_NO_COEFF_SKIP, ctx->pic_params->pic_fields.bits.mb_no_coeff_skip); 1045 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC2, VP8_FE_SIGN_BIAS_FOR_GF, ctx->pic_params->pic_fields.bits.sign_bias_golden); 1046 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC2, VP8_FE_SIGN_BIAS_FOR_ALTREF, ctx->pic_params->pic_fields.bits.sign_bias_alternate); 1047 psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC2), reg_value); 1048 1049 reg_value=0; 1050 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_FE_MB_SEGMENT_PROBS, VP8_FE_SEGMENT_ID_PROB0, ctx->pic_params->mb_segment_tree_probs[0]); 1051 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_FE_MB_SEGMENT_PROBS, VP8_FE_SEGMENT_ID_PROB1, ctx->pic_params->mb_segment_tree_probs[1]); 1052 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_FE_MB_SEGMENT_PROBS, VP8_FE_SEGMENT_ID_PROB2, ctx->pic_params->mb_segment_tree_probs[2]); 1053 psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET (MSVDX_VEC_VP8, CR_VEC_VP8_FE_MB_SEGMENT_PROBS), reg_value); 1054 1055 reg_value = 0; 1056 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_FE_MB_FLAGS_PROBS, VP8_FE_SKIP_PROB, ctx->pic_params->prob_skip_false); 1057 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_FE_MB_FLAGS_PROBS, VP8_FE_INTRA_MB_PROB, ctx->pic_params->prob_intra); 1058 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_FE_MB_FLAGS_PROBS, VP8_FE_LAST_FRAME_PROB, ctx->pic_params->prob_last); 1059 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_FE_MB_FLAGS_PROBS, VP8_FE_GOLDEN_FRAME_PROB, ctx->pic_params->prob_gf); 1060 psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET (MSVDX_VEC_VP8, CR_VEC_VP8_FE_MB_FLAGS_PROBS), reg_value); 1061 psb_cmdbuf_reg_end_block(cmdbuf); 1062 } 1063 1064 { 1065 psb_cmdbuf_p cmdbuf = ctx->obj_context->cmdbuf; 1066 1067 psb_cmdbuf_reg_start_block(cmdbuf, 0); 1068 1069 /* psb_buffer_p* const ctx->MB_flags_buffer = ctx->MB_flags_buffer.buffer_ofs; */ 1070 /* unsigned int MB_flags_buffer_alloc = ctx->MB_flags_buffer.buffer_ofs; */ 1071 1072 // psb_cmdbuf_reg_set(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC_MB_FLAGS_BASE_ADDRESS), 0); 1073 psb_cmdbuf_reg_set_address(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC_MB_FLAGS_BASE_ADDRESS), 1074 &ctx->MB_flags_buffer, ctx->MB_flags_buffer.buffer_ofs); 1075 psb_cmdbuf_reg_end_block(cmdbuf); 1076 } 1077 1078 { 1079 psb_cmdbuf_p cmdbuf = ctx->obj_context->cmdbuf; 1080 1081 psb_cmdbuf_reg_start_block(cmdbuf, 0); 1082 // psb_cmdbuf_reg_set(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_FE_SEG_ID_BASE_ADDRESS),0); 1083 psb_cmdbuf_reg_set_address(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_FE_SEG_ID_BASE_ADDRESS), &ctx->segID_buffer, ctx->segID_buffer.buffer_ofs); 1084 1085 psb_cmdbuf_reg_end_block(cmdbuf); 1086 } 1087 1088 { 1089 /* add the first partition offset */ 1090 psb_cmdbuf_reg_start_block(cmdbuf, 0); 1091 1092 ctx->DCT_Base_Address_Offset = (ctx->slice_params->partition_size[0] + (ctx->pic_params->bool_coder_ctx.count & 0x07 ? 1 : 0) + (ctx->slice_params->macroblock_offset >> 3)) + 3 * (ctx->slice_params->num_of_partitions - 2) ; 1093 /* REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_FE_DCT_BASE_ADDRESS, VP8_FE_DCT_BASE_ADDRESS, ctx->DCT_Base_Address); */ 1094 psb_cmdbuf_reg_set_address(cmdbuf, REGISTER_OFFSET (MSVDX_VEC_VP8, CR_VEC_VP8_FE_DCT_BASE_ADDRESS), 1095 ctx->dec_ctx.slice_data_buffer, ctx->DCT_Base_Address_Offset); 1096 1097 psb_cmdbuf_reg_end_block(cmdbuf); 1098 } 1099 1100 } 1101 1102 static void tng__VP8_BE_Registers_Write(context_VP8_p ctx) { 1103 psb_cmdbuf_p cmdbuf = ctx->obj_context->cmdbuf; 1104 uint32_t reg_value; 1105 1106 { 1107 /* BE Section */ 1108 psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_VEC, CR_VEC_ENTDEC_BE_CONTROL)); 1109 1110 psb_cmdbuf_rendec_write(cmdbuf, RegEntdecFeControl); 1111 1112 psb_cmdbuf_rendec_end(cmdbuf); 1113 } 1114 1115 { 1116 /* PIC0 */ 1117 psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_BE_PIC0)); 1118 reg_value = 0; 1119 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_BE_PIC0, VP8_BE_FRAME_TYPE, (ctx->pic_params->pic_fields.bits.key_frame == 0)? 0 : 1); 1120 psb_cmdbuf_rendec_write(cmdbuf, reg_value); 1121 1122 /* PIC1 */ 1123 // psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_BE_PIC1)); 1124 reg_value = 0; 1125 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_BE_PIC1, VP8_BE_PIC_HEIGHT_IN_MBS_LESS1, ((ctx->pic_params->frame_height + 15) >> 4) - 1); 1126 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_BE_PIC1, VP8_BE_PIC_WIDTH_IN_MBS_LESS1, ((ctx->pic_params->frame_width + 15) >> 4) - 1); 1127 psb_cmdbuf_rendec_write(cmdbuf, reg_value); 1128 psb_cmdbuf_rendec_end(cmdbuf); 1129 } 1130 1131 { 1132 /* PIC2 */ 1133 psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_BE_PIC2)); 1134 reg_value = 0; 1135 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_BE_PIC2, VP8_BE_DECODE_PRED_NOT_COEFFS, 1); 1136 // REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_BE_PIC2, VP8_BE_USE_STORED_SEGMENT_MAP, 1); 1137 psb_cmdbuf_rendec_write(cmdbuf, reg_value); 1138 psb_cmdbuf_rendec_end(cmdbuf); 1139 } 1140 1141 { 1142 psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_BE_QINDEXMAP)); 1143 tng__VP8_compile_qindex_data(ctx); 1144 /* QINDEX MAP */ 1145 reg_value = 0; 1146 REGIO_WRITE_FIELD(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_BE_QINDEXMAP, VP8_BE_QINDEX_SEG0_DEFAULT, ctx->q_index[0]); 1147 REGIO_WRITE_FIELD(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_BE_QINDEXMAP, VP8_BE_QINDEX_SEG1 , ctx->q_index[1]); 1148 REGIO_WRITE_FIELD(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_BE_QINDEXMAP, VP8_BE_QINDEX_SEG2 , ctx->q_index[2]); 1149 REGIO_WRITE_FIELD(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_BE_QINDEXMAP, VP8_BE_QINDEX_SEG3 , ctx->q_index[3]); 1150 psb_cmdbuf_rendec_write(cmdbuf, reg_value); 1151 psb_cmdbuf_rendec_end(cmdbuf); 1152 } 1153 1154 { 1155 psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_BE_QDELTAS)); 1156 /* QDELTAS - this was removed in msvdx_vec_vp8_regs.def in 1.11 */ 1157 reg_value = 0; 1158 uint16_t Y1_DC_Delta; 1159 Y1_DC_Delta = ctx->iq_params->quantization_index[0][1] - ctx->iq_params->quantization_index[0][0]; 1160 REGIO_WRITE_FIELD(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_BE_QDELTAS, VP8_BE_YDC_DELTA, Y1_DC_Delta); 1161 1162 uint16_t Y2_DC_Delta; 1163 Y2_DC_Delta = ctx->iq_params->quantization_index[0][2] - ctx->iq_params->quantization_index[0][0]; 1164 REGIO_WRITE_FIELD(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_BE_QDELTAS, VP8_BE_Y2DC_DELTA, Y2_DC_Delta); 1165 1166 uint16_t Y2_AC_Delta; 1167 Y2_AC_Delta = ctx->iq_params->quantization_index[0][3] - ctx->iq_params->quantization_index[0][0]; 1168 REGIO_WRITE_FIELD(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_BE_QDELTAS, VP8_BE_Y2AC_DELTA, Y2_AC_Delta); 1169 1170 uint16_t UV_DC_Delta; 1171 UV_DC_Delta = ctx->iq_params->quantization_index[0][4] - ctx->iq_params->quantization_index[0][0]; 1172 REGIO_WRITE_FIELD(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_BE_QDELTAS, VP8_BE_UVDC_DELTA, UV_DC_Delta); 1173 1174 uint16_t UV_AC_Delta; 1175 UV_AC_Delta = ctx->iq_params->quantization_index[0][5] - ctx->iq_params->quantization_index[0][0]; 1176 REGIO_WRITE_FIELD(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_BE_QDELTAS, VP8_BE_UVAC_DELTA, UV_AC_Delta); 1177 1178 psb_cmdbuf_rendec_write(cmdbuf, reg_value); 1179 psb_cmdbuf_rendec_end(cmdbuf); 1180 } 1181 #if 0 1182 { 1183 psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_BE_VLR_BASE_ADDR)); 1184 reg_value = 0; 1185 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_VEC_VP8, CR_VEC_VP8_BE_VLR_BASE_ADDR, VP8_BE_DP_BUFFER_VLR_BASE_ADDR, VLR_OFFSET_VP8_PARSER); 1186 psb_cmdbuf_rendec_write(cmdbuf, reg_value); 1187 psb_cmdbuf_rendec_end(cmdbuf); 1188 } 1189 #endif 1190 1191 { 1192 psb_cmdbuf_p cmdbuf = ctx->obj_context->cmdbuf; 1193 1194 psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_BE_BASE_ADDR_1STPART_PIC)); 1195 1196 // psb_cmdbuf_rendec_write_address(cmdbuf, &ctx->buffer_1st_part, 0); 1197 psb_cmdbuf_rendec_write_address(cmdbuf, &ctx->buffer_1st_part, ctx->buffer_1st_part.buffer_ofs); 1198 1199 psb_cmdbuf_rendec_end(cmdbuf); 1200 } 1201 1202 { 1203 psb_cmdbuf_p cmdbuf = ctx->obj_context->cmdbuf; 1204 1205 psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_BE_BASE_ADDR_CURR)); 1206 1207 // psb_cmdbuf_rendec_write(cmdbuf, 0); 1208 // psb_cmdbuf_rendec_write_address(cmdbuf, &ctx->cur_pic_buffer, 0); 1209 psb_cmdbuf_rendec_write_address(cmdbuf, &ctx->cur_pic_buffer, ctx->cur_pic_buffer.buffer_ofs); 1210 1211 psb_cmdbuf_rendec_end(cmdbuf); 1212 } 1213 } 1214 1215 1216 /*********************************************************************************** 1217 * Description : Set Bool coder context which has been conveyed from application. 1218 ************************************************************************************/ 1219 static void tng__VP8_set_bool_coder_context(context_VP8_p ctx) { 1220 psb_cmdbuf_p cmdbuf = ctx->obj_context->cmdbuf; 1221 uint32_t bool_init = 0; 1222 uint32_t bool_ctrl = 0; 1223 uint32_t reg_value = 0; 1224 { 1225 /* Entdec Front-End controls*/ 1226 psb_cmdbuf_reg_start_block(cmdbuf, 0); 1227 1228 REGIO_WRITE_FIELD_LITE (bool_init, MSVDX_VEC, CR_VEC_BOOL_INIT, BOOL_INIT_RANGE, ctx->pic_params->bool_coder_ctx.range); 1229 REGIO_WRITE_FIELD_LITE (bool_init, MSVDX_VEC, CR_VEC_BOOL_INIT, BOOL_INIT_VALUE, (ctx->pic_params->bool_coder_ctx.value) & 0xff); /* Set only MSB of value param of bool context */ 1230 psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET(MSVDX_VEC, CR_VEC_BOOL_INIT), bool_init); 1231 1232 psb_cmdbuf_reg_end_block(cmdbuf); 1233 } 1234 1235 { 1236 psb_cmdbuf_reg_start_block(cmdbuf, 0); 1237 1238 REGIO_WRITE_FIELD_LITE(bool_ctrl, MSVDX_VEC, CR_VEC_BOOL_CTRL, BOOL_MASTER_SELECT, 0x02); 1239 psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET(MSVDX_VEC, CR_VEC_BOOL_CTRL), bool_ctrl); 1240 1241 psb_cmdbuf_reg_end_block(cmdbuf); 1242 } 1243 1244 { 1245 psb_cmdbuf_rendec_start(cmdbuf, RENDEC_REGISTER_OFFSET(MSVDX_CMDS, MC_CACHE_CONFIGURATION)); 1246 REGIO_WRITE_FIELD_LITE( reg_value, MSVDX_CMDS, MC_CACHE_CONFIGURATION, CONFIG_REF_OFFSET, ctx->cache_ref_offset); 1247 REGIO_WRITE_FIELD_LITE( reg_value, MSVDX_CMDS, MC_CACHE_CONFIGURATION, CONFIG_ROW_OFFSET, ctx->cache_row_offset); 1248 psb_cmdbuf_rendec_write(cmdbuf, reg_value); 1249 psb_cmdbuf_rendec_end(cmdbuf); 1250 } 1251 } 1252 1253 /*********************************************************************************** 1254 * Description : Write probability data in buffer according to MSVDX setting. 1255 ************************************************************************************/ 1256 static void tng_KeyFrame_BModeProbsDataCompile(Probability* ui8_probs_to_write, uint32_t* ui32_probs_buffer) { 1257 uint32_t dim0, dim1; 1258 uint32_t i, j, address; 1259 uint32_t src_tab_offset = 0; 1260 1261 address = 0; 1262 1263 for(dim1 = 0; dim1 < 10; dim1++) { 1264 for(dim0 = 0; dim0 < 10; dim0++) { 1265 j =0; 1266 for (i =0 ; i < CABAC_LSR_KeyFrame_BModeProb_Stride ; i += 4) { 1267 *(ui32_probs_buffer+ address + j++ ) = 1268 (uint32_t)ui8_probs_to_write[CABAC_LSR_KeyFrame_BModeProb_ToIdxMap[i] + src_tab_offset ] 1269 | (uint32_t)ui8_probs_to_write[CABAC_LSR_KeyFrame_BModeProb_ToIdxMap[i+1] + src_tab_offset ] << 8 1270 | (uint32_t)ui8_probs_to_write[CABAC_LSR_KeyFrame_BModeProb_ToIdxMap[i+2] + src_tab_offset ] << 16 1271 | (uint32_t)ui8_probs_to_write[CABAC_LSR_KeyFrame_BModeProb_ToIdxMap[i+3] + src_tab_offset ] << 24; 1272 } 1273 /* increment the address by the stride */ 1274 address += (CABAC_LSR_KeyFrame_BModeProb_Stride >> 2); 1275 /* increment source table offset */ 1276 src_tab_offset += CABAC_LSR_KeyFrame_BModeProb_Valid; 1277 } 1278 } 1279 } 1280 1281 /*********************************************************************************** 1282 * Description : Write probability data in buffer according to MSVDX setting. 1283 ************************************************************************************/ 1284 static void tng_InterFrame_YModeProbsDataCompile(Probability* ui8_probs_to_write, uint32_t* ui32_probs_buffer) { 1285 *(ui32_probs_buffer) = (uint32_t)ui8_probs_to_write[CABAC_LSR_InterFrame_YModeProb_ToIdxMap[0]] 1286 | (uint32_t)ui8_probs_to_write[CABAC_LSR_InterFrame_YModeProb_ToIdxMap[1]] << 8 1287 | (uint32_t)ui8_probs_to_write[CABAC_LSR_InterFrame_YModeProb_ToIdxMap[2]] << 16 1288 | (uint32_t)ui8_probs_to_write[CABAC_LSR_InterFrame_YModeProb_ToIdxMap[3]] << 24; 1289 } 1290 1291 /*********************************************************************************** 1292 * Description : Write probability data in buffer according to MSVDX setting. 1293 ************************************************************************************/ 1294 static void tng_InterFrame_UVModeProbsDataCompile(Probability* ui8_probs_to_write, uint32_t* ui32_probs_buffer) { 1295 *(ui32_probs_buffer) = (uint32_t)ui8_probs_to_write[CABAC_LSR_InterFrame_UVModeProb_ToIdxMap[0]] 1296 | (uint32_t)ui8_probs_to_write[CABAC_LSR_InterFrame_UVModeProb_ToIdxMap[1]] << 8 1297 | (uint32_t)ui8_probs_to_write[CABAC_LSR_InterFrame_UVModeProb_ToIdxMap[2]] << 16; 1298 } 1299 1300 /*********************************************************************************** 1301 * Description : Write probability data in buffer according to MSVDX setting. 1302 ************************************************************************************/ 1303 static void tng_InterFrame_MVContextProbsDataCompile(uint8_t* ui8_probs_to_write, uint32_t* ui32_probs_buffer) { 1304 uint32_t dim0; 1305 uint32_t i, j, address; 1306 uint32_t src_tab_offset = 0; 1307 1308 address = 0; 1309 1310 for(dim0 = 0; dim0 < 2; dim0++) { 1311 j = 0; 1312 for (i =0 ; i < CABAC_LSR_InterFrame_MVContextProb_Stride ; i += 4) { 1313 *(ui32_probs_buffer+ address + j++ ) = 1314 (uint32_t)ui8_probs_to_write[CABAC_LSR_InterFrame_MVContextProb_ToIdxMap[i] + src_tab_offset ] 1315 | (uint32_t)ui8_probs_to_write[CABAC_LSR_InterFrame_MVContextProb_ToIdxMap[i+1] + src_tab_offset ] << 8 1316 | (uint32_t)ui8_probs_to_write[CABAC_LSR_InterFrame_MVContextProb_ToIdxMap[i+2] + src_tab_offset ] << 16 1317 | (uint32_t)ui8_probs_to_write[CABAC_LSR_InterFrame_MVContextProb_ToIdxMap[i+3] + src_tab_offset ] << 24; 1318 } 1319 /* increment the address by the stride */ 1320 address += (CABAC_LSR_InterFrame_MVContextProb_Stride >> 2); 1321 /* increment source table offset */ 1322 src_tab_offset += CABAC_LSR_InterFrame_MVContextProb_Valid; 1323 } 1324 } 1325 1326 /*********************************************************************************** 1327 * Description : Write probability data in buffer according to MSVDX setting. 1328 ************************************************************************************/ 1329 static void tng_DCT_Coefficient_ProbsDataCompile(Probability* ui8_probs_to_write, uint32_t* ui32_probs_buffer) { 1330 uint32_t dim0, dim1, dim2; 1331 uint32_t i, j, address; 1332 uint32_t src_tab_offset = 0; 1333 1334 address = 0; 1335 1336 for(dim2 = 0; dim2 < 4; dim2++) { 1337 for(dim1 = 0; dim1 < 8; dim1++) { 1338 for(dim0 = 0; dim0 < 3; dim0++) { 1339 j =0; 1340 for (i =0 ; i < CABAC_LSR_CoefficientProb_Stride ; i += 4) { 1341 *(ui32_probs_buffer + address + j++ ) = 1342 (uint32_t)ui8_probs_to_write[CABAC_LSR_CoefficientProb_ToIdxMap[i] + src_tab_offset] 1343 | (uint32_t)ui8_probs_to_write[CABAC_LSR_CoefficientProb_ToIdxMap[i+1] + src_tab_offset] << 8 1344 | (uint32_t)ui8_probs_to_write[CABAC_LSR_CoefficientProb_ToIdxMap[i+2] + src_tab_offset] << 16 1345 | (uint32_t)ui8_probs_to_write[CABAC_LSR_CoefficientProb_ToIdxMap[i+3] + src_tab_offset] << 24; 1346 1347 } 1348 /* increment the address by the stride */ 1349 address += (CABAC_LSR_CoefficientProb_Stride >> 2); 1350 /* increment source table offset */ 1351 src_tab_offset += CABAC_LSR_CoefficientProb_Valid; 1352 } 1353 } 1354 } 1355 } 1356 1357 /*********************************************************************************** 1358 * Description : programme the DMA to send probability data. 1359 ************************************************************************************/ 1360 static void tng__VP8_set_probility_reg(context_VP8_p ctx) { 1361 psb_cmdbuf_p cmdbuf = ctx->obj_context->cmdbuf; 1362 uint32_t *probs_buffer_1stPart , *probs_buffer_2ndPart; 1363 //uint32_t* probs_table_1stbuffer = NULL; 1364 1365 /* First write the data for the first partition */ 1366 /* Write the probability data in the probability data buffer */ 1367 psb_buffer_map(&ctx->probability_data_1st_part, (unsigned char **)&probs_buffer_1stPart); 1368 if(NULL == probs_buffer_1stPart) { 1369 drv_debug_msg(VIDEO_DEBUG_GENERAL, "tng__VP8_set_probility_reg: map buffer fail\n"); 1370 return; 1371 } 1372 { 1373 memset(probs_buffer_1stPart, 0, sizeof(ctx->probability_data_1st_part)); 1374 if(ctx->pic_params->pic_fields.bits.key_frame == 0) { 1375 tng_KeyFrame_BModeProbsDataCompile((uint8_t *)b_mode_prob, probs_buffer_1stPart); 1376 } else { 1377 tng_InterFrame_YModeProbsDataCompile(ctx->pic_params->y_mode_probs, probs_buffer_1stPart); 1378 1379 probs_buffer_1stPart += ( CABAC_LSR_InterFrame_UVModeProb_Address >> 2); 1380 tng_InterFrame_UVModeProbsDataCompile(ctx->pic_params->uv_mode_probs, probs_buffer_1stPart); 1381 1382 probs_buffer_1stPart += (CABAC_LSR_InterFrame_MVContextProb_Address >>2) - ( CABAC_LSR_InterFrame_UVModeProb_Address >> 2); 1383 tng_InterFrame_MVContextProbsDataCompile((uint8_t *)ctx->pic_params->mv_probs, probs_buffer_1stPart); 1384 } 1385 1386 psb_buffer_unmap(&ctx->probability_data_1st_part); 1387 psb_cmdbuf_dma_write_cmdbuf(cmdbuf, &ctx->probability_data_1st_part, 0, 1388 ctx->probability_data_1st_part_size, 0, 1389 DMA_TYPE_PROBABILITY_DATA); 1390 } 1391 1392 /* Write the probability data for the second partition and create a linked list */ 1393 psb_buffer_map(&ctx->probability_data_2nd_part, (unsigned char **)&probs_buffer_2ndPart); 1394 if(NULL == probs_buffer_2ndPart) { 1395 drv_debug_msg(VIDEO_DEBUG_GENERAL, "tng__VP8_set_probility_reg: map buffer fail\n"); 1396 return; 1397 } 1398 1399 { 1400 memset(probs_buffer_2ndPart, 0, sizeof(ctx->probability_data_2nd_part)); 1401 /* for any other partition */ 1402 tng_DCT_Coefficient_ProbsDataCompile((Probability *)ctx->probs_params->dct_coeff_probs, probs_buffer_2ndPart); 1403 1404 psb_buffer_unmap(&ctx->probability_data_2nd_part); 1405 1406 } 1407 } 1408 1409 static void tng__VP8_begin_slice(context_DEC_p dec_ctx, VASliceParameterBufferBase *vld_slice_param) 1410 { 1411 VASliceParameterBufferVP8 *slice_param = (VASliceParameterBufferVP8 *) vld_slice_param; 1412 context_VP8_p ctx = (context_VP8_p)dec_ctx; 1413 1414 dec_ctx->bits_offset = slice_param->macroblock_offset; 1415 ctx->slice_params = slice_param; 1416 /* dec_ctx->SR_flags = 0; */ 1417 } 1418 1419 static void tng__VP8_process_slice_data(context_DEC_p dec_ctx, VASliceParameterBufferBase *vld_slice_param) 1420 { 1421 VASliceParameterBufferVP8 *slice_param = (VASliceParameterBufferVP8 *) vld_slice_param; 1422 context_VP8_p ctx = (context_VP8_p)dec_ctx; 1423 1424 tng__CMDS_registers_write(ctx); 1425 tng__VP8_FE_Registers_Write(ctx); 1426 tng__VP8_BE_Registers_Write(ctx); 1427 tng__VP8_set_slice_param(ctx); 1428 tng__VP8_set_probility_reg(ctx); 1429 tng__VP8_set_target_picture(ctx); 1430 tng__VP8_set_reference_picture(ctx); 1431 tng__VP8_set_bool_coder_context(ctx); 1432 } 1433 1434 static void tng__VP8_end_slice(context_DEC_p dec_ctx) 1435 { 1436 context_VP8_p ctx = (context_VP8_p)dec_ctx; 1437 1438 #ifdef PSBVIDEO_MSVDX_EC 1439 if (ctx->obj_context->driver_data->ec_enabled) 1440 ctx->obj_context->flags |= (FW_ERROR_DETECTION_AND_RECOVERY); /* FW_ERROR_DETECTION_AND_RECOVERY */ 1441 #endif 1442 1443 ctx->obj_context->first_mb = (*(ctx->dec_ctx.slice_first_pic_last) >> 16); 1444 ctx->obj_context->last_mb = (*(ctx->dec_ctx.slice_first_pic_last) & 0xffff); 1445 } 1446 1447 static VAStatus tng_VP8_BeginPicture( 1448 object_context_p obj_context) { 1449 INIT_CONTEXT_VP8 1450 1451 if (ctx->pic_params) { 1452 free(ctx->pic_params); 1453 ctx->pic_params = NULL; 1454 } 1455 1456 if (ctx->probs_params) { 1457 free(ctx->probs_params); 1458 ctx->probs_params = NULL; 1459 } 1460 1461 if (ctx->iq_params) { 1462 free(ctx->iq_params); 1463 ctx->iq_params = NULL; 1464 } 1465 /* ctx->table_stats[VP8_VLC_NUM_TABLES-1].size = 16; */ 1466 ctx->slice_count = 0; 1467 1468 return VA_STATUS_SUCCESS; 1469 } 1470 1471 #ifdef PSBVIDEO_MSVDX_EC 1472 static void tng__VP8_choose_ec_frames(context_VP8_p ctx) 1473 { 1474 ctx->obj_context->ec_target = NULL; 1475 if (ctx->pic_params == NULL) 1476 return; 1477 1478 if (ctx->pic_params->pic_fields.bits.key_frame == 0) 1479 { 1480 /* To conceal key frame using golden referece frame */ 1481 ctx->obj_context->ec_target = ctx->golden_ref_picture; 1482 /* In case the next frame is an I frame we will need this */ 1483 ctx->obj_context->ec_candidate = ctx->obj_context->current_render_target; 1484 } else { 1485 /* To conceal inter frame using last reference frame */ 1486 ctx->obj_context->ec_target = ctx->last_ref_picture; 1487 } 1488 1489 /* Otherwise we conceal from the previous I or P frame*/ 1490 if (!ctx->obj_context->ec_target) 1491 { 1492 ctx->obj_context->ec_target = ctx->obj_context->ec_candidate; 1493 } 1494 1495 if (!ctx->obj_context->ec_target) { 1496 ctx->obj_context->ec_target = ctx->obj_context->current_render_target; 1497 } 1498 } 1499 #endif 1500 1501 static VAStatus tng_VP8_process_buffer( 1502 context_DEC_p dec_ctx, 1503 object_buffer_p buffer) { 1504 context_VP8_p ctx = (context_VP8_p)dec_ctx; 1505 VAStatus vaStatus = VA_STATUS_SUCCESS; 1506 object_buffer_p obj_buffer = buffer; 1507 1508 switch (obj_buffer->type) { 1509 case VAPictureParameterBufferType: 1510 vaStatus = tng__VP8_process_picture_param(ctx, obj_buffer); 1511 DEBUG_FAILURE; 1512 break; 1513 1514 case VAProbabilityBufferType: 1515 vaStatus = tng__VP8_process_probility_param(ctx, obj_buffer); 1516 DEBUG_FAILURE; 1517 break; 1518 1519 case VAIQMatrixBufferType: 1520 vaStatus = tng__VP8_process_iq_matrix(ctx, obj_buffer); 1521 DEBUG_FAILURE; 1522 break; 1523 1524 default: 1525 vaStatus = VA_STATUS_ERROR_UNKNOWN; 1526 DEBUG_FAILURE; 1527 } 1528 1529 return vaStatus; 1530 } 1531 1532 static VAStatus tng_VP8_EndPicture( 1533 object_context_p obj_context) { 1534 INIT_CONTEXT_VP8 1535 psb_surface_p target_surface = ctx->obj_context->current_render_target->psb_surface; 1536 psb_driver_data_p driver_data = obj_context->driver_data; 1537 VAStatus vaStatus = VA_STATUS_SUCCESS; 1538 1539 object_surface_p obj_surface = NULL; 1540 if (!obj_surface) 1541 obj_surface = obj_context->current_render_target; 1542 1543 #ifdef PSBVIDEO_MSVDX_EC 1544 if (driver_data->ec_enabled) { 1545 uint32_t rotation_flags = 0; 1546 uint32_t ext_stride_a = 0; 1547 object_surface_p ec_target; 1548 1549 tng__VP8_choose_ec_frames(ctx); 1550 ec_target = ctx->obj_context->ec_target; 1551 //ec_target = obj_surface; 1552 REGIO_WRITE_FIELD_LITE(ext_stride_a, MSVDX_CMDS, EXTENDED_ROW_STRIDE, EXT_ROW_STRIDE, target_surface->stride / 64); 1553 1554 /* FIXME ec ignor rotate condition */ 1555 if(ec_target) { 1556 if (psb_context_get_next_cmdbuf(ctx->obj_context)) { 1557 vaStatus = VA_STATUS_ERROR_UNKNOWN; 1558 DEBUG_FAILURE; 1559 return vaStatus; 1560 } 1561 1562 if (psb_context_submit_host_be_opp(ctx->obj_context, 1563 &target_surface->buf, 1564 &ec_target->psb_surface->buf, 1565 NULL, 1566 (ctx->pic_params->frame_width+15)/16, 1567 (ctx->pic_params->frame_height+15)/16, 1568 rotation_flags, 1569 2,//ctx->field_type, 1570 ext_stride_a, 1571 target_surface->chroma_offset + target_surface->buf.buffer_ofs, 1572 ec_target->psb_surface->chroma_offset + ec_target->psb_surface->buf.buffer_ofs)) { 1573 return VA_STATUS_ERROR_UNKNOWN; 1574 } 1575 } 1576 } 1577 #endif 1578 1579 if (psb_context_flush_cmdbuf(ctx->obj_context)) { 1580 return VA_STATUS_ERROR_UNKNOWN; 1581 } 1582 1583 if (ctx->pic_params) { 1584 free(ctx->pic_params); 1585 ctx->pic_params = NULL; 1586 } 1587 1588 if (ctx->probs_params) { 1589 free(ctx->probs_params); 1590 ctx->probs_params = NULL; 1591 } 1592 1593 if (ctx->iq_params) { 1594 free(ctx->iq_params); 1595 ctx->iq_params = NULL; 1596 } 1597 1598 return VA_STATUS_SUCCESS; 1599 } 1600 1601 1602 struct format_vtable_s tng_VP8_vtable = { 1603 queryConfigAttributes: 1604 tng_VP8_QueryConfigAttributes, 1605 validateConfig: 1606 tng_VP8_ValidateConfig, 1607 createContext: 1608 tng_VP8_CreateContext, 1609 destroyContext: 1610 tng_VP8_DestroyContext, 1611 beginPicture: 1612 tng_VP8_BeginPicture, 1613 renderPicture: 1614 vld_dec_RenderPicture, 1615 endPicture: 1616 tng_VP8_EndPicture 1617 }; 1618 1619 1620
