| /hardware/intel/img/psb_video/src/ |
| tng_ved_scaling.c | 250 IMG_UINT32 reg_value; local
258 reg_value = 0;
259 REGIO_WRITE_FIELD(reg_value, MSVDX_CMDS, HORIZONTAL_LUMA_COEFFICIENTS, HOR_LUMA_COEFF_3, calc_table[0][j]);
260 REGIO_WRITE_FIELD(reg_value, MSVDX_CMDS, HORIZONTAL_LUMA_COEFFICIENTS, HOR_LUMA_COEFF_2, calc_table[1][j]);
261 REGIO_WRITE_FIELD(reg_value, MSVDX_CMDS, HORIZONTAL_LUMA_COEFFICIENTS, HOR_LUMA_COEFF_1, calc_table[2][j]);
262 REGIO_WRITE_FIELD(reg_value, MSVDX_CMDS, HORIZONTAL_LUMA_COEFFICIENTS, HOR_LUMA_COEFF_0, calc_table[3][j]);
264 ctx->scaler_coeff_reg[/* Luma */ 0][/* Hori */ 0][i] = reg_value;
266 reg_value = 0;
267 REGIO_WRITE_FIELD(reg_value, MSVDX_CMDS, HORIZONTAL_CHROMA_COEFFICIENTS, HOR_CHROMA_COEFF_3, calc_table[0][j]);
268 REGIO_WRITE_FIELD(reg_value, MSVDX_CMDS, HORIZONTAL_CHROMA_COEFFICIENTS, HOR_CHROMA_COEFF_2, calc_table[1][j])
[all...] |
| tng_VP8.c | 610 uint32_t reg_value; local
806 uint32_t reg_value;
849 reg_value = 0;
850 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, MC_CACHE_CONFIGURATION, CONFIG_REF_OFFSET, ctx->cache_ref_offset );
851 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, MC_CACHE_CONFIGURATION, CONFIG_ROW_OFFSET, ctx->cache_row (…)
877 uint32_t reg_value; local
1005 uint32_t reg_value; local
1104 uint32_t reg_value; local
1223 uint32_t reg_value = 0; local
[all...] |
| tng_jpegdec.c | 665 uint32_t reg_value; local
676 reg_value = 0;
678 REGIO_WRITE_FIELD_LITE( reg_value, MSVDX_VEC, CR_VEC_VLC_TABLE_ADDR0, VLC_TABLE_ADDR0, table_address );
680 REGIO_WRITE_FIELD_LITE( reg_value, MSVDX_VEC, CR_VEC_VLC_TABLE_ADDR0, VLC_TABLE_ADDR1, table_address );
681 psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET( MSVDX_VEC, CR_VEC_VLC_TABLE_ADDR0 ), reg_value);
683 reg_value = 0;
685 REGIO_WRITE_FIELD_LITE( reg_value, MSVDX_VEC, CR_VEC_VLC_TABLE_ADDR2, VLC_TABLE_ADDR4, table_address );
687 REGIO_WRITE_FIELD_LITE( reg_value, MSVDX_VEC, CR_VEC_VLC_TABLE_ADDR2, VLC_TABLE_ADDR5, table_address );
688 psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET( MSVDX_VEC, CR_VEC_VLC_TABLE_ADDR2 ), reg_value);
693 reg_value = 0
858 uint32_t reg_value; local
876 uint32_t reg_value; local
[all...] |
| pnw_H264.c | 553 uint32_t reg_value; local
768 reg_value = 0;
769 REGIO_WRITE_FIELD(reg_value, MSVDX_VEC_H264, CR_VEC_H264_BE_COL_PIC0, COL_NOTFRAMEFLAG, (PICT_FRAME != ctx->pic_type) ? 1 : 0);
770 REGIO_WRITE_FIELD(reg_value, MSVDX_VEC_H264, CR_VEC_H264_BE_COL_PIC0, COL_MBAFFFRAMEFLAG, pic_params->seq_fields.bits.mb_adaptive_frame_field_flag);
771 SET_SURFACE_INFO_col_pic_params(target_surface, reg_value);
1002 uint32_t reg_value; local
1051 uint32_t reg_value; local
1155 uint32_t reg_value; local
1192 uint32_t reg_value; local
[all...] |
| tng_yuv_processor.c | 131 uint32_t reg_value; local
135 reg_value = 0;
136 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, DISPLAY_PICTURE_SIZE, DISPLAY_PICTURE_HEIGHT, (ctx->display_height) - 1);
137 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, DISPLAY_PICTURE_SIZE, DISPLAY_PICTURE_WIDTH, (ctx->display_width) - 1);
138 psb_cmdbuf_rendec_write(cmdbuf, reg_value);
140 reg_value = 0;
141 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, CODED_PICTURE_SIZE, CODED_PICTURE_HEIGHT, (ctx->coded_height) - 1);
142 REGIO_WRITE_FIELD_LITE(reg_value, MSVDX_CMDS, CODED_PICTURE_SIZE, CODED_PICTURE_WIDTH, (ctx->coded_width) - 1);
143 psb_cmdbuf_rendec_write(cmdbuf, reg_value);
148 reg_value = 0
196 uint32_t reg_value; local
[all...] |
| pnw_VC1.c | 1701 uint32_t reg_value; local
2298 uint32_t reg_value; local
2323 uint32_t reg_value; local
[all...] |
| /device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt6795/drivers/timer/ |
| mt_cpuxgpt.c | 42 unsigned int reg_value)
58 if (!(reg_value & 1))
|
| /hardware/intel/img/psb_video/src/mrst/ |
| psb_H264.c | 611 uint32_t reg_value; local
752 reg_value = 0;
753 REGIO_WRITE_FIELD(reg_value, MSVDX_VEC_H264, CR_VEC_H264_BE_COL_PIC0, COL_NOTFRAMEFLAG, (PICT_FRAME != ctx->pic_type) ? 1 : 0);
754 REGIO_WRITE_FIELD(reg_value, MSVDX_VEC_H264, CR_VEC_H264_BE_COL_PIC0, COL_MBAFFFRAMEFLAG, pic_params->seq_fields.bits.mb_adaptive_frame_field_flag);
755 SET_SURFACE_INFO_col_pic_params(target_surface, reg_value);
864 uint32_t reg_value; local
906 uint32_t reg_value; local
1010 uint32_t reg_value; local
1079 uint32_t reg_value; local
[all...] |
| psb_VC1.c | 1702 uint32_t reg_value; local
2312 uint32_t reg_value; local
2348 uint32_t reg_value; local
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_pair_schedule.c | 51 struct reg_value * WriteValues[4];
52 struct reg_value * ReadValues[12];
97 struct reg_value { struct
115 struct reg_value *Next; /**< Pointer to the next value to be written to the same register */
119 struct reg_value * Values[4];
160 static struct reg_value ** get_reg_valuep(struct schedule_state * s,
286 struct reg_value * v = sinst->WriteValues[i];
372 struct reg_value * v = sinst->ReadValues[i];
390 struct reg_value * v = sinst->WriteValues[i];
914 struct reg_value ** new_regvalp = get_reg_valuep
[all...] |
| /device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/ |
| core_cm3.h | 1313 uint32_t reg_value; local
[all...] |
| core_cm4.h | 1464 uint32_t reg_value; local
[all...] |
| core_sc300.h | 1293 uint32_t reg_value; local
[all...] |
| core_cm7.h | 1651 uint32_t reg_value; local
[all...] |
| /toolchain/binutils/binutils-2.27/opcodes/ |
| ns32k-dis.c | 249 list_search (int reg_value, const struct ns32k_option *optionP, char *result)
253 if ((reg_value & optionP->match) == optionP->value)
|
| /external/vixl/src/aarch64/ |
| debugger-aarch64.cc | 608 const uint64_t reg_value = local
614 uint64_t data = reg_value >> (reg_size - (i * format_size));
824 uint64_t reg_value = local
827 memcpy(&address, ®_value, sizeof(address));
[all...] |
| /system/core/debuggerd/libdebuggerd/ |
| tombstone.cpp | 389 regs->IterateRegisters([log, map, memory](const char* reg_name, uint64_t reg_value) {
393 map->FillIn(reg_value, &map_info);
397 dump_memory(log, memory, reg_value, label);
|
| /device/google/contexthub/firmware/os/drivers/st_lsm6dsm/ |
| st_lsm6dsm.c | 2702 uint8_t i, reg_value = LSM6DSM_SENSOR_SLAVE_BARO_POWER_BASE; local
2779 uint8_t i, reg_value = LSM6DSM_SENSOR_SLAVE_BARO_POWER_BASE; local
[all...] |
| /external/v8/src/compiler/ppc/ |
| code-generator-ppc.cc | 2104 int reg_value = -1; local
[all...] |
