1 /**************************************************************************//** 2 * @file core_cm7.h 3 * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File 4 * @version V4.00 5 * @date 01. September 2014 6 * 7 * @note 8 * 9 ******************************************************************************/ 10 /* Copyright (c) 2009 - 2014 ARM LIMITED 11 12 All rights reserved. 13 Redistribution and use in source and binary forms, with or without 14 modification, are permitted provided that the following conditions are met: 15 - Redistributions of source code must retain the above copyright 16 notice, this list of conditions and the following disclaimer. 17 - Redistributions in binary form must reproduce the above copyright 18 notice, this list of conditions and the following disclaimer in the 19 documentation and/or other materials provided with the distribution. 20 - Neither the name of ARM nor the names of its contributors may be used 21 to endorse or promote products derived from this software without 22 specific prior written permission. 23 * 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 POSSIBILITY OF SUCH DAMAGE. 35 ---------------------------------------------------------------------------*/ 36 37 38 #if defined ( __ICCARM__ ) 39 #pragma system_include /* treat file as system include file for MISRA check */ 40 #endif 41 42 #ifndef __CORE_CM7_H_GENERIC 43 #define __CORE_CM7_H_GENERIC 44 45 #ifdef __cplusplus 46 extern "C" { 47 #endif 48 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 50 CMSIS violates the following MISRA-C:2004 rules: 51 52 \li Required Rule 8.5, object/function definition in header file.<br> 53 Function definitions in header files are used to allow 'inlining'. 54 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 56 Unions are used for effective representation of core registers. 57 58 \li Advisory Rule 19.7, Function-like macro defined.<br> 59 Function-like macros are used to allow more efficient code. 60 */ 61 62 63 /******************************************************************************* 64 * CMSIS definitions 65 ******************************************************************************/ 66 /** \ingroup Cortex_M7 67 @{ 68 */ 69 70 /* CMSIS CM7 definitions */ 71 #define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ 72 #define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ 73 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \ 74 __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ 75 76 #define __CORTEX_M (0x07) /*!< Cortex-M Core */ 77 78 79 #if defined ( __CC_ARM ) 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 82 #define __STATIC_INLINE static __inline 83 84 #elif defined ( __GNUC__ ) 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 87 #define __STATIC_INLINE static inline 88 89 #elif defined ( __ICCARM__ ) 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ 92 #define __STATIC_INLINE static inline 93 94 #elif defined ( __TMS470__ ) 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ 96 #define __STATIC_INLINE static inline 97 98 #elif defined ( __TASKING__ ) 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 101 #define __STATIC_INLINE static inline 102 103 #elif defined ( __CSMC__ ) 104 #define __packed 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ 107 #define __STATIC_INLINE static inline 108 109 #endif 110 111 /** __FPU_USED indicates whether an FPU is used or not. 112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. 113 */ 114 #if defined ( __CC_ARM ) 115 #if defined __TARGET_FPU_VFP 116 #if (__FPU_PRESENT == 1) 117 #define __FPU_USED 1 118 #else 119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 120 #define __FPU_USED 0 121 #endif 122 #else 123 #define __FPU_USED 0 124 #endif 125 126 #elif defined ( __GNUC__ ) 127 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 128 #if (__FPU_PRESENT == 1) 129 #define __FPU_USED 1 130 #else 131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 132 #define __FPU_USED 0 133 #endif 134 #else 135 #define __FPU_USED 0 136 #endif 137 138 #elif defined ( __ICCARM__ ) 139 #if defined __ARMVFP__ 140 #if (__FPU_PRESENT == 1) 141 #define __FPU_USED 1 142 #else 143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 144 #define __FPU_USED 0 145 #endif 146 #else 147 #define __FPU_USED 0 148 #endif 149 150 #elif defined ( __TMS470__ ) 151 #if defined __TI_VFP_SUPPORT__ 152 #if (__FPU_PRESENT == 1) 153 #define __FPU_USED 1 154 #else 155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 156 #define __FPU_USED 0 157 #endif 158 #else 159 #define __FPU_USED 0 160 #endif 161 162 #elif defined ( __TASKING__ ) 163 #if defined __FPU_VFP__ 164 #if (__FPU_PRESENT == 1) 165 #define __FPU_USED 1 166 #else 167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 168 #define __FPU_USED 0 169 #endif 170 #else 171 #define __FPU_USED 0 172 #endif 173 174 #elif defined ( __CSMC__ ) /* Cosmic */ 175 #if ( __CSMC__ & 0x400) // FPU present for parser 176 #if (__FPU_PRESENT == 1) 177 #define __FPU_USED 1 178 #else 179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 180 #define __FPU_USED 0 181 #endif 182 #else 183 #define __FPU_USED 0 184 #endif 185 #endif 186 187 #include <stdint.h> /* standard types definitions */ 188 #include <core_cmInstr.h> /* Core Instruction Access */ 189 #include <core_cmFunc.h> /* Core Function Access */ 190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */ 191 192 #ifdef __cplusplus 193 } 194 #endif 195 196 #endif /* __CORE_CM7_H_GENERIC */ 197 198 #ifndef __CMSIS_GENERIC 199 200 #ifndef __CORE_CM7_H_DEPENDANT 201 #define __CORE_CM7_H_DEPENDANT 202 203 #ifdef __cplusplus 204 extern "C" { 205 #endif 206 207 /* check device defines and use defaults */ 208 #if defined __CHECK_DEVICE_DEFINES 209 #ifndef __CM7_REV 210 #define __CM7_REV 0x0000 211 #warning "__CM7_REV not defined in device header file; using default!" 212 #endif 213 214 #ifndef __FPU_PRESENT 215 #define __FPU_PRESENT 0 216 #warning "__FPU_PRESENT not defined in device header file; using default!" 217 #endif 218 219 #ifndef __MPU_PRESENT 220 #define __MPU_PRESENT 0 221 #warning "__MPU_PRESENT not defined in device header file; using default!" 222 #endif 223 224 #ifndef __ICACHE_PRESENT 225 #define __ICACHE_PRESENT 0 226 #warning "__ICACHE_PRESENT not defined in device header file; using default!" 227 #endif 228 229 #ifndef __DCACHE_PRESENT 230 #define __DCACHE_PRESENT 0 231 #warning "__DCACHE_PRESENT not defined in device header file; using default!" 232 #endif 233 234 #ifndef __DTCM_PRESENT 235 #define __DTCM_PRESENT 0 236 #warning "__DTCM_PRESENT not defined in device header file; using default!" 237 #endif 238 239 #ifndef __NVIC_PRIO_BITS 240 #define __NVIC_PRIO_BITS 3 241 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 242 #endif 243 244 #ifndef __Vendor_SysTickConfig 245 #define __Vendor_SysTickConfig 0 246 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 247 #endif 248 #endif 249 250 /* IO definitions (access restrictions to peripheral registers) */ 251 /** 252 \defgroup CMSIS_glob_defs CMSIS Global Defines 253 254 <strong>IO Type Qualifiers</strong> are used 255 \li to specify the access to peripheral variables. 256 \li for automatic generation of peripheral register debug information. 257 */ 258 #ifdef __cplusplus 259 #define __I volatile /*!< Defines 'read only' permissions */ 260 #else 261 #define __I volatile const /*!< Defines 'read only' permissions */ 262 #endif 263 #define __O volatile /*!< Defines 'write only' permissions */ 264 #define __IO volatile /*!< Defines 'read / write' permissions */ 265 266 /*@} end of group Cortex_M7 */ 267 268 269 270 /******************************************************************************* 271 * Register Abstraction 272 Core Register contain: 273 - Core Register 274 - Core NVIC Register 275 - Core SCB Register 276 - Core SysTick Register 277 - Core Debug Register 278 - Core MPU Register 279 - Core FPU Register 280 ******************************************************************************/ 281 /** \defgroup CMSIS_core_register Defines and Type Definitions 282 \brief Type definitions and defines for Cortex-M processor based devices. 283 */ 284 285 /** \ingroup CMSIS_core_register 286 \defgroup CMSIS_CORE Status and Control Registers 287 \brief Core Register type definitions. 288 @{ 289 */ 290 291 /** \brief Union type to access the Application Program Status Register (APSR). 292 */ 293 typedef union 294 { 295 struct 296 { 297 #if (__CORTEX_M != 0x07) 298 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ 299 #else 300 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 301 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 302 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 303 #endif 304 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 305 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 306 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 307 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 308 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 309 } b; /*!< Structure used for bit access */ 310 uint32_t w; /*!< Type used for word access */ 311 } APSR_Type; 312 313 314 /** \brief Union type to access the Interrupt Program Status Register (IPSR). 315 */ 316 typedef union 317 { 318 struct 319 { 320 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 321 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 322 } b; /*!< Structure used for bit access */ 323 uint32_t w; /*!< Type used for word access */ 324 } IPSR_Type; 325 326 327 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 328 */ 329 typedef union 330 { 331 struct 332 { 333 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 334 #if (__CORTEX_M != 0x07) 335 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 336 #else 337 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ 338 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 339 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 340 #endif 341 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 342 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ 343 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 344 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 345 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 346 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 347 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 348 } b; /*!< Structure used for bit access */ 349 uint32_t w; /*!< Type used for word access */ 350 } xPSR_Type; 351 352 353 /** \brief Union type to access the Control Registers (CONTROL). 354 */ 355 typedef union 356 { 357 struct 358 { 359 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 360 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 361 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 362 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 363 } b; /*!< Structure used for bit access */ 364 uint32_t w; /*!< Type used for word access */ 365 } CONTROL_Type; 366 367 /*@} end of group CMSIS_CORE */ 368 369 370 /** \ingroup CMSIS_core_register 371 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 372 \brief Type definitions for the NVIC Registers 373 @{ 374 */ 375 376 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 377 */ 378 typedef struct 379 { 380 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 381 uint32_t RESERVED0[24]; 382 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 383 uint32_t RSERVED1[24]; 384 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 385 uint32_t RESERVED2[24]; 386 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 387 uint32_t RESERVED3[24]; 388 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 389 uint32_t RESERVED4[56]; 390 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ 391 uint32_t RESERVED5[644]; 392 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 393 } NVIC_Type; 394 395 /* Software Triggered Interrupt Register Definitions */ 396 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ 397 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ 398 399 /*@} end of group CMSIS_NVIC */ 400 401 402 /** \ingroup CMSIS_core_register 403 \defgroup CMSIS_SCB System Control Block (SCB) 404 \brief Type definitions for the System Control Block Registers 405 @{ 406 */ 407 408 /** \brief Structure type to access the System Control Block (SCB). 409 */ 410 typedef struct 411 { 412 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 413 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 414 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 415 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 416 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 417 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 418 __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ 419 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 420 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ 421 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 422 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 423 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ 424 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 425 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ 426 __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 427 __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 428 __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 429 __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 430 __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 431 uint32_t RESERVED0[1]; 432 __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ 433 __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ 434 __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ 435 __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ 436 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ 437 uint32_t RESERVED3[93]; 438 __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ 439 uint32_t RESERVED4[15]; 440 __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ 441 __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ 442 __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ 443 uint32_t RESERVED5[1]; 444 __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ 445 uint32_t RESERVED6[1]; 446 __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ 447 __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ 448 __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ 449 __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ 450 __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ 451 __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ 452 __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ 453 __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ 454 uint32_t RESERVED7[6]; 455 __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ 456 __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ 457 __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ 458 __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ 459 __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ 460 uint32_t RESERVED8[1]; 461 __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ 462 } SCB_Type; 463 464 /* SCB CPUID Register Definitions */ 465 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ 466 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 467 468 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ 469 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 470 471 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ 472 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 473 474 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ 475 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 476 477 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ 478 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ 479 480 /* SCB Interrupt Control State Register Definitions */ 481 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ 482 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 483 484 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ 485 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 486 487 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ 488 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 489 490 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ 491 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 492 493 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ 494 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 495 496 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ 497 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 498 499 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ 500 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 501 502 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ 503 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 504 505 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ 506 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 507 508 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ 509 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ 510 511 /* SCB Vector Table Offset Register Definitions */ 512 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ 513 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 514 515 /* SCB Application Interrupt and Reset Control Register Definitions */ 516 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ 517 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 518 519 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ 520 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 521 522 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ 523 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 524 525 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ 526 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ 527 528 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ 529 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 530 531 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ 532 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 533 534 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ 535 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ 536 537 /* SCB System Control Register Definitions */ 538 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ 539 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 540 541 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ 542 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 543 544 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ 545 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 546 547 /* SCB Configuration Control Register Definitions */ 548 #define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */ 549 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ 550 551 #define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */ 552 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ 553 554 #define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */ 555 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ 556 557 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ 558 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 559 560 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ 561 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 562 563 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ 564 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 565 566 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ 567 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 568 569 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ 570 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 571 572 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ 573 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ 574 575 /* SCB System Handler Control and State Register Definitions */ 576 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ 577 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ 578 579 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ 580 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ 581 582 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ 583 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ 584 585 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ 586 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 587 588 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ 589 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ 590 591 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ 592 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ 593 594 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ 595 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ 596 597 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ 598 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 599 600 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ 601 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 602 603 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ 604 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ 605 606 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ 607 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 608 609 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ 610 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ 611 612 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ 613 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ 614 615 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ 616 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ 617 618 /* SCB Configurable Fault Status Registers Definitions */ 619 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ 620 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ 621 622 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ 623 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ 624 625 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ 626 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ 627 628 /* SCB Hard Fault Status Registers Definitions */ 629 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ 630 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ 631 632 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ 633 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ 634 635 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ 636 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ 637 638 /* SCB Debug Fault Status Register Definitions */ 639 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ 640 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 641 642 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ 643 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 644 645 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ 646 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 647 648 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ 649 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 650 651 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ 652 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ 653 654 /* Cache Level ID register */ 655 #define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */ 656 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ 657 658 #define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */ 659 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */ 660 661 /* Cache Type register */ 662 #define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */ 663 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ 664 665 #define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */ 666 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ 667 668 #define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */ 669 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ 670 671 #define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */ 672 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ 673 674 #define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */ 675 #define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */ 676 677 /* Cache Size ID Register */ 678 #define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */ 679 #define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ 680 681 #define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */ 682 #define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ 683 684 #define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */ 685 #define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ 686 687 #define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */ 688 #define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ 689 690 #define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */ 691 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ 692 693 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */ 694 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ 695 696 #define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */ 697 #define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */ 698 699 /* Cache Size Selection Register */ 700 #define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */ 701 #define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ 702 703 #define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */ 704 #define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */ 705 706 /* SCB Software Triggered Interrupt Register */ 707 #define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */ 708 #define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */ 709 710 /* Instruction Tightly-Coupled Memory Control Register*/ 711 #define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */ 712 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ 713 714 #define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */ 715 #define SCB_ITCMCR_RETEN_Msk (1FFUL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ 716 717 #define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */ 718 #define SCB_ITCMCR_RMW_Msk (1FFUL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ 719 720 #define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */ 721 #define SCB_ITCMCR_EN_Msk (1FFUL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */ 722 723 /* Data Tightly-Coupled Memory Control Registers */ 724 #define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */ 725 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ 726 727 #define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */ 728 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ 729 730 #define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */ 731 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ 732 733 #define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */ 734 #define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */ 735 736 /* AHBP Control Register */ 737 #define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */ 738 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ 739 740 #define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */ 741 #define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */ 742 743 /* L1 Cache Control Register */ 744 #define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */ 745 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ 746 747 #define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */ 748 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ 749 750 #define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */ 751 #define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */ 752 753 /* AHBS control register */ 754 #define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */ 755 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ 756 757 #define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */ 758 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ 759 760 #define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/ 761 #define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */ 762 763 /* Auxiliary Bus Fault Status Register */ 764 #define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/ 765 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ 766 767 #define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/ 768 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ 769 770 #define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/ 771 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ 772 773 #define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/ 774 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ 775 776 #define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/ 777 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ 778 779 #define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/ 780 #define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */ 781 782 /*@} end of group CMSIS_SCB */ 783 784 785 /** \ingroup CMSIS_core_register 786 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 787 \brief Type definitions for the System Control and ID Register not in the SCB 788 @{ 789 */ 790 791 /** \brief Structure type to access the System Control and ID Register not in the SCB. 792 */ 793 typedef struct 794 { 795 uint32_t RESERVED0[1]; 796 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 797 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 798 } SCnSCB_Type; 799 800 /* Interrupt Controller Type Register Definitions */ 801 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ 802 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ 803 804 /* Auxiliary Control Register Definitions */ 805 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */ 806 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ 807 808 #define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */ 809 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ 810 811 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */ 812 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ 813 814 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ 815 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ 816 817 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ 818 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ 819 820 /*@} end of group CMSIS_SCnotSCB */ 821 822 823 /** \ingroup CMSIS_core_register 824 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 825 \brief Type definitions for the System Timer Registers. 826 @{ 827 */ 828 829 /** \brief Structure type to access the System Timer (SysTick). 830 */ 831 typedef struct 832 { 833 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 834 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 835 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 836 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 837 } SysTick_Type; 838 839 /* SysTick Control / Status Register Definitions */ 840 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ 841 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 842 843 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ 844 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 845 846 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ 847 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 848 849 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ 850 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ 851 852 /* SysTick Reload Register Definitions */ 853 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ 854 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ 855 856 /* SysTick Current Register Definitions */ 857 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ 858 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ 859 860 /* SysTick Calibration Register Definitions */ 861 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ 862 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 863 864 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ 865 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 866 867 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ 868 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ 869 870 /*@} end of group CMSIS_SysTick */ 871 872 873 /** \ingroup CMSIS_core_register 874 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 875 \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 876 @{ 877 */ 878 879 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 880 */ 881 typedef struct 882 { 883 __O union 884 { 885 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 886 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 887 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 888 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 889 uint32_t RESERVED0[864]; 890 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 891 uint32_t RESERVED1[15]; 892 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 893 uint32_t RESERVED2[15]; 894 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 895 uint32_t RESERVED3[29]; 896 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ 897 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ 898 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ 899 uint32_t RESERVED4[43]; 900 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 901 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 902 uint32_t RESERVED5[6]; 903 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ 904 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ 905 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ 906 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ 907 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ 908 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ 909 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ 910 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ 911 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ 912 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ 913 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ 914 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ 915 } ITM_Type; 916 917 /* ITM Trace Privilege Register Definitions */ 918 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ 919 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ 920 921 /* ITM Trace Control Register Definitions */ 922 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ 923 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ 924 925 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ 926 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ 927 928 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ 929 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ 930 931 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ 932 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ 933 934 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ 935 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ 936 937 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ 938 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ 939 940 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ 941 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ 942 943 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ 944 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ 945 946 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ 947 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ 948 949 /* ITM Integration Write Register Definitions */ 950 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ 951 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ 952 953 /* ITM Integration Read Register Definitions */ 954 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ 955 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ 956 957 /* ITM Integration Mode Control Register Definitions */ 958 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ 959 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ 960 961 /* ITM Lock Status Register Definitions */ 962 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ 963 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ 964 965 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ 966 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ 967 968 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ 969 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ 970 971 /*@}*/ /* end of group CMSIS_ITM */ 972 973 974 /** \ingroup CMSIS_core_register 975 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 976 \brief Type definitions for the Data Watchpoint and Trace (DWT) 977 @{ 978 */ 979 980 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 981 */ 982 typedef struct 983 { 984 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 985 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 986 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 987 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ 988 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 989 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 990 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ 991 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 992 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 993 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ 994 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 995 uint32_t RESERVED0[1]; 996 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 997 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ 998 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 999 uint32_t RESERVED1[1]; 1000 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 1001 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ 1002 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 1003 uint32_t RESERVED2[1]; 1004 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 1005 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ 1006 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 1007 uint32_t RESERVED3[981]; 1008 __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ 1009 __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ 1010 } DWT_Type; 1011 1012 /* DWT Control Register Definitions */ 1013 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ 1014 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 1015 1016 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ 1017 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 1018 1019 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ 1020 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 1021 1022 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ 1023 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 1024 1025 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ 1026 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 1027 1028 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ 1029 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ 1030 1031 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ 1032 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ 1033 1034 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ 1035 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ 1036 1037 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ 1038 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ 1039 1040 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ 1041 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ 1042 1043 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ 1044 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ 1045 1046 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ 1047 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ 1048 1049 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ 1050 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ 1051 1052 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ 1053 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ 1054 1055 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ 1056 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ 1057 1058 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ 1059 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ 1060 1061 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ 1062 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ 1063 1064 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ 1065 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ 1066 1067 /* DWT CPI Count Register Definitions */ 1068 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ 1069 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ 1070 1071 /* DWT Exception Overhead Count Register Definitions */ 1072 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ 1073 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ 1074 1075 /* DWT Sleep Count Register Definitions */ 1076 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ 1077 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ 1078 1079 /* DWT LSU Count Register Definitions */ 1080 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ 1081 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ 1082 1083 /* DWT Folded-instruction Count Register Definitions */ 1084 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ 1085 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ 1086 1087 /* DWT Comparator Mask Register Definitions */ 1088 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ 1089 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ 1090 1091 /* DWT Comparator Function Register Definitions */ 1092 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ 1093 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 1094 1095 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ 1096 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ 1097 1098 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ 1099 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ 1100 1101 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ 1102 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 1103 1104 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ 1105 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ 1106 1107 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ 1108 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ 1109 1110 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ 1111 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ 1112 1113 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ 1114 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ 1115 1116 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ 1117 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ 1118 1119 /*@}*/ /* end of group CMSIS_DWT */ 1120 1121 1122 /** \ingroup CMSIS_core_register 1123 \defgroup CMSIS_TPI Trace Port Interface (TPI) 1124 \brief Type definitions for the Trace Port Interface (TPI) 1125 @{ 1126 */ 1127 1128 /** \brief Structure type to access the Trace Port Interface Register (TPI). 1129 */ 1130 typedef struct 1131 { 1132 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ 1133 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ 1134 uint32_t RESERVED0[2]; 1135 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 1136 uint32_t RESERVED1[55]; 1137 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 1138 uint32_t RESERVED2[131]; 1139 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 1140 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 1141 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ 1142 uint32_t RESERVED3[759]; 1143 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ 1144 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 1145 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 1146 uint32_t RESERVED4[1]; 1147 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 1148 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ 1149 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 1150 uint32_t RESERVED5[39]; 1151 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 1152 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 1153 uint32_t RESERVED7[8]; 1154 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 1155 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 1156 } TPI_Type; 1157 1158 /* TPI Asynchronous Clock Prescaler Register Definitions */ 1159 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ 1160 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ 1161 1162 /* TPI Selected Pin Protocol Register Definitions */ 1163 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ 1164 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ 1165 1166 /* TPI Formatter and Flush Status Register Definitions */ 1167 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ 1168 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 1169 1170 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ 1171 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 1172 1173 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ 1174 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 1175 1176 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ 1177 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ 1178 1179 /* TPI Formatter and Flush Control Register Definitions */ 1180 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ 1181 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 1182 1183 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ 1184 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 1185 1186 /* TPI TRIGGER Register Definitions */ 1187 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ 1188 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ 1189 1190 /* TPI Integration ETM Data Register Definitions (FIFO0) */ 1191 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ 1192 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ 1193 1194 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ 1195 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ 1196 1197 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ 1198 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ 1199 1200 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ 1201 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ 1202 1203 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ 1204 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ 1205 1206 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ 1207 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ 1208 1209 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ 1210 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ 1211 1212 /* TPI ITATBCTR2 Register Definitions */ 1213 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ 1214 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ 1215 1216 /* TPI Integration ITM Data Register Definitions (FIFO1) */ 1217 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ 1218 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ 1219 1220 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ 1221 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ 1222 1223 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ 1224 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ 1225 1226 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ 1227 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ 1228 1229 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ 1230 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ 1231 1232 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ 1233 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ 1234 1235 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ 1236 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ 1237 1238 /* TPI ITATBCTR0 Register Definitions */ 1239 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ 1240 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ 1241 1242 /* TPI Integration Mode Control Register Definitions */ 1243 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ 1244 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ 1245 1246 /* TPI DEVID Register Definitions */ 1247 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ 1248 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 1249 1250 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ 1251 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 1252 1253 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ 1254 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 1255 1256 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ 1257 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ 1258 1259 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ 1260 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ 1261 1262 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ 1263 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ 1264 1265 /* TPI DEVTYPE Register Definitions */ 1266 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ 1267 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ 1268 1269 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ 1270 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 1271 1272 /*@}*/ /* end of group CMSIS_TPI */ 1273 1274 1275 #if (__MPU_PRESENT == 1) 1276 /** \ingroup CMSIS_core_register 1277 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 1278 \brief Type definitions for the Memory Protection Unit (MPU) 1279 @{ 1280 */ 1281 1282 /** \brief Structure type to access the Memory Protection Unit (MPU). 1283 */ 1284 typedef struct 1285 { 1286 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 1287 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 1288 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 1289 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 1290 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 1291 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ 1292 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ 1293 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ 1294 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ 1295 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ 1296 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ 1297 } MPU_Type; 1298 1299 /* MPU Type Register */ 1300 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ 1301 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 1302 1303 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ 1304 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 1305 1306 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ 1307 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ 1308 1309 /* MPU Control Register */ 1310 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ 1311 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 1312 1313 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ 1314 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 1315 1316 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ 1317 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ 1318 1319 /* MPU Region Number Register */ 1320 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ 1321 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ 1322 1323 /* MPU Region Base Address Register */ 1324 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ 1325 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 1326 1327 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ 1328 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 1329 1330 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ 1331 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ 1332 1333 /* MPU Region Attribute and Size Register */ 1334 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ 1335 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 1336 1337 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ 1338 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 1339 1340 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ 1341 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 1342 1343 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ 1344 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 1345 1346 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ 1347 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 1348 1349 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ 1350 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 1351 1352 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ 1353 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 1354 1355 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ 1356 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 1357 1358 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ 1359 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 1360 1361 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ 1362 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ 1363 1364 /*@} end of group CMSIS_MPU */ 1365 #endif 1366 1367 1368 #if (__FPU_PRESENT == 1) 1369 /** \ingroup CMSIS_core_register 1370 \defgroup CMSIS_FPU Floating Point Unit (FPU) 1371 \brief Type definitions for the Floating Point Unit (FPU) 1372 @{ 1373 */ 1374 1375 /** \brief Structure type to access the Floating Point Unit (FPU). 1376 */ 1377 typedef struct 1378 { 1379 uint32_t RESERVED0[1]; 1380 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ 1381 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ 1382 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ 1383 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ 1384 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ 1385 __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ 1386 } FPU_Type; 1387 1388 /* Floating-Point Context Control Register */ 1389 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ 1390 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ 1391 1392 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ 1393 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ 1394 1395 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ 1396 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ 1397 1398 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ 1399 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ 1400 1401 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ 1402 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ 1403 1404 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ 1405 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ 1406 1407 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ 1408 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ 1409 1410 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ 1411 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ 1412 1413 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ 1414 #define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ 1415 1416 /* Floating-Point Context Address Register */ 1417 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ 1418 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ 1419 1420 /* Floating-Point Default Status Control Register */ 1421 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ 1422 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ 1423 1424 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ 1425 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ 1426 1427 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ 1428 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ 1429 1430 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ 1431 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ 1432 1433 /* Media and FP Feature Register 0 */ 1434 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ 1435 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ 1436 1437 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ 1438 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ 1439 1440 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ 1441 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ 1442 1443 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ 1444 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ 1445 1446 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ 1447 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ 1448 1449 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ 1450 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ 1451 1452 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ 1453 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ 1454 1455 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ 1456 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ 1457 1458 /* Media and FP Feature Register 1 */ 1459 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ 1460 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ 1461 1462 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ 1463 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ 1464 1465 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ 1466 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ 1467 1468 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ 1469 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ 1470 1471 /* Media and FP Feature Register 2 */ 1472 1473 /*@} end of group CMSIS_FPU */ 1474 #endif 1475 1476 1477 /** \ingroup CMSIS_core_register 1478 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 1479 \brief Type definitions for the Core Debug Registers 1480 @{ 1481 */ 1482 1483 /** \brief Structure type to access the Core Debug Register (CoreDebug). 1484 */ 1485 typedef struct 1486 { 1487 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 1488 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 1489 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 1490 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 1491 } CoreDebug_Type; 1492 1493 /* Debug Halting Control and Status Register */ 1494 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ 1495 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 1496 1497 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ 1498 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 1499 1500 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 1501 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 1502 1503 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ 1504 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 1505 1506 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ 1507 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 1508 1509 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ 1510 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 1511 1512 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ 1513 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 1514 1515 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ 1516 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ 1517 1518 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ 1519 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 1520 1521 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ 1522 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 1523 1524 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ 1525 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 1526 1527 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 1528 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 1529 1530 /* Debug Core Register Selector Register */ 1531 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ 1532 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 1533 1534 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ 1535 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ 1536 1537 /* Debug Exception and Monitor Control Register */ 1538 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ 1539 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ 1540 1541 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ 1542 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ 1543 1544 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ 1545 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ 1546 1547 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ 1548 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ 1549 1550 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ 1551 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ 1552 1553 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ 1554 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 1555 1556 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ 1557 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ 1558 1559 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ 1560 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ 1561 1562 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ 1563 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ 1564 1565 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ 1566 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ 1567 1568 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ 1569 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ 1570 1571 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ 1572 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ 1573 1574 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ 1575 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 1576 1577 /*@} end of group CMSIS_CoreDebug */ 1578 1579 1580 /** \ingroup CMSIS_core_register 1581 \defgroup CMSIS_core_base Core Definitions 1582 \brief Definitions for base addresses, unions, and structures. 1583 @{ 1584 */ 1585 1586 /* Memory mapping of Cortex-M4 Hardware */ 1587 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 1588 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 1589 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 1590 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 1591 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 1592 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 1593 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 1594 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 1595 1596 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 1597 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 1598 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 1599 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 1600 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ 1601 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 1602 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 1603 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ 1604 1605 #if (__MPU_PRESENT == 1) 1606 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 1607 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 1608 #endif 1609 1610 #if (__FPU_PRESENT == 1) 1611 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ 1612 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ 1613 #endif 1614 1615 /*@} */ 1616 1617 1618 1619 /******************************************************************************* 1620 * Hardware Abstraction Layer 1621 Core Function Interface contains: 1622 - Core NVIC Functions 1623 - Core SysTick Functions 1624 - Core Debug Functions 1625 - Core Register Access Functions 1626 ******************************************************************************/ 1627 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 1628 */ 1629 1630 1631 1632 /* ########################## NVIC functions #################################### */ 1633 /** \ingroup CMSIS_Core_FunctionInterface 1634 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 1635 \brief Functions that manage interrupts and exceptions via the NVIC. 1636 @{ 1637 */ 1638 1639 /** \brief Set Priority Grouping 1640 1641 The function sets the priority grouping field using the required unlock sequence. 1642 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 1643 Only values from 0..7 are used. 1644 In case of a conflict between priority grouping and available 1645 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 1646 1647 \param [in] PriorityGroup Priority grouping field. 1648 */ 1649 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 1650 { 1651 uint32_t reg_value; 1652 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ 1653 1654 reg_value = SCB->AIRCR; /* read old register configuration */ 1655 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ 1656 reg_value = (reg_value | 1657 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | 1658 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ 1659 SCB->AIRCR = reg_value; 1660 } 1661 1662 1663 /** \brief Get Priority Grouping 1664 1665 The function reads the priority grouping field from the NVIC Interrupt Controller. 1666 1667 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 1668 */ 1669 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) 1670 { 1671 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ 1672 } 1673 1674 1675 /** \brief Enable External Interrupt 1676 1677 The function enables a device-specific interrupt in the NVIC interrupt controller. 1678 1679 \param [in] IRQn External interrupt number. Value cannot be negative. 1680 */ 1681 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 1682 { 1683 /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ 1684 NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ 1685 } 1686 1687 1688 /** \brief Disable External Interrupt 1689 1690 The function disables a device-specific interrupt in the NVIC interrupt controller. 1691 1692 \param [in] IRQn External interrupt number. Value cannot be negative. 1693 */ 1694 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 1695 { 1696 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ 1697 } 1698 1699 1700 /** \brief Get Pending Interrupt 1701 1702 The function reads the pending register in the NVIC and returns the pending bit 1703 for the specified interrupt. 1704 1705 \param [in] IRQn Interrupt number. 1706 1707 \return 0 Interrupt status is not pending. 1708 \return 1 Interrupt status is pending. 1709 */ 1710 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 1711 { 1712 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ 1713 } 1714 1715 1716 /** \brief Set Pending Interrupt 1717 1718 The function sets the pending bit of an external interrupt. 1719 1720 \param [in] IRQn Interrupt number. Value cannot be negative. 1721 */ 1722 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 1723 { 1724 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ 1725 } 1726 1727 1728 /** \brief Clear Pending Interrupt 1729 1730 The function clears the pending bit of an external interrupt. 1731 1732 \param [in] IRQn External interrupt number. Value cannot be negative. 1733 */ 1734 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 1735 { 1736 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ 1737 } 1738 1739 1740 /** \brief Get Active Interrupt 1741 1742 The function reads the active register in NVIC and returns the active bit. 1743 1744 \param [in] IRQn Interrupt number. 1745 1746 \return 0 Interrupt status is not active. 1747 \return 1 Interrupt status is active. 1748 */ 1749 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) 1750 { 1751 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ 1752 } 1753 1754 1755 /** \brief Set Interrupt Priority 1756 1757 The function sets the priority of an interrupt. 1758 1759 \note The priority cannot be set for every core interrupt. 1760 1761 \param [in] IRQn Interrupt number. 1762 \param [in] priority Priority to set. 1763 */ 1764 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 1765 { 1766 if(IRQn < 0) { 1767 SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ 1768 else { 1769 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ 1770 } 1771 1772 1773 /** \brief Get Interrupt Priority 1774 1775 The function reads the priority of an interrupt. The interrupt 1776 number can be positive to specify an external (device specific) 1777 interrupt, or negative to specify an internal (core) interrupt. 1778 1779 1780 \param [in] IRQn Interrupt number. 1781 \return Interrupt Priority. Value is aligned automatically to the implemented 1782 priority bits of the microcontroller. 1783 */ 1784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) 1785 { 1786 1787 if(IRQn < 0) { 1788 return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ 1789 else { 1790 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ 1791 } 1792 1793 1794 /** \brief Encode Priority 1795 1796 The function encodes the priority for an interrupt with the given priority group, 1797 preemptive priority value, and subpriority value. 1798 In case of a conflict between priority grouping and available 1799 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 1800 1801 \param [in] PriorityGroup Used priority group. 1802 \param [in] PreemptPriority Preemptive priority value (starting from 0). 1803 \param [in] SubPriority Subpriority value (starting from 0). 1804 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 1805 */ 1806 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 1807 { 1808 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ 1809 uint32_t PreemptPriorityBits; 1810 uint32_t SubPriorityBits; 1811 1812 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; 1813 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; 1814 1815 return ( 1816 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | 1817 ((SubPriority & ((1 << (SubPriorityBits )) - 1))) 1818 ); 1819 } 1820 1821 1822 /** \brief Decode Priority 1823 1824 The function decodes an interrupt priority value with a given priority group to 1825 preemptive priority value and subpriority value. 1826 In case of a conflict between priority grouping and available 1827 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 1828 1829 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 1830 \param [in] PriorityGroup Used priority group. 1831 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 1832 \param [out] pSubPriority Subpriority value (starting from 0). 1833 */ 1834 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) 1835 { 1836 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ 1837 uint32_t PreemptPriorityBits; 1838 uint32_t SubPriorityBits; 1839 1840 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; 1841 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; 1842 1843 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); 1844 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); 1845 } 1846 1847 1848 /** \brief System Reset 1849 1850 The function initiates a system reset request to reset the MCU. 1851 */ 1852 __STATIC_INLINE void NVIC_SystemReset(void) 1853 { 1854 __DSB(); /* Ensure all outstanding memory accesses included 1855 buffered write are completed before reset */ 1856 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | 1857 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 1858 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ 1859 __DSB(); /* Ensure completion of memory access */ 1860 while(1); /* wait until reset */ 1861 } 1862 1863 /*@} end of CMSIS_Core_NVICFunctions */ 1864 1865 1866 /* ########################## Cache functions #################################### */ 1867 /** \ingroup CMSIS_Core_FunctionInterface 1868 \defgroup CMSIS_Core_CacheFunctions Cache Functions 1869 \brief Functions that configure Instruction and Data cache. 1870 @{ 1871 */ 1872 1873 /* Cache Size ID Register Macros */ 1874 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) 1875 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) 1876 #define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos ) 1877 1878 1879 /** \brief Enable I-Cache 1880 1881 The function turns on I-Cache 1882 */ 1883 __STATIC_INLINE void SCB_EnableICache(void) 1884 { 1885 #if (__ICACHE_PRESENT == 1) 1886 __DSB(); 1887 __ISB(); 1888 SCB->ICIALLU = 0; // invalidate I-Cache 1889 SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache 1890 __DSB(); 1891 __ISB(); 1892 #endif 1893 } 1894 1895 1896 /** \brief Disable I-Cache 1897 1898 The function turns off I-Cache 1899 */ 1900 __STATIC_INLINE void SCB_DisableICache(void) 1901 { 1902 #if (__ICACHE_PRESENT == 1) 1903 __DSB(); 1904 __ISB(); 1905 SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache 1906 SCB->ICIALLU = 0; // invalidate I-Cache 1907 __DSB(); 1908 __ISB(); 1909 #endif 1910 } 1911 1912 1913 /** \brief Invalidate I-Cache 1914 1915 The function invalidates I-Cache 1916 */ 1917 __STATIC_INLINE void SCB_InvalidateICache(void) 1918 { 1919 #if (__ICACHE_PRESENT == 1) 1920 __DSB(); 1921 __ISB(); 1922 SCB->ICIALLU = 0; 1923 __DSB(); 1924 __ISB(); 1925 #endif 1926 } 1927 1928 1929 /** \brief Enable D-Cache 1930 1931 The function turns on D-Cache 1932 */ 1933 __STATIC_INLINE void SCB_EnableDCache(void) 1934 { 1935 #if (__DCACHE_PRESENT == 1) 1936 uint32_t ccsidr, sshift, wshift, sw; 1937 uint32_t sets, ways; 1938 1939 ccsidr = SCB->CCSIDR; 1940 sets = CCSIDR_SETS(ccsidr); 1941 sshift = CCSIDR_LSSHIFT(ccsidr) + 4; 1942 ways = CCSIDR_WAYS(ccsidr); 1943 wshift = __CLZ(ways) & 0x1f; 1944 1945 __DSB(); 1946 1947 do { // invalidate D-Cache 1948 int32_t tmpways = ways; 1949 do { 1950 sw = ((tmpways << wshift) | (sets << sshift)); 1951 SCB->DCISW = sw; 1952 } while(tmpways--); 1953 } while(sets--); 1954 __DSB(); 1955 1956 SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache 1957 1958 __DSB(); 1959 __ISB(); 1960 #endif 1961 } 1962 1963 1964 /** \brief Disable D-Cache 1965 1966 The function turns off D-Cache 1967 */ 1968 __STATIC_INLINE void SCB_DisableDCache(void) 1969 { 1970 #if (__DCACHE_PRESENT == 1) 1971 uint32_t ccsidr, sshift, wshift, sw; 1972 uint32_t sets, ways; 1973 1974 ccsidr = SCB->CCSIDR; 1975 sets = CCSIDR_SETS(ccsidr); 1976 sshift = CCSIDR_LSSHIFT(ccsidr) + 4; 1977 ways = CCSIDR_WAYS(ccsidr); 1978 wshift = __CLZ(ways) & 0x1f; 1979 1980 __DSB(); 1981 1982 SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache 1983 1984 do { // clean & invalidate D-Cache 1985 int32_t tmpways = ways; 1986 do { 1987 sw = ((tmpways << wshift) | (sets << sshift)); 1988 SCB->DCCISW = sw; 1989 } while(tmpways--); 1990 } while(sets--); 1991 1992 1993 __DSB(); 1994 __ISB(); 1995 #endif 1996 } 1997 1998 1999 /** \brief Invalidate D-Cache 2000 2001 The function invalidates D-Cache 2002 */ 2003 __STATIC_INLINE void SCB_InvalidateDCache(void) 2004 { 2005 #if (__DCACHE_PRESENT == 1) 2006 uint32_t ccsidr, sshift, wshift, sw; 2007 uint32_t sets, ways; 2008 2009 ccsidr = SCB->CCSIDR; 2010 sets = CCSIDR_SETS(ccsidr); 2011 sshift = CCSIDR_LSSHIFT(ccsidr) + 4; 2012 ways = CCSIDR_WAYS(ccsidr); 2013 wshift = __CLZ(ways) & 0x1f; 2014 2015 __DSB(); 2016 2017 do { // invalidate D-Cache 2018 int32_t tmpways = ways; 2019 do { 2020 sw = ((tmpways << wshift) | (sets << sshift)); 2021 SCB->DCISW = sw; 2022 } while(tmpways--); 2023 } while(sets--); 2024 2025 __DSB(); 2026 __ISB(); 2027 #endif 2028 } 2029 2030 2031 /** \brief Clean D-Cache 2032 2033 The function cleans D-Cache 2034 */ 2035 __STATIC_INLINE void SCB_CleanDCache(void) 2036 { 2037 #if (__DCACHE_PRESENT == 1) 2038 uint32_t ccsidr, sshift, wshift, sw; 2039 uint32_t sets, ways; 2040 2041 ccsidr = SCB->CCSIDR; 2042 sets = CCSIDR_SETS(ccsidr); 2043 sshift = CCSIDR_LSSHIFT(ccsidr) + 4; 2044 ways = CCSIDR_WAYS(ccsidr); 2045 wshift = __CLZ(ways) & 0x1f; 2046 2047 __DSB(); 2048 2049 do { // clean D-Cache 2050 int32_t tmpways = ways; 2051 do { 2052 sw = ((tmpways << wshift) | (sets << sshift)); 2053 SCB->DCCSW = sw; 2054 } while(tmpways--); 2055 } while(sets--); 2056 2057 __DSB(); 2058 __ISB(); 2059 #endif 2060 } 2061 2062 2063 /** \brief Clean & Invalidate D-Cache 2064 2065 The function cleans and Invalidates D-Cache 2066 */ 2067 __STATIC_INLINE void SCB_CleanInvalidateDCache(void) 2068 { 2069 #if (__DCACHE_PRESENT == 1) 2070 uint32_t ccsidr, sshift, wshift, sw; 2071 uint32_t sets, ways; 2072 2073 ccsidr = SCB->CCSIDR; 2074 sets = CCSIDR_SETS(ccsidr); 2075 sshift = CCSIDR_LSSHIFT(ccsidr) + 4; 2076 ways = CCSIDR_WAYS(ccsidr); 2077 wshift = __CLZ(ways) & 0x1f; 2078 2079 __DSB(); 2080 2081 do { // clean & invalidate D-Cache 2082 int32_t tmpways = ways; 2083 do { 2084 sw = ((tmpways << wshift) | (sets << sshift)); 2085 SCB->DCCISW = sw; 2086 } while(tmpways--); 2087 } while(sets--); 2088 2089 __DSB(); 2090 __ISB(); 2091 #endif 2092 } 2093 2094 2095 /*@} end of CMSIS_Core_CacheFunctions */ 2096 2097 2098 2099 /* ################################## SysTick function ############################################ */ 2100 /** \ingroup CMSIS_Core_FunctionInterface 2101 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 2102 \brief Functions that configure the System. 2103 @{ 2104 */ 2105 2106 #if (__Vendor_SysTickConfig == 0) 2107 2108 /** \brief System Tick Configuration 2109 2110 The function initializes the System Timer and its interrupt, and starts the System Tick Timer. 2111 Counter is in free running mode to generate periodic interrupts. 2112 2113 \param [in] ticks Number of ticks between two interrupts. 2114 2115 \return 0 Function succeeded. 2116 \return 1 Function failed. 2117 2118 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 2119 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 2120 must contain a vendor-specific implementation of this function. 2121 2122 */ 2123 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 2124 { 2125 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ 2126 2127 SysTick->LOAD = ticks - 1; /* set reload register */ 2128 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ 2129 SysTick->VAL = 0; /* Load the SysTick Counter Value */ 2130 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 2131 SysTick_CTRL_TICKINT_Msk | 2132 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 2133 return (0); /* Function successful */ 2134 } 2135 2136 #endif 2137 2138 /*@} end of CMSIS_Core_SysTickFunctions */ 2139 2140 2141 2142 /* ##################################### Debug In/Output function ########################################### */ 2143 /** \ingroup CMSIS_Core_FunctionInterface 2144 \defgroup CMSIS_core_DebugFunctions ITM Functions 2145 \brief Functions that access the ITM debug interface. 2146 @{ 2147 */ 2148 2149 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ 2150 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ 2151 2152 2153 /** \brief ITM Send Character 2154 2155 The function transmits a character via the ITM channel 0, and 2156 \li Just returns when no debugger is connected that has booked the output. 2157 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. 2158 2159 \param [in] ch Character to transmit. 2160 2161 \returns Character to transmit. 2162 */ 2163 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) 2164 { 2165 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ 2166 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ 2167 { 2168 while (ITM->PORT[0].u32 == 0); 2169 ITM->PORT[0].u8 = (uint8_t) ch; 2170 } 2171 return (ch); 2172 } 2173 2174 2175 /** \brief ITM Receive Character 2176 2177 The function inputs a character via the external variable \ref ITM_RxBuffer. 2178 2179 \return Received character. 2180 \return -1 No character pending. 2181 */ 2182 __STATIC_INLINE int32_t ITM_ReceiveChar (void) { 2183 int32_t ch = -1; /* no character available */ 2184 2185 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { 2186 ch = ITM_RxBuffer; 2187 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 2188 } 2189 2190 return (ch); 2191 } 2192 2193 2194 /** \brief ITM Check Character 2195 2196 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. 2197 2198 \return 0 No character available. 2199 \return 1 Character available. 2200 */ 2201 __STATIC_INLINE int32_t ITM_CheckChar (void) { 2202 2203 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { 2204 return (0); /* no character available */ 2205 } else { 2206 return (1); /* character available */ 2207 } 2208 } 2209 2210 /*@} end of CMSIS_core_DebugFunctions */ 2211 2212 2213 2214 2215 #ifdef __cplusplus 2216 } 2217 #endif 2218 2219 #endif /* __CORE_CM7_H_DEPENDANT */ 2220 2221 #endif /* __CMSIS_GENERIC */ 2222
