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Searched
refs:SCB
(Results
1 - 14
of
14
) sorted by null
/device/google/contexthub/firmware/os/cpu/cortexm4/
pendsv.c
60
SCB
->ICSR = 1UL << 28;
65
SCB
->ICSR = 1UL << 27;
70
return !!(
SCB
->ICSR & (1UL << 28));
appSupport.c
220
uint32_t hasSvcAct =
SCB
->SHCSR & SCB_SHCSR_SVCALLACT_Msk;
222
SCB
->SHCSR &= ~SCB_SHCSR_SVCALLACT_Msk;
224
SCB
->SHCSR |= hasSvcAct;
cpu.c
88
SCB
->CPACR |= 0x00F00000;
286
cpuPackSrBits(&dbx->sr_hfsr_cfsr_lo, &hi, excRegs[7],
SCB
->HFSR,
SCB
->CFSR);
/device/google/contexthub/firmware/os/platform/stm32/
pwr.c
245
SCB
->SCR &=~ SCB_SCR_SLEEPDEEP_Msk;
248
SCB
->SCR |= SCB_SCR_SLEEPDEEP_Msk;
251
SCB
->SCR |= SCB_SCR_SLEEPDEEP_Msk;
255
SCB
->SCR |= SCB_SCR_SLEEPDEEP_Msk;
259
SCB
->SCR |= SCB_SCR_SLEEPDEEP_Msk;
bl.c
377
SCB
->AIRCR = 0x05FA0004;
487
SCB
->VTOR = (uint32_t)&BL;
497
SCB
->VTOR = appBase;
mpu.c
138
SCB
->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
platform.c
240
SCB
->SCR &=~ SCB_SCR_SLEEPONEXIT_Msk;
/device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
core_cm7.h
275
- Core
SCB
Register
403
\defgroup CMSIS_SCB System Control Block (
SCB
)
408
/** \brief Structure type to access the System Control Block (
SCB
).
464
/*
SCB
CPUID Register Definitions */
465
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!<
SCB
CPUID: IMPLEMENTER Position */
466
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!<
SCB
CPUID: IMPLEMENTER Mask */
468
#define SCB_CPUID_VARIANT_Pos 20 /*!<
SCB
CPUID: VARIANT Position */
469
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!<
SCB
CPUID: VARIANT Mask */
471
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!<
SCB
CPUID: ARCHITECTURE Position */
472
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!<
SCB
CPUID: ARCHITECTURE Mask *
[
all
...]
core_cm0.h
209
- Core
SCB
Register
327
\defgroup CMSIS_SCB System Control Block (
SCB
)
332
/** \brief Structure type to access the System Control Block (
SCB
).
347
/*
SCB
CPUID Register Definitions */
348
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!<
SCB
CPUID: IMPLEMENTER Position */
349
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!<
SCB
CPUID: IMPLEMENTER Mask */
351
#define SCB_CPUID_VARIANT_Pos 20 /*!<
SCB
CPUID: VARIANT Position */
352
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!<
SCB
CPUID: VARIANT Mask */
354
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!<
SCB
CPUID: ARCHITECTURE Position */
355
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!<
SCB
CPUID: ARCHITECTURE Mask *
[
all
...]
core_cm0plus.h
219
- Core
SCB
Register
338
\defgroup CMSIS_SCB System Control Block (
SCB
)
343
/** \brief Structure type to access the System Control Block (
SCB
).
362
/*
SCB
CPUID Register Definitions */
363
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!<
SCB
CPUID: IMPLEMENTER Position */
364
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!<
SCB
CPUID: IMPLEMENTER Mask */
366
#define SCB_CPUID_VARIANT_Pos 20 /*!<
SCB
CPUID: VARIANT Position */
367
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!<
SCB
CPUID: VARIANT Mask */
369
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!<
SCB
CPUID: ARCHITECTURE Position */
370
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!<
SCB
CPUID: ARCHITECTURE Mask *
[
all
...]
core_sc000.h
214
- Core
SCB
Register
333
\defgroup CMSIS_SCB System Control Block (
SCB
)
338
/** \brief Structure type to access the System Control Block (
SCB
).
355
/*
SCB
CPUID Register Definitions */
356
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!<
SCB
CPUID: IMPLEMENTER Position */
357
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!<
SCB
CPUID: IMPLEMENTER Mask */
359
#define SCB_CPUID_VARIANT_Pos 20 /*!<
SCB
CPUID: VARIANT Position */
360
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!<
SCB
CPUID: VARIANT Mask */
362
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!<
SCB
CPUID: ARCHITECTURE Position */
363
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!<
SCB
CPUID: ARCHITECTURE Mask *
[
all
...]
core_cm3.h
214
- Core
SCB
Register
341
\defgroup CMSIS_SCB System Control Block (
SCB
)
346
/** \brief Structure type to access the System Control Block (
SCB
).
373
/*
SCB
CPUID Register Definitions */
374
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!<
SCB
CPUID: IMPLEMENTER Position */
375
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!<
SCB
CPUID: IMPLEMENTER Mask */
377
#define SCB_CPUID_VARIANT_Pos 20 /*!<
SCB
CPUID: VARIANT Position */
378
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!<
SCB
CPUID: VARIANT Mask */
380
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!<
SCB
CPUID: ARCHITECTURE Position */
381
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!<
SCB
CPUID: ARCHITECTURE Mask *
[
all
...]
core_cm4.h
260
- Core
SCB
Register
388
\defgroup CMSIS_SCB System Control Block (
SCB
)
393
/** \brief Structure type to access the System Control Block (
SCB
).
420
/*
SCB
CPUID Register Definitions */
421
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!<
SCB
CPUID: IMPLEMENTER Position */
422
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!<
SCB
CPUID: IMPLEMENTER Mask */
424
#define SCB_CPUID_VARIANT_Pos 20 /*!<
SCB
CPUID: VARIANT Position */
425
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!<
SCB
CPUID: VARIANT Mask */
427
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!<
SCB
CPUID: ARCHITECTURE Position */
428
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!<
SCB
CPUID: ARCHITECTURE Mask *
[
all
...]
core_sc300.h
214
- Core
SCB
Register
341
\defgroup CMSIS_SCB System Control Block (
SCB
)
346
/** \brief Structure type to access the System Control Block (
SCB
).
373
/*
SCB
CPUID Register Definitions */
374
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!<
SCB
CPUID: IMPLEMENTER Position */
375
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!<
SCB
CPUID: IMPLEMENTER Mask */
377
#define SCB_CPUID_VARIANT_Pos 20 /*!<
SCB
CPUID: VARIANT Position */
378
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!<
SCB
CPUID: VARIANT Mask */
380
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!<
SCB
CPUID: ARCHITECTURE Position */
381
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!<
SCB
CPUID: ARCHITECTURE Mask *
[
all
...]
Completed in 3914 milliseconds