1 /**************************************************************************//** 2 * @file core_cm0.h 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File 4 * @version V4.00 5 * @date 22. August 2014 6 * 7 * @note 8 * 9 ******************************************************************************/ 10 /* Copyright (c) 2009 - 2014 ARM LIMITED 11 12 All rights reserved. 13 Redistribution and use in source and binary forms, with or without 14 modification, are permitted provided that the following conditions are met: 15 - Redistributions of source code must retain the above copyright 16 notice, this list of conditions and the following disclaimer. 17 - Redistributions in binary form must reproduce the above copyright 18 notice, this list of conditions and the following disclaimer in the 19 documentation and/or other materials provided with the distribution. 20 - Neither the name of ARM nor the names of its contributors may be used 21 to endorse or promote products derived from this software without 22 specific prior written permission. 23 * 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 POSSIBILITY OF SUCH DAMAGE. 35 ---------------------------------------------------------------------------*/ 36 37 38 #if defined ( __ICCARM__ ) 39 #pragma system_include /* treat file as system include file for MISRA check */ 40 #endif 41 42 #ifndef __CORE_CM0_H_GENERIC 43 #define __CORE_CM0_H_GENERIC 44 45 #ifdef __cplusplus 46 extern "C" { 47 #endif 48 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 50 CMSIS violates the following MISRA-C:2004 rules: 51 52 \li Required Rule 8.5, object/function definition in header file.<br> 53 Function definitions in header files are used to allow 'inlining'. 54 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 56 Unions are used for effective representation of core registers. 57 58 \li Advisory Rule 19.7, Function-like macro defined.<br> 59 Function-like macros are used to allow more efficient code. 60 */ 61 62 63 /******************************************************************************* 64 * CMSIS definitions 65 ******************************************************************************/ 66 /** \ingroup Cortex_M0 67 @{ 68 */ 69 70 /* CMSIS CM0 definitions */ 71 #define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ 72 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ 75 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */ 77 78 79 #if defined ( __CC_ARM ) 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 82 #define __STATIC_INLINE static __inline 83 84 #elif defined ( __GNUC__ ) 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 87 #define __STATIC_INLINE static inline 88 89 #elif defined ( __ICCARM__ ) 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ 92 #define __STATIC_INLINE static inline 93 94 #elif defined ( __TMS470__ ) 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ 96 #define __STATIC_INLINE static inline 97 98 #elif defined ( __TASKING__ ) 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 101 #define __STATIC_INLINE static inline 102 103 #elif defined ( __CSMC__ ) 104 #define __packed 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ 107 #define __STATIC_INLINE static inline 108 109 #endif 110 111 /** __FPU_USED indicates whether an FPU is used or not. 112 This core does not support an FPU at all 113 */ 114 #define __FPU_USED 0 115 116 #if defined ( __CC_ARM ) 117 #if defined __TARGET_FPU_VFP 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 119 #endif 120 121 #elif defined ( __GNUC__ ) 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 124 #endif 125 126 #elif defined ( __ICCARM__ ) 127 #if defined __ARMVFP__ 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 129 #endif 130 131 #elif defined ( __TMS470__ ) 132 #if defined __TI__VFP_SUPPORT____ 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 134 #endif 135 136 #elif defined ( __TASKING__ ) 137 #if defined __FPU_VFP__ 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 139 #endif 140 141 #elif defined ( __CSMC__ ) /* Cosmic */ 142 #if ( __CSMC__ & 0x400) // FPU present for parser 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 144 #endif 145 #endif 146 147 #include <stdint.h> /* standard types definitions */ 148 #include <core_cmInstr.h> /* Core Instruction Access */ 149 #include <core_cmFunc.h> /* Core Function Access */ 150 151 #ifdef __cplusplus 152 } 153 #endif 154 155 #endif /* __CORE_CM0_H_GENERIC */ 156 157 #ifndef __CMSIS_GENERIC 158 159 #ifndef __CORE_CM0_H_DEPENDANT 160 #define __CORE_CM0_H_DEPENDANT 161 162 #ifdef __cplusplus 163 extern "C" { 164 #endif 165 166 /* check device defines and use defaults */ 167 #if defined __CHECK_DEVICE_DEFINES 168 #ifndef __CM0_REV 169 #define __CM0_REV 0x0000 170 #warning "__CM0_REV not defined in device header file; using default!" 171 #endif 172 173 #ifndef __NVIC_PRIO_BITS 174 #define __NVIC_PRIO_BITS 2 175 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 176 #endif 177 178 #ifndef __Vendor_SysTickConfig 179 #define __Vendor_SysTickConfig 0 180 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 181 #endif 182 #endif 183 184 /* IO definitions (access restrictions to peripheral registers) */ 185 /** 186 \defgroup CMSIS_glob_defs CMSIS Global Defines 187 188 <strong>IO Type Qualifiers</strong> are used 189 \li to specify the access to peripheral variables. 190 \li for automatic generation of peripheral register debug information. 191 */ 192 #ifdef __cplusplus 193 #define __I volatile /*!< Defines 'read only' permissions */ 194 #else 195 #define __I volatile const /*!< Defines 'read only' permissions */ 196 #endif 197 #define __O volatile /*!< Defines 'write only' permissions */ 198 #define __IO volatile /*!< Defines 'read / write' permissions */ 199 200 /*@} end of group Cortex_M0 */ 201 202 203 204 /******************************************************************************* 205 * Register Abstraction 206 Core Register contain: 207 - Core Register 208 - Core NVIC Register 209 - Core SCB Register 210 - Core SysTick Register 211 ******************************************************************************/ 212 /** \defgroup CMSIS_core_register Defines and Type Definitions 213 \brief Type definitions and defines for Cortex-M processor based devices. 214 */ 215 216 /** \ingroup CMSIS_core_register 217 \defgroup CMSIS_CORE Status and Control Registers 218 \brief Core Register type definitions. 219 @{ 220 */ 221 222 /** \brief Union type to access the Application Program Status Register (APSR). 223 */ 224 typedef union 225 { 226 struct 227 { 228 #if (__CORTEX_M != 0x04) 229 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ 230 #else 231 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 232 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 233 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 234 #endif 235 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 236 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 237 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 238 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 239 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 240 } b; /*!< Structure used for bit access */ 241 uint32_t w; /*!< Type used for word access */ 242 } APSR_Type; 243 244 245 /** \brief Union type to access the Interrupt Program Status Register (IPSR). 246 */ 247 typedef union 248 { 249 struct 250 { 251 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 252 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 253 } b; /*!< Structure used for bit access */ 254 uint32_t w; /*!< Type used for word access */ 255 } IPSR_Type; 256 257 258 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 259 */ 260 typedef union 261 { 262 struct 263 { 264 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 265 #if (__CORTEX_M != 0x04) 266 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 267 #else 268 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ 269 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 270 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 271 #endif 272 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 273 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ 274 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 275 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 276 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 277 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 278 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 279 } b; /*!< Structure used for bit access */ 280 uint32_t w; /*!< Type used for word access */ 281 } xPSR_Type; 282 283 284 /** \brief Union type to access the Control Registers (CONTROL). 285 */ 286 typedef union 287 { 288 struct 289 { 290 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 291 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 292 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 293 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 294 } b; /*!< Structure used for bit access */ 295 uint32_t w; /*!< Type used for word access */ 296 } CONTROL_Type; 297 298 /*@} end of group CMSIS_CORE */ 299 300 301 /** \ingroup CMSIS_core_register 302 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 303 \brief Type definitions for the NVIC Registers 304 @{ 305 */ 306 307 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 308 */ 309 typedef struct 310 { 311 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 312 uint32_t RESERVED0[31]; 313 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 314 uint32_t RSERVED1[31]; 315 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 316 uint32_t RESERVED2[31]; 317 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 318 uint32_t RESERVED3[31]; 319 uint32_t RESERVED4[64]; 320 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 321 } NVIC_Type; 322 323 /*@} end of group CMSIS_NVIC */ 324 325 326 /** \ingroup CMSIS_core_register 327 \defgroup CMSIS_SCB System Control Block (SCB) 328 \brief Type definitions for the System Control Block Registers 329 @{ 330 */ 331 332 /** \brief Structure type to access the System Control Block (SCB). 333 */ 334 typedef struct 335 { 336 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 337 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 338 uint32_t RESERVED0; 339 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 340 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 341 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 342 uint32_t RESERVED1; 343 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 344 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 345 } SCB_Type; 346 347 /* SCB CPUID Register Definitions */ 348 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ 349 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 350 351 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ 352 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 353 354 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ 355 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 356 357 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ 358 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 359 360 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ 361 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ 362 363 /* SCB Interrupt Control State Register Definitions */ 364 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ 365 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 366 367 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ 368 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 369 370 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ 371 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 372 373 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ 374 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 375 376 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ 377 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 378 379 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ 380 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 381 382 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ 383 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 384 385 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ 386 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 387 388 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ 389 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ 390 391 /* SCB Application Interrupt and Reset Control Register Definitions */ 392 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ 393 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 394 395 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ 396 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 397 398 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ 399 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 400 401 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ 402 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 403 404 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ 405 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 406 407 /* SCB System Control Register Definitions */ 408 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ 409 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 410 411 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ 412 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 413 414 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ 415 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 416 417 /* SCB Configuration Control Register Definitions */ 418 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ 419 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 420 421 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ 422 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 423 424 /* SCB System Handler Control and State Register Definitions */ 425 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ 426 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 427 428 /*@} end of group CMSIS_SCB */ 429 430 431 /** \ingroup CMSIS_core_register 432 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 433 \brief Type definitions for the System Timer Registers. 434 @{ 435 */ 436 437 /** \brief Structure type to access the System Timer (SysTick). 438 */ 439 typedef struct 440 { 441 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 442 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 443 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 444 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 445 } SysTick_Type; 446 447 /* SysTick Control / Status Register Definitions */ 448 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ 449 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 450 451 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ 452 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 453 454 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ 455 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 456 457 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ 458 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ 459 460 /* SysTick Reload Register Definitions */ 461 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ 462 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ 463 464 /* SysTick Current Register Definitions */ 465 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ 466 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ 467 468 /* SysTick Calibration Register Definitions */ 469 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ 470 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 471 472 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ 473 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 474 475 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ 476 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ 477 478 /*@} end of group CMSIS_SysTick */ 479 480 481 /** \ingroup CMSIS_core_register 482 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 483 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) 484 are only accessible over DAP and not via processor. Therefore 485 they are not covered by the Cortex-M0 header file. 486 @{ 487 */ 488 /*@} end of group CMSIS_CoreDebug */ 489 490 491 /** \ingroup CMSIS_core_register 492 \defgroup CMSIS_core_base Core Definitions 493 \brief Definitions for base addresses, unions, and structures. 494 @{ 495 */ 496 497 /* Memory mapping of Cortex-M0 Hardware */ 498 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 499 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 500 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 501 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 502 503 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 504 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 505 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 506 507 508 /*@} */ 509 510 511 512 /******************************************************************************* 513 * Hardware Abstraction Layer 514 Core Function Interface contains: 515 - Core NVIC Functions 516 - Core SysTick Functions 517 - Core Register Access Functions 518 ******************************************************************************/ 519 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 520 */ 521 522 523 524 /* ########################## NVIC functions #################################### */ 525 /** \ingroup CMSIS_Core_FunctionInterface 526 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 527 \brief Functions that manage interrupts and exceptions via the NVIC. 528 @{ 529 */ 530 531 /* Interrupt Priorities are WORD accessible only under ARMv6M */ 532 /* The following MACROS handle generation of the register offset and byte masks */ 533 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) 534 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) 535 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) 536 537 538 /** \brief Enable External Interrupt 539 540 The function enables a device-specific interrupt in the NVIC interrupt controller. 541 542 \param [in] IRQn External interrupt number. Value cannot be negative. 543 */ 544 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 545 { 546 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 547 } 548 549 550 /** \brief Disable External Interrupt 551 552 The function disables a device-specific interrupt in the NVIC interrupt controller. 553 554 \param [in] IRQn External interrupt number. Value cannot be negative. 555 */ 556 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 557 { 558 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 559 } 560 561 562 /** \brief Get Pending Interrupt 563 564 The function reads the pending register in the NVIC and returns the pending bit 565 for the specified interrupt. 566 567 \param [in] IRQn Interrupt number. 568 569 \return 0 Interrupt status is not pending. 570 \return 1 Interrupt status is pending. 571 */ 572 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 573 { 574 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); 575 } 576 577 578 /** \brief Set Pending Interrupt 579 580 The function sets the pending bit of an external interrupt. 581 582 \param [in] IRQn Interrupt number. Value cannot be negative. 583 */ 584 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 585 { 586 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 587 } 588 589 590 /** \brief Clear Pending Interrupt 591 592 The function clears the pending bit of an external interrupt. 593 594 \param [in] IRQn External interrupt number. Value cannot be negative. 595 */ 596 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 597 { 598 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ 599 } 600 601 602 /** \brief Set Interrupt Priority 603 604 The function sets the priority of an interrupt. 605 606 \note The priority cannot be set for every core interrupt. 607 608 \param [in] IRQn Interrupt number. 609 \param [in] priority Priority to set. 610 */ 611 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 612 { 613 if(IRQn < 0) { 614 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 615 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } 616 else { 617 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 618 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } 619 } 620 621 622 /** \brief Get Interrupt Priority 623 624 The function reads the priority of an interrupt. The interrupt 625 number can be positive to specify an external (device specific) 626 interrupt, or negative to specify an internal (core) interrupt. 627 628 629 \param [in] IRQn Interrupt number. 630 \return Interrupt Priority. Value is aligned automatically to the implemented 631 priority bits of the microcontroller. 632 */ 633 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) 634 { 635 636 if(IRQn < 0) { 637 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ 638 else { 639 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ 640 } 641 642 643 /** \brief System Reset 644 645 The function initiates a system reset request to reset the MCU. 646 */ 647 __STATIC_INLINE void NVIC_SystemReset(void) 648 { 649 __DSB(); /* Ensure all outstanding memory accesses included 650 buffered write are completed before reset */ 651 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | 652 SCB_AIRCR_SYSRESETREQ_Msk); 653 __DSB(); /* Ensure completion of memory access */ 654 while(1); /* wait until reset */ 655 } 656 657 /*@} end of CMSIS_Core_NVICFunctions */ 658 659 660 661 /* ################################## SysTick function ############################################ */ 662 /** \ingroup CMSIS_Core_FunctionInterface 663 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 664 \brief Functions that configure the System. 665 @{ 666 */ 667 668 #if (__Vendor_SysTickConfig == 0) 669 670 /** \brief System Tick Configuration 671 672 The function initializes the System Timer and its interrupt, and starts the System Tick Timer. 673 Counter is in free running mode to generate periodic interrupts. 674 675 \param [in] ticks Number of ticks between two interrupts. 676 677 \return 0 Function succeeded. 678 \return 1 Function failed. 679 680 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 681 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 682 must contain a vendor-specific implementation of this function. 683 684 */ 685 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 686 { 687 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ 688 689 SysTick->LOAD = ticks - 1; /* set reload register */ 690 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ 691 SysTick->VAL = 0; /* Load the SysTick Counter Value */ 692 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 693 SysTick_CTRL_TICKINT_Msk | 694 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 695 return (0); /* Function successful */ 696 } 697 698 #endif 699 700 /*@} end of CMSIS_Core_SysTickFunctions */ 701 702 703 704 705 #ifdef __cplusplus 706 } 707 #endif 708 709 #endif /* __CORE_CM0_H_DEPENDANT */ 710 711 #endif /* __CMSIS_GENERIC */ 712
