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Searched
refs:SHCSR
(Results
1 - 9
of
9
) sorted by null
/device/google/contexthub/firmware/os/cpu/cortexm4/
appSupport.c
220
uint32_t hasSvcAct = SCB->
SHCSR
& SCB_SHCSR_SVCALLACT_Msk;
222
SCB->
SHCSR
&= ~SCB_SHCSR_SVCALLACT_Msk;
224
SCB->
SHCSR
|= hasSvcAct;
/device/google/contexthub/firmware/os/platform/stm32/
mpu.c
138
SCB->
SHCSR
|= SCB_SHCSR_MEMFAULTENA_Msk;
/device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
core_cm0.h
344
__IO uint32_t
SHCSR
; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
425
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB
SHCSR
: SVCALLPENDED Position */
426
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB
SHCSR
: SVCALLPENDED Mask */
483
\brief Cortex-M0 Core Debug Registers (DCB registers,
SHCSR
, and DFSR)
[
all
...]
core_cm0plus.h
359
__IO uint32_t
SHCSR
; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
446
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB
SHCSR
: SVCALLPENDED Position */
447
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB
SHCSR
: SVCALLPENDED Mask */
590
\brief Cortex-M0+ Core Debug Registers (DCB registers,
SHCSR
, and DFSR)
[
all
...]
core_sc000.h
350
__IO uint32_t
SHCSR
; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
437
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB
SHCSR
: SVCALLPENDED Position */
438
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB
SHCSR
: SVCALLPENDED Mask */
[
all
...]
core_cm3.h
357
__IO uint32_t
SHCSR
; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
484
#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB
SHCSR
: USGFAULTENA Position */
485
#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB
SHCSR
: USGFAULTENA Mask */
487
#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB
SHCSR
: BUSFAULTENA Position */
488
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB
SHCSR
: BUSFAULTENA Mask */
490
#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB
SHCSR
: MEMFAULTENA Position */
491
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB
SHCSR
: MEMFAULTENA Mask */
493
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB
SHCSR
: SVCALLPENDED Position */
494
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB
SHCSR
: SVCALLPENDED Mask */
496
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB
SHCSR
: BUSFAULTPENDED Position *
[
all
...]
core_cm4.h
404
__IO uint32_t
SHCSR
; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
523
#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB
SHCSR
: USGFAULTENA Position */
524
#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB
SHCSR
: USGFAULTENA Mask */
526
#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB
SHCSR
: BUSFAULTENA Position */
527
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB
SHCSR
: BUSFAULTENA Mask */
529
#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB
SHCSR
: MEMFAULTENA Position */
530
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB
SHCSR
: MEMFAULTENA Mask */
532
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB
SHCSR
: SVCALLPENDED Position */
533
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB
SHCSR
: SVCALLPENDED Mask */
535
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB
SHCSR
: BUSFAULTPENDED Position *
[
all
...]
core_sc300.h
357
__IO uint32_t
SHCSR
; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
479
#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB
SHCSR
: USGFAULTENA Position */
480
#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB
SHCSR
: USGFAULTENA Mask */
482
#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB
SHCSR
: BUSFAULTENA Position */
483
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB
SHCSR
: BUSFAULTENA Mask */
485
#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB
SHCSR
: MEMFAULTENA Position */
486
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB
SHCSR
: MEMFAULTENA Mask */
488
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB
SHCSR
: SVCALLPENDED Position */
489
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB
SHCSR
: SVCALLPENDED Mask */
491
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB
SHCSR
: BUSFAULTPENDED Position *
[
all
...]
core_cm7.h
419
__IO uint32_t
SHCSR
; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
576
#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB
SHCSR
: USGFAULTENA Position */
577
#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB
SHCSR
: USGFAULTENA Mask */
579
#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB
SHCSR
: BUSFAULTENA Position */
580
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB
SHCSR
: BUSFAULTENA Mask */
582
#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB
SHCSR
: MEMFAULTENA Position */
583
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB
SHCSR
: MEMFAULTENA Mask */
585
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB
SHCSR
: SVCALLPENDED Position */
586
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB
SHCSR
: SVCALLPENDED Mask */
588
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB
SHCSR
: BUSFAULTPENDED Position *
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all
...]
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