1 /**************************************************************************//** 2 * @file core_sc000.h 3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File 4 * @version V4.00 5 * @date 22. August 2014 6 * 7 * @note 8 * 9 ******************************************************************************/ 10 /* Copyright (c) 2009 - 2014 ARM LIMITED 11 12 All rights reserved. 13 Redistribution and use in source and binary forms, with or without 14 modification, are permitted provided that the following conditions are met: 15 - Redistributions of source code must retain the above copyright 16 notice, this list of conditions and the following disclaimer. 17 - Redistributions in binary form must reproduce the above copyright 18 notice, this list of conditions and the following disclaimer in the 19 documentation and/or other materials provided with the distribution. 20 - Neither the name of ARM nor the names of its contributors may be used 21 to endorse or promote products derived from this software without 22 specific prior written permission. 23 * 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 POSSIBILITY OF SUCH DAMAGE. 35 ---------------------------------------------------------------------------*/ 36 37 38 #if defined ( __ICCARM__ ) 39 #pragma system_include /* treat file as system include file for MISRA check */ 40 #endif 41 42 #ifndef __CORE_SC000_H_GENERIC 43 #define __CORE_SC000_H_GENERIC 44 45 #ifdef __cplusplus 46 extern "C" { 47 #endif 48 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 50 CMSIS violates the following MISRA-C:2004 rules: 51 52 \li Required Rule 8.5, object/function definition in header file.<br> 53 Function definitions in header files are used to allow 'inlining'. 54 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 56 Unions are used for effective representation of core registers. 57 58 \li Advisory Rule 19.7, Function-like macro defined.<br> 59 Function-like macros are used to allow more efficient code. 60 */ 61 62 63 /******************************************************************************* 64 * CMSIS definitions 65 ******************************************************************************/ 66 /** \ingroup SC000 67 @{ 68 */ 69 70 /* CMSIS SC000 definitions */ 71 #define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ 72 #define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ 73 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ 74 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ 75 76 #define __CORTEX_SC (000) /*!< Cortex secure core */ 77 78 79 #if defined ( __CC_ARM ) 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 82 #define __STATIC_INLINE static __inline 83 84 #elif defined ( __GNUC__ ) 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 87 #define __STATIC_INLINE static inline 88 89 #elif defined ( __ICCARM__ ) 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ 92 #define __STATIC_INLINE static inline 93 94 #elif defined ( __TMS470__ ) 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ 96 #define __STATIC_INLINE static inline 97 98 #elif defined ( __TASKING__ ) 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 101 #define __STATIC_INLINE static inline 102 103 #elif defined ( __CSMC__ ) 104 #define __packed 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ 107 #define __STATIC_INLINE static inline 108 109 #endif 110 111 /** __FPU_USED indicates whether an FPU is used or not. 112 This core does not support an FPU at all 113 */ 114 #define __FPU_USED 0 115 116 #if defined ( __CC_ARM ) 117 #if defined __TARGET_FPU_VFP 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 119 #endif 120 121 #elif defined ( __GNUC__ ) 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 124 #endif 125 126 #elif defined ( __ICCARM__ ) 127 #if defined __ARMVFP__ 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 129 #endif 130 131 #elif defined ( __TMS470__ ) 132 #if defined __TI__VFP_SUPPORT____ 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 134 #endif 135 136 #elif defined ( __TASKING__ ) 137 #if defined __FPU_VFP__ 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 139 #endif 140 141 #elif defined ( __CSMC__ ) /* Cosmic */ 142 #if ( __CSMC__ & 0x400) // FPU present for parser 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 144 #endif 145 #endif 146 147 #include <stdint.h> /* standard types definitions */ 148 #include <core_cmInstr.h> /* Core Instruction Access */ 149 #include <core_cmFunc.h> /* Core Function Access */ 150 151 #ifdef __cplusplus 152 } 153 #endif 154 155 #endif /* __CORE_SC000_H_GENERIC */ 156 157 #ifndef __CMSIS_GENERIC 158 159 #ifndef __CORE_SC000_H_DEPENDANT 160 #define __CORE_SC000_H_DEPENDANT 161 162 #ifdef __cplusplus 163 extern "C" { 164 #endif 165 166 /* check device defines and use defaults */ 167 #if defined __CHECK_DEVICE_DEFINES 168 #ifndef __SC000_REV 169 #define __SC000_REV 0x0000 170 #warning "__SC000_REV not defined in device header file; using default!" 171 #endif 172 173 #ifndef __MPU_PRESENT 174 #define __MPU_PRESENT 0 175 #warning "__MPU_PRESENT not defined in device header file; using default!" 176 #endif 177 178 #ifndef __NVIC_PRIO_BITS 179 #define __NVIC_PRIO_BITS 2 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 181 #endif 182 183 #ifndef __Vendor_SysTickConfig 184 #define __Vendor_SysTickConfig 0 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 186 #endif 187 #endif 188 189 /* IO definitions (access restrictions to peripheral registers) */ 190 /** 191 \defgroup CMSIS_glob_defs CMSIS Global Defines 192 193 <strong>IO Type Qualifiers</strong> are used 194 \li to specify the access to peripheral variables. 195 \li for automatic generation of peripheral register debug information. 196 */ 197 #ifdef __cplusplus 198 #define __I volatile /*!< Defines 'read only' permissions */ 199 #else 200 #define __I volatile const /*!< Defines 'read only' permissions */ 201 #endif 202 #define __O volatile /*!< Defines 'write only' permissions */ 203 #define __IO volatile /*!< Defines 'read / write' permissions */ 204 205 /*@} end of group SC000 */ 206 207 208 209 /******************************************************************************* 210 * Register Abstraction 211 Core Register contain: 212 - Core Register 213 - Core NVIC Register 214 - Core SCB Register 215 - Core SysTick Register 216 - Core MPU Register 217 ******************************************************************************/ 218 /** \defgroup CMSIS_core_register Defines and Type Definitions 219 \brief Type definitions and defines for Cortex-M processor based devices. 220 */ 221 222 /** \ingroup CMSIS_core_register 223 \defgroup CMSIS_CORE Status and Control Registers 224 \brief Core Register type definitions. 225 @{ 226 */ 227 228 /** \brief Union type to access the Application Program Status Register (APSR). 229 */ 230 typedef union 231 { 232 struct 233 { 234 #if (__CORTEX_M != 0x04) 235 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ 236 #else 237 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 238 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 239 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 240 #endif 241 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 242 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 243 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 244 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 245 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 246 } b; /*!< Structure used for bit access */ 247 uint32_t w; /*!< Type used for word access */ 248 } APSR_Type; 249 250 251 /** \brief Union type to access the Interrupt Program Status Register (IPSR). 252 */ 253 typedef union 254 { 255 struct 256 { 257 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 258 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 259 } b; /*!< Structure used for bit access */ 260 uint32_t w; /*!< Type used for word access */ 261 } IPSR_Type; 262 263 264 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 265 */ 266 typedef union 267 { 268 struct 269 { 270 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 271 #if (__CORTEX_M != 0x04) 272 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 273 #else 274 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ 275 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 276 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 277 #endif 278 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 279 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ 280 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 281 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 282 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 283 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 284 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 285 } b; /*!< Structure used for bit access */ 286 uint32_t w; /*!< Type used for word access */ 287 } xPSR_Type; 288 289 290 /** \brief Union type to access the Control Registers (CONTROL). 291 */ 292 typedef union 293 { 294 struct 295 { 296 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 297 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 298 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 299 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 300 } b; /*!< Structure used for bit access */ 301 uint32_t w; /*!< Type used for word access */ 302 } CONTROL_Type; 303 304 /*@} end of group CMSIS_CORE */ 305 306 307 /** \ingroup CMSIS_core_register 308 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 309 \brief Type definitions for the NVIC Registers 310 @{ 311 */ 312 313 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 314 */ 315 typedef struct 316 { 317 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 318 uint32_t RESERVED0[31]; 319 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 320 uint32_t RSERVED1[31]; 321 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 322 uint32_t RESERVED2[31]; 323 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 324 uint32_t RESERVED3[31]; 325 uint32_t RESERVED4[64]; 326 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 327 } NVIC_Type; 328 329 /*@} end of group CMSIS_NVIC */ 330 331 332 /** \ingroup CMSIS_core_register 333 \defgroup CMSIS_SCB System Control Block (SCB) 334 \brief Type definitions for the System Control Block Registers 335 @{ 336 */ 337 338 /** \brief Structure type to access the System Control Block (SCB). 339 */ 340 typedef struct 341 { 342 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 343 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 344 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 345 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 346 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 347 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 348 uint32_t RESERVED0[1]; 349 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 350 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 351 uint32_t RESERVED1[154]; 352 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */ 353 } SCB_Type; 354 355 /* SCB CPUID Register Definitions */ 356 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ 357 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 358 359 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ 360 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 361 362 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ 363 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 364 365 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ 366 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 367 368 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ 369 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ 370 371 /* SCB Interrupt Control State Register Definitions */ 372 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ 373 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 374 375 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ 376 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 377 378 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ 379 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 380 381 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ 382 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 383 384 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ 385 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 386 387 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ 388 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 389 390 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ 391 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 392 393 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ 394 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 395 396 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ 397 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ 398 399 /* SCB Interrupt Control State Register Definitions */ 400 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ 401 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 402 403 /* SCB Application Interrupt and Reset Control Register Definitions */ 404 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ 405 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 406 407 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ 408 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 409 410 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ 411 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 412 413 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ 414 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 415 416 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ 417 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 418 419 /* SCB System Control Register Definitions */ 420 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ 421 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 422 423 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ 424 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 425 426 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ 427 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 428 429 /* SCB Configuration Control Register Definitions */ 430 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ 431 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 432 433 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ 434 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 435 436 /* SCB System Handler Control and State Register Definitions */ 437 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ 438 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 439 440 /* SCB Security Features Register Definitions */ 441 #define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */ 442 #define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */ 443 444 #define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */ 445 #define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */ 446 447 /*@} end of group CMSIS_SCB */ 448 449 450 /** \ingroup CMSIS_core_register 451 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 452 \brief Type definitions for the System Control and ID Register not in the SCB 453 @{ 454 */ 455 456 /** \brief Structure type to access the System Control and ID Register not in the SCB. 457 */ 458 typedef struct 459 { 460 uint32_t RESERVED0[2]; 461 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 462 } SCnSCB_Type; 463 464 /* Auxiliary Control Register Definitions */ 465 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ 466 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ 467 468 /*@} end of group CMSIS_SCnotSCB */ 469 470 471 /** \ingroup CMSIS_core_register 472 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 473 \brief Type definitions for the System Timer Registers. 474 @{ 475 */ 476 477 /** \brief Structure type to access the System Timer (SysTick). 478 */ 479 typedef struct 480 { 481 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 482 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 483 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 484 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 485 } SysTick_Type; 486 487 /* SysTick Control / Status Register Definitions */ 488 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ 489 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 490 491 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ 492 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 493 494 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ 495 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 496 497 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ 498 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ 499 500 /* SysTick Reload Register Definitions */ 501 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ 502 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ 503 504 /* SysTick Current Register Definitions */ 505 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ 506 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ 507 508 /* SysTick Calibration Register Definitions */ 509 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ 510 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 511 512 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ 513 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 514 515 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ 516 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ 517 518 /*@} end of group CMSIS_SysTick */ 519 520 #if (__MPU_PRESENT == 1) 521 /** \ingroup CMSIS_core_register 522 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 523 \brief Type definitions for the Memory Protection Unit (MPU) 524 @{ 525 */ 526 527 /** \brief Structure type to access the Memory Protection Unit (MPU). 528 */ 529 typedef struct 530 { 531 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 532 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 533 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 534 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 535 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 536 } MPU_Type; 537 538 /* MPU Type Register */ 539 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ 540 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 541 542 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ 543 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 544 545 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ 546 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ 547 548 /* MPU Control Register */ 549 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ 550 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 551 552 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ 553 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 554 555 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ 556 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ 557 558 /* MPU Region Number Register */ 559 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ 560 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ 561 562 /* MPU Region Base Address Register */ 563 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ 564 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 565 566 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ 567 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 568 569 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ 570 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ 571 572 /* MPU Region Attribute and Size Register */ 573 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ 574 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 575 576 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ 577 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 578 579 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ 580 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 581 582 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ 583 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 584 585 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ 586 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 587 588 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ 589 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 590 591 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ 592 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 593 594 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ 595 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 596 597 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ 598 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 599 600 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ 601 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ 602 603 /*@} end of group CMSIS_MPU */ 604 #endif 605 606 607 /** \ingroup CMSIS_core_register 608 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 609 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) 610 are only accessible over DAP and not via processor. Therefore 611 they are not covered by the Cortex-M0 header file. 612 @{ 613 */ 614 /*@} end of group CMSIS_CoreDebug */ 615 616 617 /** \ingroup CMSIS_core_register 618 \defgroup CMSIS_core_base Core Definitions 619 \brief Definitions for base addresses, unions, and structures. 620 @{ 621 */ 622 623 /* Memory mapping of SC000 Hardware */ 624 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 625 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 626 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 627 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 628 629 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 630 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 631 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 632 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 633 634 #if (__MPU_PRESENT == 1) 635 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 636 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 637 #endif 638 639 /*@} */ 640 641 642 643 /******************************************************************************* 644 * Hardware Abstraction Layer 645 Core Function Interface contains: 646 - Core NVIC Functions 647 - Core SysTick Functions 648 - Core Register Access Functions 649 ******************************************************************************/ 650 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 651 */ 652 653 654 655 /* ########################## NVIC functions #################################### */ 656 /** \ingroup CMSIS_Core_FunctionInterface 657 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 658 \brief Functions that manage interrupts and exceptions via the NVIC. 659 @{ 660 */ 661 662 /* Interrupt Priorities are WORD accessible only under ARMv6M */ 663 /* The following MACROS handle generation of the register offset and byte masks */ 664 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) 665 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) 666 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) 667 668 669 /** \brief Enable External Interrupt 670 671 The function enables a device-specific interrupt in the NVIC interrupt controller. 672 673 \param [in] IRQn External interrupt number. Value cannot be negative. 674 */ 675 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 676 { 677 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 678 } 679 680 681 /** \brief Disable External Interrupt 682 683 The function disables a device-specific interrupt in the NVIC interrupt controller. 684 685 \param [in] IRQn External interrupt number. Value cannot be negative. 686 */ 687 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 688 { 689 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 690 } 691 692 693 /** \brief Get Pending Interrupt 694 695 The function reads the pending register in the NVIC and returns the pending bit 696 for the specified interrupt. 697 698 \param [in] IRQn Interrupt number. 699 700 \return 0 Interrupt status is not pending. 701 \return 1 Interrupt status is pending. 702 */ 703 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 704 { 705 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); 706 } 707 708 709 /** \brief Set Pending Interrupt 710 711 The function sets the pending bit of an external interrupt. 712 713 \param [in] IRQn Interrupt number. Value cannot be negative. 714 */ 715 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 716 { 717 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 718 } 719 720 721 /** \brief Clear Pending Interrupt 722 723 The function clears the pending bit of an external interrupt. 724 725 \param [in] IRQn External interrupt number. Value cannot be negative. 726 */ 727 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 728 { 729 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ 730 } 731 732 733 /** \brief Set Interrupt Priority 734 735 The function sets the priority of an interrupt. 736 737 \note The priority cannot be set for every core interrupt. 738 739 \param [in] IRQn Interrupt number. 740 \param [in] priority Priority to set. 741 */ 742 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 743 { 744 if(IRQn < 0) { 745 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 746 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } 747 else { 748 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 749 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } 750 } 751 752 753 /** \brief Get Interrupt Priority 754 755 The function reads the priority of an interrupt. The interrupt 756 number can be positive to specify an external (device specific) 757 interrupt, or negative to specify an internal (core) interrupt. 758 759 760 \param [in] IRQn Interrupt number. 761 \return Interrupt Priority. Value is aligned automatically to the implemented 762 priority bits of the microcontroller. 763 */ 764 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) 765 { 766 767 if(IRQn < 0) { 768 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ 769 else { 770 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ 771 } 772 773 774 /** \brief System Reset 775 776 The function initiates a system reset request to reset the MCU. 777 */ 778 __STATIC_INLINE void NVIC_SystemReset(void) 779 { 780 __DSB(); /* Ensure all outstanding memory accesses included 781 buffered write are completed before reset */ 782 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | 783 SCB_AIRCR_SYSRESETREQ_Msk); 784 __DSB(); /* Ensure completion of memory access */ 785 while(1); /* wait until reset */ 786 } 787 788 /*@} end of CMSIS_Core_NVICFunctions */ 789 790 791 792 /* ################################## SysTick function ############################################ */ 793 /** \ingroup CMSIS_Core_FunctionInterface 794 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 795 \brief Functions that configure the System. 796 @{ 797 */ 798 799 #if (__Vendor_SysTickConfig == 0) 800 801 /** \brief System Tick Configuration 802 803 The function initializes the System Timer and its interrupt, and starts the System Tick Timer. 804 Counter is in free running mode to generate periodic interrupts. 805 806 \param [in] ticks Number of ticks between two interrupts. 807 808 \return 0 Function succeeded. 809 \return 1 Function failed. 810 811 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 812 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 813 must contain a vendor-specific implementation of this function. 814 815 */ 816 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 817 { 818 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ 819 820 SysTick->LOAD = ticks - 1; /* set reload register */ 821 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ 822 SysTick->VAL = 0; /* Load the SysTick Counter Value */ 823 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 824 SysTick_CTRL_TICKINT_Msk | 825 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 826 return (0); /* Function successful */ 827 } 828 829 #endif 830 831 /*@} end of CMSIS_Core_SysTickFunctions */ 832 833 834 835 836 #ifdef __cplusplus 837 } 838 #endif 839 840 #endif /* __CORE_SC000_H_DEPENDANT */ 841 842 #endif /* __CMSIS_GENERIC */ 843
