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Searched
refs:RASR
(Results
1 - 7
of
7
) sorted by null
/device/google/contexthub/firmware/os/platform/stm32/
mpu.c
99
MPU->
RASR
= 0; /* disable region before changing it */
101
MPU->
RASR
= MPU_SRD_BITS | MPU_BIT_ENABLE | attrs | ((lenVal-1) << 1);
154
uint32_t addr,
rasr
;
local
166
rasr
= MPU->
RASR
;
167
xn =
rasr
& MPU_RASR_XN_Msk;
168
ap = (
rasr
& MPU_RASR_AP_Msk) >> MPU_RASR_AP_Pos;
201
i, (
rasr
& MPU_RASR_ENABLE_Msk) ? 'E' : 'D',
203
addr + (1 << (((
rasr
& MPU_RASR_SIZE_Msk) >> MPU_RASR_SIZE_Pos) + 1))-1,
205
(
rasr
& MPU_RASR_TEX_Msk) >> MPU_RASR_TEX_Pos
[
all
...]
/device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
core_cm0plus.h
516
__IO uint32_t
RASR
; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
554
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU
RASR
: MPU Region Attribute field Position */
555
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU
RASR
: MPU Region Attribute field Mask */
557
#define MPU_RASR_XN_Pos 28 /*!< MPU
RASR
: ATTRS.XN Position */
558
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU
RASR
: ATTRS.XN Mask */
560
#define MPU_RASR_AP_Pos 24 /*!< MPU
RASR
: ATTRS.AP Position */
561
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU
RASR
: ATTRS.AP Mask */
563
#define MPU_RASR_TEX_Pos 19 /*!< MPU
RASR
: ATTRS.TEX Position */
564
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU
RASR
: ATTRS.TEX Mask */
566
#define MPU_RASR_S_Pos 18 /*!< MPU
RASR
: ATTRS.S Position *
[
all
...]
core_sc000.h
535
__IO uint32_t
RASR
; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
573
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU
RASR
: MPU Region Attribute field Position */
574
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU
RASR
: MPU Region Attribute field Mask */
576
#define MPU_RASR_XN_Pos 28 /*!< MPU
RASR
: ATTRS.XN Position */
577
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU
RASR
: ATTRS.XN Mask */
579
#define MPU_RASR_AP_Pos 24 /*!< MPU
RASR
: ATTRS.AP Position */
580
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU
RASR
: ATTRS.AP Mask */
582
#define MPU_RASR_TEX_Pos 19 /*!< MPU
RASR
: ATTRS.TEX Position */
583
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU
RASR
: ATTRS.TEX Mask */
585
#define MPU_RASR_S_Pos 18 /*!< MPU
RASR
: ATTRS.S Position *
[
all
...]
core_cm3.h
[
all
...]
core_cm4.h
[
all
...]
core_sc300.h
[
all
...]
core_cm7.h
[
all
...]
Completed in 295 milliseconds