| /device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/ |
| core_cm0.h | 315 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
574 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
586 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
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| core_cm0plus.h | 326 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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| core_sc000.h | 321 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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| core_cm3.h | 322 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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| core_cm4.h | 369 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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| core_sc300.h | 322 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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| core_cm7.h | 384 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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| /external/icu/icu4c/source/test/cintltst/ |
| cucdtst.c | 752 #define ISPR 0x100
788 { 0x0020, ISPR|ISSP|ISBL }, /* space */
789 { 0x0021, ISPU|ISGR|ISPR }, /* ! */
790 { 0x0033, ISDI|ISXD|ISAN| ISGR|ISPR }, /* 3 */
791 { 0x0040, ISPU|ISGR|ISPR }, /* @ */
792 { 0x0041, ISAL| ISUP| ISXD|ISAN| ISGR|ISPR }, /* A */
793 { 0x007a, ISAL|ISLO| ISAN| ISGR|ISPR }, /* z */
794 { 0x007b, ISPU|ISGR|ISPR }, /* { */
796 { 0x00a0, ISPR|ISSP|ISBL }, /* NBSP */
797 { 0x00a4, ISGR|ISPR }, /* currency sign *
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