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Searched
refs:CFSR
(Results
1 - 5
of
5
) sorted by null
/device/google/contexthub/firmware/os/cpu/cortexm4/
cpu.c
92
static void cpuPackSrBits(uint32_t *dstLo, uint32_t *dstHi, uint32_t sr, uint32_t hfsr, uint32_t
cfsr
)
97
//
CFSR
: 00000011 00001111 10111111 10111111 (total of 20 bits)
102
cfsr
&= 0x030FBFBF;
104
*dstLo = sr | ((
cfsr
<< 4) & 0x00FF0000) | (hfsr >> 12) | (hfsr << 8);
105
*dstHi = ((
cfsr
& 0x01000000) >> 18) | ((
cfsr
& 0x02000000) >> 13) | (
cfsr
& 0x00000fff);
118
uint32_t i, hfsr,
cfsr
, sr;
local
128
cpuUnpackSrBits(dbx->sr_hfsr_cfsr_lo, dbx->magic & HARD_FAULT_DROPBOX_MAGIC_DATA_MASK, &sr, &hfsr, &
cfsr
);
131
osLog(LOG_ERROR, "
CFSR
= 0x%08lX BITS = 0x%08lX\n", cfsr, dbx->bits)
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...]
/device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
core_cm3.h
358
__IO uint32_t
CFSR
; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
527
#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB
CFSR
: Usage Fault Status Register Position */
528
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB
CFSR
: Usage Fault Status Register Mask */
530
#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB
CFSR
: Bus Fault Status Register Position */
531
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB
CFSR
: Bus Fault Status Register Mask */
533
#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB
CFSR
: Memory Manage Fault Status Register Position */
534
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB
CFSR
: Memory Manage Fault Status Register Mask */
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core_cm4.h
405
__IO uint32_t
CFSR
; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
566
#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB
CFSR
: Usage Fault Status Register Position */
567
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB
CFSR
: Usage Fault Status Register Mask */
569
#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB
CFSR
: Bus Fault Status Register Position */
570
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB
CFSR
: Bus Fault Status Register Mask */
572
#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB
CFSR
: Memory Manage Fault Status Register Position */
573
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB
CFSR
: Memory Manage Fault Status Register Mask */
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...]
core_sc300.h
358
__IO uint32_t
CFSR
; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
522
#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB
CFSR
: Usage Fault Status Register Position */
523
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB
CFSR
: Usage Fault Status Register Mask */
525
#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB
CFSR
: Bus Fault Status Register Position */
526
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB
CFSR
: Bus Fault Status Register Mask */
528
#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB
CFSR
: Memory Manage Fault Status Register Position */
529
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB
CFSR
: Memory Manage Fault Status Register Mask */
[
all
...]
core_cm7.h
420
__IO uint32_t
CFSR
; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
[
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...]
Completed in 688 milliseconds