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  /device/linaro/bootloader/edk2/ArmPkg/Library/ArmMmuLib/AArch64/
ArmMmuLibCore.c 562 UINT64 TCR;
577 // Set TCR that allows us to retrieve T0SZ in the subsequent functions
583 TCR = T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB;
587 TCR |= TCR_PS_4GB;
589 TCR |= TCR_PS_64GB;
591 TCR |= TCR_PS_1TB;
593 TCR |= TCR_PS_4TB;
595 TCR |= TCR_PS_16TB;
597 TCR |= TCR_PS_256TB;
605 TCR = T0SZ | TCR_TG0_4KB | TCR_TG1_4KB | TCR_EPD1;
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  /external/syslinux/gpxe/src/drivers/net/
smc9000.c 533 _outw(TCR_CLEAR, ioaddr + TCR);
740 _outw(inw(nic->ioaddr + TCR ) | TCR_ENABLE, nic->ioaddr + TCR );
809 _outb( TCR_CLEAR, nic->ioaddr + TCR );
910 /* see the header file for options in TCR/RCR NORMAL*/
911 _outw(TCR_NORMAL, nic->ioaddr + TCR);
smc9000.h 66 #define TCR 0 /* transmit control register */
74 /* the normal settings for the TCR register : */
via-velocity.c 537 td_ptr->tdesc1.TCR = TCR0_TIC;
571 td_ptr->tdesc1.TCR |= TCR0_VETAG;
    [all...]
via-velocity.h 240 u8 TCR;
472 * Bits in the TCR register
1036 volatile u8 TCR;
    [all...]
  /device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
core_cm3.h     [all...]
core_cm4.h     [all...]
core_sc300.h     [all...]
core_cm7.h     [all...]
  /device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/include/drivers/
smmu.h 678 make_smmu_cb_cfg(TCR, n), \
  /build/make/tools/droiddoc/templates-ndk/assets/js/
android_3p-bundle.js     [all...]
  /external/doclava/res/assets/templates-sdk/assets/js/
android_3p-bundle.js     [all...]

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