| /art/compiler/optimizing/ |
| intrinsics_x86_64.cc | 95 CpuRegister src_curr_addr = locations->GetTemp(0).AsRegister<CpuRegister>();
96 CpuRegister dst_curr_addr = locations->GetTemp(1).AsRegister<CpuRegister>();
97 CpuRegister src_stop_addr = locations->GetTemp(2).AsRegister<CpuRegister>();
148 __ movd(output.AsRegister<CpuRegister>(), input.AsFpuRegister<XmmRegister>(), is64bit);
154 __ movd(output.AsFpuRegister<XmmRegister>(), input.AsRegister<CpuRegister>(), is64bit);
195 CpuRegister out = locations->Out().AsRegister<CpuRegister>();
299 CpuRegister out = output.AsRegister<CpuRegister>();
300 CpuRegister mask = locations->GetTemp(0).AsRegister<CpuRegister>();
479 CpuRegister out = locations->Out().AsRegister<CpuRegister>();
480 CpuRegister op2 = op2_loc.AsRegister<CpuRegister>()
[all...] |
| code_generator_x86_64.cc | 201 Address array_len(array_loc.AsRegister<CpuRegister>(), len_offset);
208 __ movl(length_loc.AsRegister<CpuRegister>(), array_len);
210 __ shrl(length_loc.AsRegister<CpuRegister>(), Immediate(1));
344 __ UnpoisonHeapReference(locations->InAt(1).AsRegister<CpuRegister>());
480 CpuRegister ref_cpu_reg = ref_.AsRegister<CpuRegister>();
481 Register ref_reg = ref_cpu_reg.AsRegister();
573 CpuRegister ref_cpu_reg = ref_.AsRegister<CpuRegister>();
574 Register ref_reg = ref_cpu_reg.AsRegister();
646 bool base_equals_value = (base.AsRegister() == value.AsRegister());
[all...] |
| intrinsics_x86.cc | 103 Register src = locations->InAt(0).AsRegister<Register>();
105 Register dest = locations->InAt(2).AsRegister<Register>();
109 Register temp1 = temp1_loc.AsRegister<Register>();
110 Register temp2 = locations->GetTemp(1).AsRegister<Register>();
111 Register temp3 = locations->GetTemp(2).AsRegister<Register>();
134 __ leal(temp2, Address(src_pos.AsRegister<Register>(), temp1, ScaleFactor::TIMES_1, 0));
157 __ leal(temp3, Address(dest_pos.AsRegister<Register>(), temp1, ScaleFactor::TIMES_1, 0));
210 __ movd(output.AsRegister<Register>(), input.AsFpuRegister<XmmRegister>());
226 __ movd(output.AsFpuRegister<XmmRegister>(), input.AsRegister<Register>());
282 Register out = locations->Out().AsRegister<Register>()
[all...] |
| intrinsics_mips64.cc | 62 GpuRegister trg_reg = trg.AsRegister<GpuRegister>();
153 GpuRegister out = locations->Out().AsRegister<GpuRegister>();
188 GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>();
226 GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>();
227 GpuRegister out = locations->Out().AsRegister<GpuRegister>();
278 GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>();
279 GpuRegister out = locations->Out().AsRegister<GpuRegister>();
313 __ Dsbh(out.AsRegister<GpuRegister>(), in.AsRegister<GpuRegister>());
314 __ Dshd(out.AsRegister<GpuRegister>(), out.AsRegister<GpuRegister>())
[all...] |
| code_generator_x86.cc | 150 Address array_len(array_loc.AsRegister<Register>(), len_offset);
157 __ movl(length_loc.AsRegister<Register>(), array_len);
159 __ shrl(length_loc.AsRegister<Register>(), Immediate(1));
324 __ UnpoisonHeapReference(locations->InAt(1).AsRegister<Register>());
465 Register ref_reg = ref_.AsRegister<Register>();
552 Register ref_reg = ref_.AsRegister<Register>();
717 Register reg_out = out_.AsRegister<Register>();
740 Register index_reg = index_.AsRegister<Register>();
[all...] |
| intrinsics_mips.cc | 74 Register trg_reg = trg.AsRegister<Register>();
172 Register out = locations->Out().AsRegister<Register>();
213 Register in = locations->InAt(0).AsRegister<Register>();
258 Register in = locations->InAt(0).AsRegister<Register>();
259 Register out = locations->Out().AsRegister<Register>();
272 Register in = locations->InAt(0).AsRegister<Register>();
273 Register out = locations->Out().AsRegister<Register>();
446 Register out = locations->Out().AsRegister<Register>();
462 Register in = locations->InAt(0).AsRegister<Register>();
494 Register out = locations->Out().AsRegister<Register>()
[all...] |
| code_generator_mips64.cc | 488 GpuRegister ref_reg = ref_.AsRegister<GpuRegister>();
528 DCHECK_EQ(entrypoint_.AsRegister<GpuRegister>(), T9);
529 __ Jalr(entrypoint_.AsRegister<GpuRegister>());
583 GpuRegister ref_reg = ref_.AsRegister<GpuRegister>();
650 GpuRegister offset = field_offset_.AsRegister<GpuRegister>();
742 GpuRegister reg_out = out_.AsRegister<GpuRegister>();
765 GpuRegister index_reg = index_.AsRegister<GpuRegister>();
[all...] |
| code_generator_mips.cc | 531 Register ref_reg = ref_.AsRegister<Register>();
571 DCHECK_EQ(entrypoint_.AsRegister<Register>(), T9);
572 __ Jalr(entrypoint_.AsRegister<Register>());
627 Register ref_reg = ref_.AsRegister<Register>();
795 Register reg_out = out_.AsRegister<Register>();
818 Register index_reg = index_.AsRegister<Register>();
[all...] |
| code_generator_vector_x86_64.cc | 72 __ movd(dst, locations->InAt(0).AsRegister<CpuRegister>(), /*64-bit*/ false);
80 __ movd(dst, locations->InAt(0).AsRegister<CpuRegister>(), /*64-bit*/ false);
86 __ movd(dst, locations->InAt(0).AsRegister<CpuRegister>(), /*64-bit*/ false);
91 __ movd(dst, locations->InAt(0).AsRegister<CpuRegister>(), /*64-bit*/ true);
147 __ movd(locations->Out().AsRegister<CpuRegister>(), src, /*64-bit*/ false);
151 __ movd(locations->Out().AsRegister<CpuRegister>(), src, /*64-bit*/ true);
[all...] |
| code_generator_vector_mips64.cc | 63 __ FillB(dst, locations->InAt(0).AsRegister<GpuRegister>());
68 __ FillH(dst, locations->InAt(0).AsRegister<GpuRegister>());
72 __ FillW(dst, locations->InAt(0).AsRegister<GpuRegister>());
76 __ FillD(dst, locations->InAt(0).AsRegister<GpuRegister>());
126 __ Copy_sW(locations->Out().AsRegister<GpuRegister>(), src, 0);
130 __ Copy_sD(locations->Out().AsRegister<GpuRegister>(), src, 0);
[all...] |
| code_generator_vector_x86.cc | 77 __ movd(dst, locations->InAt(0).AsRegister<Register>());
85 __ movd(dst, locations->InAt(0).AsRegister<Register>());
91 __ movd(dst, locations->InAt(0).AsRegister<Register>());
160 __ movd(locations->Out().AsRegister<Register>(), src);
[all...] |
| code_generator_vector_mips.cc | 58 __ FillB(dst, locations->InAt(0).AsRegister<Register>());
63 __ FillH(dst, locations->InAt(0).AsRegister<Register>());
67 __ FillW(dst, locations->InAt(0).AsRegister<Register>());
127 __ Copy_sW(locations->Out().AsRegister<Register>(), src, 0);
[all...] |
| locations.h | 181 T AsRegister() const {
|
| /art/compiler/utils/x86_64/ |
| managed_register_x86_64.cc | 63 Register low = AsRegisterPairLow().AsRegister();
64 Register high = AsRegisterPairHigh().AsRegister();
101 os << "CPU: " << static_cast<int>(AsCpuRegister().AsRegister());
|
| constants_x86_64.h | 35 constexpr Register AsRegister() const {
|
| assembler_x86_64.cc | 28 return os << reg.AsRegister();
42 if (addr.rm() != RSP || addr.cpu_index().AsRegister() == RSP) {
51 if (addr.rm() != RSP || addr.cpu_index().AsRegister() == RSP) {
57 if (addr.rm() != RSP || addr.cpu_index().AsRegister() == RSP) {
[all...] |
| assembler_x86_64.h | 197 CHECK_EQ(base_in.AsRegister(), RSP);
228 CHECK_NE(index_in.AsRegister(), RSP); // Illegal addressing mode.
235 CHECK_NE(index_in.AsRegister(), RSP); // Illegal addressing mode.
[all...] |
| jni_macro_assembler_x86_64.cc | 52 cfi().RelOffset(DWARFReg(spill.AsCpuRegister().AsRegister()), 0);
130 cfi().Restore(DWARFReg(spill.AsCpuRegister().AsRegister()));
|
| assembler_x86_64_test.cc | 125 return a.AsRegister() < b.AsRegister();
516 if (index->AsRegister() == x86_64::RSP) {
519 } else if (base->AsRegister() == index->AsRegister()) {
[all...] |
| /external/v8/src/compiler/ |
| instruction-selector-impl.h | 145 location.AsRegister());
295 int reg_id = primary_location.AsRegister();
320 location.AsRegister(), virtual_register);
323 location.AsRegister(), virtual_register);
|
| linkage.h | 145 int32_t AsRegister() const {
|
| /art/compiler/jni/quick/x86_64/ |
| calling_convention_x86_64.cc | 60 result |= (1 << r.AsX86_64().AsCpuRegister().AsRegister());
|
| /external/vixl/src/aarch32/ |
| instructions-aarch32.h | 160 Register AsRegister() const {
171 return os << reg.AsRegister();
[all...] |
| macro-assembler-aarch32.h | 500 return GetScratchRegisterList()->Includes(reg.AsRegister());
[all...] |
