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    Searched refs:CP_PACKET0 (Results 1 - 12 of 12) sorted by null

  /external/mesa3d/src/gallium/drivers/r300/
r300_cb.h 132 OUT_CB(CP_PACKET0(register, 0)); \
140 OUT_CB(CP_PACKET0(register, (count) - 1)); \
145 OUT_CB(CP_PACKET0(register, (count) - 1) | RADEON_ONE_REG_WR); \
r300_cs.h 83 OUT_CS(CP_PACKET0(register, 0)); \
90 OUT_CS(CP_PACKET0((register), ((count) - 1)))
93 OUT_CS(CP_PACKET0((register), ((count) - 1)) | RADEON_ONE_REG_WR)
r300_reg.h     [all...]
  /external/mesa3d/src/mesa/drivers/dri/radeon/
radeon_state_init.c 163 return CP_PACKET0(packet[id].start, packet[id].len - 1);
243 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
245 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
254 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
375 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
379 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
382 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
386 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
388 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
393 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0))
    [all...]
radeon_cmdbuf.h 19 #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2))
radeon_ioctl.c 102 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0));
104 OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
107 OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
113 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0));
radeon_blit.c 37 return CP_PACKET0(reg, count - 1);
radeon_context.c 116 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
  /external/mesa3d/src/mesa/drivers/dri/r200/
r200_state_init.c 167 return CP_PACKET0(packet[id].start, packet[id].len - 1);
280 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
282 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
296 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
298 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
309 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
318 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
492 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
496 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
499 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0))
    [all...]
r200_context.c 151 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
r200_blit.c 37 return CP_PACKET0(reg, count - 1);
r200_cmdbuf.c 215 OUT_BATCH(CP_PACKET0(R200_SE_VF_MAX_VTX_INDX, 0));

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