1 /* 2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. 3 4 The Weather Channel (TM) funded Tungsten Graphics to develop the 5 initial release of the Radeon 8500 driver under the XFree86 license. 6 This notice must be preserved. 7 8 Permission is hereby granted, free of charge, to any person obtaining 9 a copy of this software and associated documentation files (the 10 "Software"), to deal in the Software without restriction, including 11 without limitation the rights to use, copy, modify, merge, publish, 12 distribute, sublicense, and/or sell copies of the Software, and to 13 permit persons to whom the Software is furnished to do so, subject to 14 the following conditions: 15 16 The above copyright notice and this permission notice (including the 17 next paragraph) shall be included in all copies or substantial 18 portions of the Software. 19 20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 */ 28 29 /* 30 * Authors: 31 * Keith Whitwell <keithw (at) vmware.com> 32 */ 33 34 #include "main/glheader.h" 35 #include "main/imports.h" 36 #include "main/enums.h" 37 #include "main/api_arrayelt.h" 38 39 #include "swrast/swrast.h" 40 #include "vbo/vbo.h" 41 #include "tnl/t_pipeline.h" 42 #include "swrast_setup/swrast_setup.h" 43 44 #include "radeon_common.h" 45 #include "radeon_mipmap_tree.h" 46 #include "r200_context.h" 47 #include "r200_ioctl.h" 48 #include "r200_state.h" 49 #include "radeon_queryobj.h" 50 51 #include "xmlpool.h" 52 53 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in 54 * 1.3 cmdbuffers allow all previous state to be updated as well as 55 * the tcl scalar and vector areas. 56 */ 57 static struct { 58 int start; 59 int len; 60 const char *name; 61 } packet[RADEON_MAX_STATE_PACKETS] = { 62 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"}, 63 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"}, 64 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"}, 65 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"}, 66 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"}, 67 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"}, 68 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"}, 69 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"}, 70 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"}, 71 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"}, 72 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"}, 73 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"}, 74 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"}, 75 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"}, 76 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"}, 77 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"}, 78 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"}, 79 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"}, 80 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"}, 81 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"}, 82 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17, 83 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"}, 84 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"}, 85 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"}, 86 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"}, 87 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"}, 88 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"}, 89 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"}, 90 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"}, 91 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"}, 92 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"}, 93 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"}, 94 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"}, 95 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"}, 96 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"}, 97 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"}, 98 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"}, 99 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"}, 100 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"}, 101 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"}, 102 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"}, 103 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"}, 104 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"}, 105 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"}, 106 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"}, 107 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"}, 108 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"}, 109 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"}, 110 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"}, 111 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"}, 112 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, 113 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"}, 114 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"}, 115 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"}, 116 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"}, 117 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"}, 118 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"}, 119 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"}, 120 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"}, 121 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"}, 122 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"}, 123 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"}, 124 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, 125 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"}, 126 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */ 127 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */ 128 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"}, 129 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"}, 130 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"}, 131 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"}, 132 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"}, 133 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"}, 134 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"}, 135 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"}, 136 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"}, 137 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"}, 138 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"}, 139 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"}, 140 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"}, 141 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"}, 142 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"}, 143 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"}, 144 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"}, 145 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"}, 146 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, 147 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, 148 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, 149 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, 150 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */ 151 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"}, 152 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"}, 153 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"}, 154 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"}, 155 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"}, 156 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, 157 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, 158 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, 159 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"}, 160 }; 161 162 /* ============================================================= 163 * State initialization 164 */ 165 static int cmdpkt( r200ContextPtr rmesa, int id ) 166 { 167 return CP_PACKET0(packet[id].start, packet[id].len - 1); 168 } 169 170 static int cmdvec( int offset, int stride, int count ) 171 { 172 drm_radeon_cmd_header_t h; 173 h.i = 0; 174 h.vectors.cmd_type = RADEON_CMD_VECTORS; 175 h.vectors.offset = offset; 176 h.vectors.stride = stride; 177 h.vectors.count = count; 178 return h.i; 179 } 180 181 /* warning: the count here is divided by 4 compared to other cmds 182 (so it doesn't exceed the char size)! */ 183 static int cmdveclinear( int offset, int count ) 184 { 185 drm_radeon_cmd_header_t h; 186 h.i = 0; 187 h.veclinear.cmd_type = RADEON_CMD_VECLINEAR; 188 h.veclinear.addr_lo = offset & 0xff; 189 h.veclinear.addr_hi = (offset & 0xff00) >> 8; 190 h.veclinear.count = count; 191 return h.i; 192 } 193 194 static int cmdscl( int offset, int stride, int count ) 195 { 196 drm_radeon_cmd_header_t h; 197 h.i = 0; 198 h.scalars.cmd_type = RADEON_CMD_SCALARS; 199 h.scalars.offset = offset; 200 h.scalars.stride = stride; 201 h.scalars.count = count; 202 return h.i; 203 } 204 205 static int cmdscl2( int offset, int stride, int count ) 206 { 207 drm_radeon_cmd_header_t h; 208 h.i = 0; 209 h.scalars.cmd_type = RADEON_CMD_SCALARS2; 210 h.scalars.offset = offset - 0x100; 211 h.scalars.stride = stride; 212 h.scalars.count = count; 213 return h.i; 214 } 215 216 /** 217 * Check functions are used to check if state is active. 218 * If it is active check function returns maximum emit size. 219 */ 220 #define CHECK( NM, FLAG, ADD ) \ 221 static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom) \ 222 { \ 223 r200ContextPtr rmesa = R200_CONTEXT(ctx); \ 224 (void) rmesa; \ 225 return (FLAG) ? atom->cmd_size + (ADD) : 0; \ 226 } 227 228 #define TCL_CHECK( NM, FLAG, ADD ) \ 229 static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom) \ 230 { \ 231 r200ContextPtr rmesa = R200_CONTEXT(ctx); \ 232 return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size + (ADD) : 0; \ 233 } 234 235 #define TCL_OR_VP_CHECK( NM, FLAG, ADD ) \ 236 static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom ) \ 237 { \ 238 r200ContextPtr rmesa = R200_CONTEXT(ctx); \ 239 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \ 240 } 241 242 #define VP_CHECK( NM, FLAG, ADD ) \ 243 static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom ) \ 244 { \ 245 r200ContextPtr rmesa = R200_CONTEXT(ctx); \ 246 (void) atom; \ 247 return (!rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size + (ADD) : 0; \ 248 } 249 250 CHECK( always, GL_TRUE, 0 ) 251 CHECK( always_add4, GL_TRUE, 4 ) 252 CHECK( never, GL_FALSE, 0 ) 253 CHECK( tex_any, ctx->Texture._MaxEnabledTexImageUnit != -1, 0 ) 254 CHECK( tf, (ctx->Texture._MaxEnabledTexImageUnit != -1 && !ctx->ATIFragmentShader._Enabled), 0 ); 255 CHECK( pix_zero, !ctx->ATIFragmentShader._Enabled, 0 ) 256 CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !ctx->ATIFragmentShader._Enabled), 0 ) 257 CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)), 0 ) 258 CHECK( afs, ctx->ATIFragmentShader._Enabled, 0 ) 259 CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT, 3 + 3*5 - CUBE_STATE_SIZE ) 260 CHECK( tex_cube_cs, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT, 2 + 4*5 - CUBE_STATE_SIZE ) 261 TCL_CHECK( tcl_fog_add4, ctx->Fog.Enabled, 4 ) 262 TCL_CHECK( tcl, GL_TRUE, 0 ) 263 TCL_CHECK( tcl_add8, GL_TRUE, 8 ) 264 TCL_CHECK( tcl_add4, GL_TRUE, 4 ) 265 TCL_CHECK( tcl_tex_add4, rmesa->state.texture.unit[atom->idx].unitneeded, 4 ) 266 TCL_CHECK( tcl_lighting_add4, ctx->Light.Enabled, 4 ) 267 TCL_CHECK( tcl_lighting_add6, ctx->Light.Enabled, 6 ) 268 TCL_CHECK( tcl_light_add6, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled, 6 ) 269 TCL_OR_VP_CHECK( tcl_ucp_add4, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))), 4 ) 270 TCL_OR_VP_CHECK( tcl_or_vp, GL_TRUE, 0 ) 271 TCL_OR_VP_CHECK( tcl_or_vp_add2, GL_TRUE, 2 ) 272 VP_CHECK( tcl_vp, GL_TRUE, 0 ) 273 VP_CHECK( tcl_vp_add4, GL_TRUE, 4 ) 274 VP_CHECK( tcl_vp_size_add4, ctx->VertexProgram.Current->arb.NumNativeInstructions > 64, 4 ) 275 VP_CHECK( tcl_vpp_size_add4, ctx->VertexProgram.Current->arb.NumNativeParameters > 96, 4 ) 276 277 #define OUT_VEC(hdr, data) do { \ 278 drm_radeon_cmd_header_t h; \ 279 h.i = hdr; \ 280 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \ 281 OUT_BATCH(0); \ 282 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \ 283 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \ 284 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \ 285 OUT_BATCH_TABLE((data), h.vectors.count); \ 286 } while(0) 287 288 #define OUT_VECLINEAR(hdr, data) do { \ 289 drm_radeon_cmd_header_t h; \ 290 uint32_t _start, _sz; \ 291 h.i = hdr; \ 292 _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8); \ 293 _sz = h.veclinear.count * 4; \ 294 if (_sz) { \ 295 BEGIN_BATCH(dwords); \ 296 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \ 297 OUT_BATCH(0); \ 298 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \ 299 OUT_BATCH(_start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \ 300 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, _sz - 1)); \ 301 OUT_BATCH_TABLE((data), _sz); \ 302 END_BATCH(); \ 303 } \ 304 } while(0) 305 306 #define OUT_SCL(hdr, data) do { \ 307 drm_radeon_cmd_header_t h; \ 308 h.i = hdr; \ 309 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \ 310 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \ 311 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \ 312 OUT_BATCH_TABLE((data), h.scalars.count); \ 313 } while(0) 314 315 #define OUT_SCL2(hdr, data) do { \ 316 drm_radeon_cmd_header_t h; \ 317 h.i = hdr; \ 318 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \ 319 OUT_BATCH((h.scalars.offset + 0x100) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \ 320 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \ 321 OUT_BATCH_TABLE((data), h.scalars.count); \ 322 } while(0) 323 static int check_rrb(struct gl_context *ctx, struct radeon_state_atom *atom) 324 { 325 r200ContextPtr r200 = R200_CONTEXT(ctx); 326 struct radeon_renderbuffer *rrb; 327 rrb = radeon_get_colorbuffer(&r200->radeon); 328 if (!rrb || !rrb->bo) 329 return 0; 330 return atom->cmd_size; 331 } 332 333 static int check_polygon_stipple(struct gl_context *ctx, 334 struct radeon_state_atom *atom) 335 { 336 r200ContextPtr r200 = R200_CONTEXT(ctx); 337 if (r200->hw.set.cmd[SET_RE_CNTL] & R200_STIPPLE_ENABLE) 338 return atom->cmd_size; 339 return 0; 340 } 341 342 static void mtl_emit(struct gl_context *ctx, struct radeon_state_atom *atom) 343 { 344 r200ContextPtr r200 = R200_CONTEXT(ctx); 345 BATCH_LOCALS(&r200->radeon); 346 uint32_t dwords = atom->check(ctx, atom); 347 348 BEGIN_BATCH(dwords); 349 OUT_VEC(atom->cmd[MTL_CMD_0], (atom->cmd+1)); 350 OUT_SCL2(atom->cmd[MTL_CMD_1], (atom->cmd + 18)); 351 END_BATCH(); 352 } 353 354 static void lit_emit(struct gl_context *ctx, struct radeon_state_atom *atom) 355 { 356 r200ContextPtr r200 = R200_CONTEXT(ctx); 357 BATCH_LOCALS(&r200->radeon); 358 uint32_t dwords = atom->check(ctx, atom); 359 360 BEGIN_BATCH(dwords); 361 OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1); 362 OUT_SCL(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1); 363 END_BATCH(); 364 } 365 366 static void ptp_emit(struct gl_context *ctx, struct radeon_state_atom *atom) 367 { 368 r200ContextPtr r200 = R200_CONTEXT(ctx); 369 BATCH_LOCALS(&r200->radeon); 370 uint32_t dwords = atom->check(ctx, atom); 371 372 BEGIN_BATCH(dwords); 373 OUT_VEC(atom->cmd[PTP_CMD_0], atom->cmd+1); 374 OUT_VEC(atom->cmd[PTP_CMD_1], atom->cmd+PTP_CMD_1+1); 375 END_BATCH(); 376 } 377 378 static void veclinear_emit(struct gl_context *ctx, struct radeon_state_atom *atom) 379 { 380 r200ContextPtr r200 = R200_CONTEXT(ctx); 381 BATCH_LOCALS(&r200->radeon); 382 uint32_t dwords = atom->check(ctx, atom); 383 384 OUT_VECLINEAR(atom->cmd[0], atom->cmd+1); 385 } 386 387 static void scl_emit(struct gl_context *ctx, struct radeon_state_atom *atom) 388 { 389 r200ContextPtr r200 = R200_CONTEXT(ctx); 390 BATCH_LOCALS(&r200->radeon); 391 uint32_t dwords = atom->check(ctx, atom); 392 393 BEGIN_BATCH(dwords); 394 OUT_SCL(atom->cmd[0], atom->cmd+1); 395 END_BATCH(); 396 } 397 398 399 static void vec_emit(struct gl_context *ctx, struct radeon_state_atom *atom) 400 { 401 r200ContextPtr r200 = R200_CONTEXT(ctx); 402 BATCH_LOCALS(&r200->radeon); 403 uint32_t dwords = atom->check(ctx, atom); 404 405 BEGIN_BATCH(dwords); 406 OUT_VEC(atom->cmd[0], atom->cmd+1); 407 END_BATCH(); 408 } 409 410 static int check_always_ctx( struct gl_context *ctx, struct radeon_state_atom *atom) 411 { 412 r200ContextPtr r200 = R200_CONTEXT(ctx); 413 struct radeon_renderbuffer *rrb, *drb; 414 uint32_t dwords; 415 416 rrb = radeon_get_colorbuffer(&r200->radeon); 417 if (!rrb || !rrb->bo) { 418 return 0; 419 } 420 421 drb = radeon_get_depthbuffer(&r200->radeon); 422 423 dwords = 10; 424 if (drb) 425 dwords += 6; 426 if (rrb) 427 dwords += 8; 428 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) 429 dwords += 4; 430 431 432 return dwords; 433 } 434 435 static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) 436 { 437 r200ContextPtr r200 = R200_CONTEXT(ctx); 438 BATCH_LOCALS(&r200->radeon); 439 struct radeon_renderbuffer *rrb, *drb; 440 uint32_t cbpitch = 0; 441 uint32_t zbpitch = 0; 442 uint32_t dwords = atom->check(ctx, atom); 443 uint32_t depth_fmt; 444 445 rrb = radeon_get_colorbuffer(&r200->radeon); 446 if (!rrb || !rrb->bo) { 447 return; 448 } 449 450 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); 451 if (rrb->cpp == 4) 452 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; 453 else switch (rrb->base.Base.Format) { 454 case MESA_FORMAT_B5G6R5_UNORM: 455 case MESA_FORMAT_R5G6B5_UNORM: 456 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; 457 break; 458 case MESA_FORMAT_B4G4R4A4_UNORM: 459 case MESA_FORMAT_A4R4G4B4_UNORM: 460 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444; 461 break; 462 case MESA_FORMAT_B5G5R5A1_UNORM: 463 case MESA_FORMAT_A1R5G5B5_UNORM: 464 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555; 465 break; 466 default: 467 _mesa_problem(ctx, "Unexpected format in ctx_emit_cs"); 468 } 469 470 cbpitch = (rrb->pitch / rrb->cpp); 471 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) 472 cbpitch |= R200_COLOR_TILE_ENABLE; 473 if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) 474 cbpitch |= R200_COLOR_MICROTILE_ENABLE; 475 476 477 drb = radeon_get_depthbuffer(&r200->radeon); 478 if (drb) { 479 zbpitch = (drb->pitch / drb->cpp); 480 if (drb->cpp == 4) 481 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; 482 else 483 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; 484 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK; 485 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt; 486 } 487 488 /* output the first 7 bytes of context */ 489 BEGIN_BATCH(dwords); 490 491 /* In the CS case we need to split this up */ 492 OUT_BATCH(CP_PACKET0(packet[0].start, 3)); 493 OUT_BATCH_TABLE((atom->cmd + 1), 4); 494 495 if (drb) { 496 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0)); 497 OUT_BATCH_RELOC(0, drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); 498 499 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0)); 500 OUT_BATCH(zbpitch); 501 } 502 503 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0)); 504 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]); 505 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1)); 506 OUT_BATCH(atom->cmd[CTX_PP_CNTL]); 507 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); 508 509 510 if (rrb) { 511 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0)); 512 OUT_BATCH_RELOC(rrb->draw_offset, rrb->bo, rrb->draw_offset, 0, RADEON_GEM_DOMAIN_VRAM, 0); 513 514 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); 515 OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0); 516 } 517 518 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) { 519 OUT_BATCH_TABLE((atom->cmd + 14), 4); 520 } 521 522 END_BATCH(); 523 } 524 525 static int get_tex_mm_size(struct gl_context* ctx, struct radeon_state_atom *atom) 526 { 527 r200ContextPtr r200 = R200_CONTEXT(ctx); 528 uint32_t dwords = atom->cmd_size + 2; 529 int hastexture = 1; 530 int i = atom->idx; 531 radeonTexObj *t = r200->state.texture.unit[i].texobj; 532 if (!t) 533 hastexture = 0; 534 else { 535 if (!t->mt && !t->bo) 536 hastexture = 0; 537 } 538 539 if (!hastexture) 540 dwords -= 4; 541 return dwords; 542 } 543 544 static int check_tex_pair_mm(struct gl_context* ctx, struct radeon_state_atom *atom) 545 { 546 r200ContextPtr r200 = R200_CONTEXT(ctx); 547 /** XOR is bit flip operation so use it for finding pair */ 548 if (!(r200->state.texture.unit[atom->idx].unitneeded | r200->state.texture.unit[atom->idx ^ 1].unitneeded)) 549 return 0; 550 551 return get_tex_mm_size(ctx, atom); 552 } 553 554 static int check_tex_mm(struct gl_context* ctx, struct radeon_state_atom *atom) 555 { 556 r200ContextPtr r200 = R200_CONTEXT(ctx); 557 if (!(r200->state.texture.unit[atom->idx].unitneeded)) 558 return 0; 559 560 return get_tex_mm_size(ctx, atom); 561 } 562 563 564 static void tex_emit_mm(struct gl_context *ctx, struct radeon_state_atom *atom) 565 { 566 r200ContextPtr r200 = R200_CONTEXT(ctx); 567 BATCH_LOCALS(&r200->radeon); 568 uint32_t dwords = atom->check(ctx, atom); 569 int i = atom->idx; 570 radeonTexObj *t = r200->state.texture.unit[i].texobj; 571 572 if (!r200->state.texture.unit[i].unitneeded && !(dwords <= atom->cmd_size)) 573 dwords -= 4; 574 BEGIN_BATCH(dwords); 575 576 OUT_BATCH(CP_PACKET0(R200_PP_TXFILTER_0 + (32 * i), 7)); 577 OUT_BATCH_TABLE((atom->cmd + 1), 8); 578 579 if (dwords > atom->cmd_size) { 580 OUT_BATCH(CP_PACKET0(R200_PP_TXOFFSET_0 + (24 * i), 0)); 581 if (t->mt && !t->image_override) { 582 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, 583 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); 584 } else { 585 if (t->bo) 586 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, 587 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); 588 } 589 } 590 END_BATCH(); 591 } 592 593 static void cube_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) 594 { 595 r200ContextPtr r200 = R200_CONTEXT(ctx); 596 BATCH_LOCALS(&r200->radeon); 597 uint32_t dwords = atom->check(ctx, atom); 598 int i = atom->idx, j; 599 radeonTexObj *t = r200->state.texture.unit[i].texobj; 600 radeon_mipmap_level *lvl; 601 if (!(t && !t->image_override)) 602 dwords = 2; 603 604 BEGIN_BATCH(dwords); 605 OUT_BATCH_TABLE(atom->cmd, 2); 606 607 if (t && !t->image_override) { 608 lvl = &t->mt->levels[0]; 609 for (j = 1; j <= 5; j++) { 610 OUT_BATCH(CP_PACKET0(R200_PP_CUBIC_OFFSET_F1_0 + (24*i) + (4 * (j-1)), 0)); 611 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset, 612 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); 613 } 614 } 615 END_BATCH(); 616 } 617 618 /* Initialize the context's hardware state. 619 */ 620 void r200InitState( r200ContextPtr rmesa ) 621 { 622 struct gl_context *ctx = &rmesa->radeon.glCtx; 623 GLuint i; 624 625 rmesa->radeon.Fallback = 0; 626 627 rmesa->radeon.hw.max_state_size = 0; 628 629 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \ 630 do { \ 631 rmesa->hw.ATOM.cmd_size = SZ; \ 632 rmesa->hw.ATOM.cmd = (GLuint *) calloc(SZ, sizeof(int)); \ 633 rmesa->hw.ATOM.lastcmd = (GLuint *) calloc(SZ, sizeof(int)); \ 634 rmesa->hw.ATOM.name = NM; \ 635 rmesa->hw.ATOM.idx = IDX; \ 636 if (check_##CHK != check_never) { \ 637 rmesa->hw.ATOM.check = check_##CHK; \ 638 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \ 639 } else { \ 640 rmesa->hw.ATOM.check = NULL; \ 641 } \ 642 rmesa->hw.ATOM.dirty = GL_FALSE; \ 643 } while (0) 644 645 646 /* Allocate state buffers: 647 */ 648 ALLOC_STATE( ctx, always_add4, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 ); 649 650 rmesa->hw.ctx.emit = ctx_emit_cs; 651 rmesa->hw.ctx.check = check_always_ctx; 652 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 ); 653 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 ); 654 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 ); 655 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 ); 656 ALLOC_STATE( vtx, always, VTX_STATE_SIZE, "VTX/vertex", 0 ); 657 ALLOC_STATE( vap, always, VAP_STATE_SIZE, "VAP/vap", 0 ); 658 ALLOC_STATE( vte, always, VTE_STATE_SIZE, "VTE/vte", 0 ); 659 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 ); 660 ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 ); 661 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 ); 662 ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 ); 663 { 664 int state_size = TEX_STATE_SIZE_NEWDRM; 665 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) { 666 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */ 667 ALLOC_STATE( tex[0], tex_pair_mm, state_size, "TEX/tex-0", 0 ); 668 ALLOC_STATE( tex[1], tex_pair_mm, state_size, "TEX/tex-1", 1 ); 669 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 ); 670 } 671 else { 672 ALLOC_STATE( tex[0], tex_mm, state_size, "TEX/tex-0", 0 ); 673 ALLOC_STATE( tex[1], tex_mm, state_size, "TEX/tex-1", 1 ); 674 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 ); 675 } 676 ALLOC_STATE( tex[2], tex_mm, state_size, "TEX/tex-2", 2 ); 677 ALLOC_STATE( tex[3], tex_mm, state_size, "TEX/tex-3", 3 ); 678 ALLOC_STATE( tex[4], tex_mm, state_size, "TEX/tex-4", 4 ); 679 ALLOC_STATE( tex[5], tex_mm, state_size, "TEX/tex-5", 5 ); 680 ALLOC_STATE( atf, afs, ATF_STATE_SIZE, "ATF/tfactor", 0 ); 681 ALLOC_STATE( afs[0], afs_pass1, AFS_STATE_SIZE, "AFS/afsinst-0", 0 ); 682 ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 ); 683 } 684 685 ALLOC_STATE( stp, polygon_stipple, STP_STATE_SIZE, "STP/stp", 0 ); 686 687 for (i = 0; i < 6; i++) 688 rmesa->hw.tex[i].emit = tex_emit_mm; 689 ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 ); 690 ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 ); 691 ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 ); 692 ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 ); 693 ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 ); 694 ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 ); 695 for (i = 0; i < 6; i++) { 696 rmesa->hw.cube[i].emit = cube_emit_cs; 697 rmesa->hw.cube[i].check = check_tex_cube_cs; 698 } 699 700 ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 ); 701 ALLOC_STATE( vpi[0], tcl_vp_add4, VPI_STATE_SIZE, "VP/vertexprog-0", 0 ); 702 ALLOC_STATE( vpi[1], tcl_vp_size_add4, VPI_STATE_SIZE, "VP/vertexprog-1", 1 ); 703 ALLOC_STATE( vpp[0], tcl_vp_add4, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 ); 704 ALLOC_STATE( vpp[1], tcl_vpp_size_add4, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 ); 705 706 /* FIXME: this atom has two commands, we need only one (ucp_vert_blend) for vp */ 707 ALLOC_STATE( tcl, tcl_or_vp, TCL_STATE_SIZE, "TCL/tcl", 0 ); 708 ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 ); 709 ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 ); 710 ALLOC_STATE( mtl[0], tcl_lighting_add6, MTL_STATE_SIZE, "MTL0/material0", 0 ); 711 ALLOC_STATE( mtl[1], tcl_lighting_add6, MTL_STATE_SIZE, "MTL1/material1", 1 ); 712 ALLOC_STATE( grd, tcl_or_vp_add2, GRD_STATE_SIZE, "GRD/guard-band", 0 ); 713 ALLOC_STATE( fog, tcl_fog_add4, FOG_STATE_SIZE, "FOG/fog", 0 ); 714 ALLOC_STATE( glt, tcl_lighting_add4, GLT_STATE_SIZE, "GLT/light-global", 0 ); 715 ALLOC_STATE( eye, tcl_lighting_add4, EYE_STATE_SIZE, "EYE/eye-vector", 0 ); 716 ALLOC_STATE( mat[R200_MTX_MV], tcl_add4, MAT_STATE_SIZE, "MAT/modelview", 0 ); 717 ALLOC_STATE( mat[R200_MTX_IMV], tcl_add4, MAT_STATE_SIZE, "MAT/it-modelview", 0 ); 718 ALLOC_STATE( mat[R200_MTX_MVP], tcl_add4, MAT_STATE_SIZE, "MAT/modelproject", 0 ); 719 ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat0", 0 ); 720 ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat1", 1 ); 721 ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat2", 2 ); 722 ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat3", 3 ); 723 ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat4", 4 ); 724 ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat5", 5 ); 725 ALLOC_STATE( ucp[0], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-0", 0 ); 726 ALLOC_STATE( ucp[1], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-1", 1 ); 727 ALLOC_STATE( ucp[2], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-2", 2 ); 728 ALLOC_STATE( ucp[3], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-3", 3 ); 729 ALLOC_STATE( ucp[4], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-4", 4 ); 730 ALLOC_STATE( ucp[5], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-5", 5 ); 731 ALLOC_STATE( lit[0], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-0", 0 ); 732 ALLOC_STATE( lit[1], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-1", 1 ); 733 ALLOC_STATE( lit[2], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-2", 2 ); 734 ALLOC_STATE( lit[3], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-3", 3 ); 735 ALLOC_STATE( lit[4], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-4", 4 ); 736 ALLOC_STATE( lit[5], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-5", 5 ); 737 ALLOC_STATE( lit[6], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-6", 6 ); 738 ALLOC_STATE( lit[7], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-7", 7 ); 739 ALLOC_STATE( sci, rrb, SCI_STATE_SIZE, "SCI/scissor", 0 ); 740 ALLOC_STATE( pix[0], pix_zero, PIX_STATE_SIZE, "PIX/pixstage-0", 0 ); 741 ALLOC_STATE( pix[1], texenv, PIX_STATE_SIZE, "PIX/pixstage-1", 1 ); 742 ALLOC_STATE( pix[2], texenv, PIX_STATE_SIZE, "PIX/pixstage-2", 2 ); 743 ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 ); 744 ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 ); 745 ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 ); 746 ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 ); 747 ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 ); 748 ALLOC_STATE( ptp, tcl_add8, PTP_STATE_SIZE, "PTP/pointparams", 0 ); 749 750 r200SetUpAtomList( rmesa ); 751 752 /* Fill in the packet headers: 753 */ 754 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC); 755 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL); 756 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH); 757 rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(rmesa, R200_EMIT_RB3D_BLENDCOLOR); 758 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN); 759 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH); 760 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK); 761 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE); 762 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL); 763 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC); 764 rmesa->hw.cst.cmd[CST_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CNTL_X); 765 rmesa->hw.cst.cmd[CST_CMD_1] = cmdpkt(rmesa, R200_EMIT_RB3D_DEPTHXY_OFFSET); 766 rmesa->hw.cst.cmd[CST_CMD_2] = cmdpkt(rmesa, R200_EMIT_RE_AUX_SCISSOR_CNTL); 767 rmesa->hw.cst.cmd[CST_CMD_4] = cmdpkt(rmesa, R200_EMIT_SE_VAP_CNTL_STATUS); 768 rmesa->hw.cst.cmd[CST_CMD_5] = cmdpkt(rmesa, R200_EMIT_RE_POINTSIZE); 769 rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(rmesa, R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0); 770 rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TAM_DEBUG3); 771 rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(rmesa, R200_EMIT_TFACTOR_0); 772 rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(rmesa, R200_EMIT_ATF_TFACTOR); 773 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_0); 774 rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0); 775 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_1); 776 rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1); 777 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_2); 778 rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2); 779 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_3); 780 rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3); 781 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_4); 782 rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4); 783 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_5); 784 rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5); 785 rmesa->hw.afs[0].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_0); 786 rmesa->hw.afs[1].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_1); 787 rmesa->hw.pvs.cmd[PVS_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_PVS_CNTL); 788 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_0); 789 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_0); 790 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_1); 791 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_1); 792 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_2); 793 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_2); 794 rmesa->hw.cube[3].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_3); 795 rmesa->hw.cube[3].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_3); 796 rmesa->hw.cube[4].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_4); 797 rmesa->hw.cube[4].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_4); 798 rmesa->hw.cube[5].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_5); 799 rmesa->hw.cube[5].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_5); 800 rmesa->hw.pix[0].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_0); 801 rmesa->hw.pix[1].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_1); 802 rmesa->hw.pix[2].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_2); 803 rmesa->hw.pix[3].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_3); 804 rmesa->hw.pix[4].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_4); 805 rmesa->hw.pix[5].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_5); 806 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR); 807 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_LIGHT_MODEL_CTL_0); 808 rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(rmesa, R200_EMIT_TCL_UCP_VERT_BLEND_CTL); 809 rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(rmesa, R200_EMIT_TEX_PROC_CTL_2); 810 rmesa->hw.msl.cmd[MSL_CMD_0] = cmdpkt(rmesa, R200_EMIT_MATRIX_SELECT_0); 811 rmesa->hw.vap.cmd[VAP_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_CTL); 812 rmesa->hw.vtx.cmd[VTX_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTX_FMT_0); 813 rmesa->hw.vtx.cmd[VTX_CMD_1] = cmdpkt(rmesa, R200_EMIT_OUTPUT_VTX_COMP_SEL); 814 rmesa->hw.vtx.cmd[VTX_CMD_2] = cmdpkt(rmesa, R200_EMIT_SE_VTX_STATE_CNTL); 815 rmesa->hw.vte.cmd[VTE_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTE_CNTL); 816 rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TRI_PERF_CNTL); 817 rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_POINT_SPRITE_CNTL); 818 819 rmesa->hw.sci.cmd[SCI_CMD_1] = CP_PACKET0(R200_RE_TOP_LEFT, 0); 820 rmesa->hw.sci.cmd[SCI_CMD_2] = CP_PACKET0(R200_RE_WIDTH_HEIGHT, 0); 821 822 rmesa->hw.stp.cmd[STP_CMD_0] = CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0); 823 rmesa->hw.stp.cmd[STP_DATA_0] = 0; 824 rmesa->hw.stp.cmd[STP_CMD_1] = CP_PACKET0_ONE(RADEON_RE_STIPPLE_DATA, 31); 825 826 rmesa->hw.mtl[0].emit = mtl_emit; 827 rmesa->hw.mtl[1].emit = mtl_emit; 828 829 rmesa->hw.vpi[0].emit = veclinear_emit; 830 rmesa->hw.vpi[1].emit = veclinear_emit; 831 rmesa->hw.vpp[0].emit = veclinear_emit; 832 rmesa->hw.vpp[1].emit = veclinear_emit; 833 834 rmesa->hw.grd.emit = scl_emit; 835 rmesa->hw.fog.emit = vec_emit; 836 rmesa->hw.glt.emit = vec_emit; 837 rmesa->hw.eye.emit = vec_emit; 838 839 for (i = R200_MTX_MV; i <= R200_MTX_TEX5; i++) 840 rmesa->hw.mat[i].emit = vec_emit; 841 842 for (i = 0; i < 8; i++) 843 rmesa->hw.lit[i].emit = lit_emit; 844 845 for (i = 0; i < 6; i++) 846 rmesa->hw.ucp[i].emit = vec_emit; 847 848 rmesa->hw.ptp.emit = ptp_emit; 849 850 rmesa->hw.mtl[0].cmd[MTL_CMD_0] = 851 cmdvec( R200_VS_MAT_0_EMISS, 1, 16 ); 852 rmesa->hw.mtl[0].cmd[MTL_CMD_1] = 853 cmdscl2( R200_SS_MAT_0_SHININESS, 1, 1 ); 854 rmesa->hw.mtl[1].cmd[MTL_CMD_0] = 855 cmdvec( R200_VS_MAT_1_EMISS, 1, 16 ); 856 rmesa->hw.mtl[1].cmd[MTL_CMD_1] = 857 cmdscl2( R200_SS_MAT_1_SHININESS, 1, 1 ); 858 859 rmesa->hw.vpi[0].cmd[VPI_CMD_0] = 860 cmdveclinear( R200_PVS_PROG0, 64 ); 861 rmesa->hw.vpi[1].cmd[VPI_CMD_0] = 862 cmdveclinear( R200_PVS_PROG1, 64 ); 863 rmesa->hw.vpp[0].cmd[VPP_CMD_0] = 864 cmdveclinear( R200_PVS_PARAM0, 96 ); 865 rmesa->hw.vpp[1].cmd[VPP_CMD_0] = 866 cmdveclinear( R200_PVS_PARAM1, 96 ); 867 868 rmesa->hw.grd.cmd[GRD_CMD_0] = 869 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 ); 870 rmesa->hw.fog.cmd[FOG_CMD_0] = 871 cmdvec( R200_VS_FOG_PARAM_ADDR, 1, 4 ); 872 rmesa->hw.glt.cmd[GLT_CMD_0] = 873 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR, 1, 4 ); 874 rmesa->hw.eye.cmd[EYE_CMD_0] = 875 cmdvec( R200_VS_EYE_VECTOR_ADDR, 1, 4 ); 876 877 rmesa->hw.mat[R200_MTX_MV].cmd[MAT_CMD_0] = 878 cmdvec( R200_VS_MATRIX_0_MV, 1, 16); 879 rmesa->hw.mat[R200_MTX_IMV].cmd[MAT_CMD_0] = 880 cmdvec( R200_VS_MATRIX_1_INV_MV, 1, 16); 881 rmesa->hw.mat[R200_MTX_MVP].cmd[MAT_CMD_0] = 882 cmdvec( R200_VS_MATRIX_2_MVP, 1, 16); 883 rmesa->hw.mat[R200_MTX_TEX0].cmd[MAT_CMD_0] = 884 cmdvec( R200_VS_MATRIX_3_TEX0, 1, 16); 885 rmesa->hw.mat[R200_MTX_TEX1].cmd[MAT_CMD_0] = 886 cmdvec( R200_VS_MATRIX_4_TEX1, 1, 16); 887 rmesa->hw.mat[R200_MTX_TEX2].cmd[MAT_CMD_0] = 888 cmdvec( R200_VS_MATRIX_5_TEX2, 1, 16); 889 rmesa->hw.mat[R200_MTX_TEX3].cmd[MAT_CMD_0] = 890 cmdvec( R200_VS_MATRIX_6_TEX3, 1, 16); 891 rmesa->hw.mat[R200_MTX_TEX4].cmd[MAT_CMD_0] = 892 cmdvec( R200_VS_MATRIX_7_TEX4, 1, 16); 893 rmesa->hw.mat[R200_MTX_TEX5].cmd[MAT_CMD_0] = 894 cmdvec( R200_VS_MATRIX_8_TEX5, 1, 16); 895 896 for (i = 0 ; i < 8; i++) { 897 rmesa->hw.lit[i].cmd[LIT_CMD_0] = 898 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 ); 899 rmesa->hw.lit[i].cmd[LIT_CMD_1] = 900 cmdscl( R200_SS_LIGHT_DCD_ADDR + i, 8, 7 ); 901 } 902 903 for (i = 0 ; i < 6; i++) { 904 rmesa->hw.ucp[i].cmd[UCP_CMD_0] = 905 cmdvec( R200_VS_UCP_ADDR + i, 1, 4 ); 906 } 907 908 rmesa->hw.ptp.cmd[PTP_CMD_0] = 909 cmdvec( R200_VS_PNT_SPRITE_VPORT_SCALE, 1, 4 ); 910 rmesa->hw.ptp.cmd[PTP_CMD_1] = 911 cmdvec( R200_VS_PNT_SPRITE_ATT_CONST, 1, 12 ); 912 913 /* Initial Harware state: 914 */ 915 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (R200_ALPHA_TEST_PASS 916 /* | R200_RIGHT_HAND_CUBE_OGL*/); 917 918 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (R200_FOG_VERTEX | 919 R200_FOG_USE_SPEC_ALPHA); 920 921 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000; 922 923 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP | 924 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | 925 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT)); 926 927 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000; 928 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP | 929 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | 930 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT)); 931 rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP | 932 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | 933 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT)); 934 935 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] = 936 rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation; 937 938 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] = 939 ((rmesa->radeon.radeonScreen->depthPitch & 940 R200_DEPTHPITCH_MASK) | 941 R200_DEPTH_ENDIAN_NO_SWAP); 942 943 if (rmesa->using_hyperz) 944 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= R200_DEPTH_HYPERZ; 945 946 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (R200_Z_TEST_LESS | 947 R200_STENCIL_TEST_ALWAYS | 948 R200_STENCIL_FAIL_KEEP | 949 R200_STENCIL_ZPASS_KEEP | 950 R200_STENCIL_ZFAIL_KEEP | 951 R200_Z_WRITE_ENABLE); 952 953 if (rmesa->using_hyperz) { 954 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE | 955 R200_Z_DECOMPRESSION_ENABLE; 956 /* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) 957 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/ 958 } 959 960 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE 961 | R200_TEX_BLEND_0_ENABLE); 962 963 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) { 964 case DRI_CONF_DITHER_XERRORDIFFRESET: 965 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT; 966 break; 967 case DRI_CONF_DITHER_ORDERED: 968 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE; 969 break; 970 } 971 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) == 972 DRI_CONF_ROUND_ROUND ) 973 rmesa->radeon.state.color.roundEnable = R200_ROUND_ENABLE; 974 else 975 rmesa->radeon.state.color.roundEnable = 0; 976 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) == 977 DRI_CONF_COLOR_REDUCTION_DITHER ) 978 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE; 979 else 980 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable; 981 982 rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK * 983 driQueryOptionf (&rmesa->radeon.optionCache,"texture_blend_quality"); 984 rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0; 985 986 rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW | 987 R200_BFACE_SOLID | 988 R200_FFACE_SOLID | 989 R200_FLAT_SHADE_VTX_LAST | 990 R200_DIFFUSE_SHADE_GOURAUD | 991 R200_ALPHA_SHADE_GOURAUD | 992 R200_SPECULAR_SHADE_GOURAUD | 993 R200_FOG_SHADE_GOURAUD | 994 R200_DISC_FOG_SHADE_GOURAUD | 995 R200_VTX_PIX_CENTER_OGL | 996 R200_ROUND_MODE_TRUNC | 997 R200_ROUND_PREC_8TH_PIX); 998 999 rmesa->hw.set.cmd[SET_RE_CNTL] = (R200_PERSPECTIVE_ENABLE | 1000 R200_SCISSOR_ENABLE); 1001 1002 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff); 1003 1004 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] = 1005 ((0 << R200_LINE_CURRENT_PTR_SHIFT) | 1006 (1 << R200_LINE_CURRENT_COUNT_SHIFT)); 1007 1008 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4); 1009 1010 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] = 1011 ((0x00 << R200_STENCIL_REF_SHIFT) | 1012 (0xff << R200_STENCIL_MASK_SHIFT) | 1013 (0xff << R200_STENCIL_WRITEMASK_SHIFT)); 1014 1015 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = R200_ROP_COPY; 1016 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff; 1017 1018 rmesa->hw.tam.cmd[TAM_DEBUG3] = 0; 1019 1020 rmesa->hw.msc.cmd[MSC_RE_MISC] = 1021 ((0 << R200_STIPPLE_X_OFFSET_SHIFT) | 1022 (0 << R200_STIPPLE_Y_OFFSET_SHIFT) | 1023 R200_STIPPLE_BIG_BIT_ORDER); 1024 1025 1026 rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0; 1027 rmesa->hw.cst.cmd[CST_RB3D_DEPTHXY_OFFSET] = 0; 1028 rmesa->hw.cst.cmd[CST_RE_AUX_SCISSOR_CNTL] = 0x0; 1029 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] = 1030 #ifdef MESA_BIG_ENDIAN 1031 R200_VC_32BIT_SWAP; 1032 #else 1033 R200_VC_NO_SWAP; 1034 #endif 1035 1036 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { 1037 /* Bypass TCL */ 1038 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8); 1039 } 1040 1041 rmesa->hw.cst.cmd[CST_RE_POINTSIZE] = 1042 (((GLuint)(ctx->Const.MaxPointSize * 16.0)) << R200_MAXPOINTSIZE_SHIFT) | 0x10; 1043 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_0] = 1044 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT); 1045 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_1] = 1046 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT) | 1047 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT); 1048 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_2] = 1049 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT) | 1050 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT) | 1051 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT) | 1052 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT); 1053 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_3] = 1054 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT) | 1055 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT); 1056 1057 1058 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000; 1059 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000; 1060 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000; 1061 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000; 1062 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000; 1063 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000; 1064 1065 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) { 1066 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = R200_BORDER_MODE_OGL; 1067 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] = 1068 ((i << R200_TXFORMAT_ST_ROUTE_SHIFT) | /* <-- note i */ 1069 (2 << R200_TXFORMAT_WIDTH_SHIFT) | 1070 (2 << R200_TXFORMAT_HEIGHT_SHIFT)); 1071 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0; 1072 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] = 1073 (/* R200_TEXCOORD_PROJ | */ 1074 R200_LOD_BIAS_CORRECTION); /* Small default bias */ 1075 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] = 1076 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 1077 rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0; 1078 rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0; 1079 1080 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0; 1081 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] = 1082 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 1083 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] = 1084 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 1085 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] = 1086 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 1087 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] = 1088 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 1089 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] = 1090 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 1091 1092 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] = 1093 (R200_TXC_ARG_A_ZERO | 1094 R200_TXC_ARG_B_ZERO | 1095 R200_TXC_ARG_C_DIFFUSE_COLOR | 1096 R200_TXC_OP_MADD); 1097 1098 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND2] = 1099 ((i << R200_TXC_TFACTOR_SEL_SHIFT) | 1100 R200_TXC_SCALE_1X | 1101 R200_TXC_CLAMP_0_1 | 1102 R200_TXC_OUTPUT_REG_R0); 1103 1104 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND] = 1105 (R200_TXA_ARG_A_ZERO | 1106 R200_TXA_ARG_B_ZERO | 1107 R200_TXA_ARG_C_DIFFUSE_ALPHA | 1108 R200_TXA_OP_MADD); 1109 1110 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND2] = 1111 ((i << R200_TXA_TFACTOR_SEL_SHIFT) | 1112 R200_TXA_SCALE_1X | 1113 R200_TXA_CLAMP_0_1 | 1114 R200_TXA_OUTPUT_REG_R0); 1115 } 1116 1117 rmesa->hw.tf.cmd[TF_TFACTOR_0] = 0; 1118 rmesa->hw.tf.cmd[TF_TFACTOR_1] = 0; 1119 rmesa->hw.tf.cmd[TF_TFACTOR_2] = 0; 1120 rmesa->hw.tf.cmd[TF_TFACTOR_3] = 0; 1121 rmesa->hw.tf.cmd[TF_TFACTOR_4] = 0; 1122 rmesa->hw.tf.cmd[TF_TFACTOR_5] = 0; 1123 1124 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] = 1125 (R200_VAP_TCL_ENABLE | 1126 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT)); 1127 1128 rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] = 1129 (R200_VPORT_X_SCALE_ENA | 1130 R200_VPORT_Y_SCALE_ENA | 1131 R200_VPORT_Z_SCALE_ENA | 1132 R200_VPORT_X_OFFSET_ENA | 1133 R200_VPORT_Y_OFFSET_ENA | 1134 R200_VPORT_Z_OFFSET_ENA | 1135 /* FIXME: Turn on for tex rect only */ 1136 R200_VTX_ST_DENORMALIZED | 1137 R200_VTX_W0_FMT); 1138 1139 1140 rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = 0; 1141 rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = 0; 1142 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] = 1143 ((R200_VTX_Z0 | R200_VTX_W0 | 1144 (R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT))); 1145 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] = 0; 1146 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = (R200_OUTPUT_XYZW); 1147 rmesa->hw.vtx.cmd[VTX_STATE_CNTL] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE; 1148 1149 1150 /* Matrix selection */ 1151 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_0] = 1152 (R200_MTX_MV << R200_MODELVIEW_0_SHIFT); 1153 1154 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_1] = 1155 (R200_MTX_IMV << R200_IT_MODELVIEW_0_SHIFT); 1156 1157 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_2] = 1158 (R200_MTX_MVP << R200_MODELPROJECT_0_SHIFT); 1159 1160 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_3] = 1161 ((R200_MTX_TEX0 << R200_TEXMAT_0_SHIFT) | 1162 (R200_MTX_TEX1 << R200_TEXMAT_1_SHIFT) | 1163 (R200_MTX_TEX2 << R200_TEXMAT_2_SHIFT) | 1164 (R200_MTX_TEX3 << R200_TEXMAT_3_SHIFT)); 1165 1166 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_4] = 1167 ((R200_MTX_TEX4 << R200_TEXMAT_4_SHIFT) | 1168 (R200_MTX_TEX5 << R200_TEXMAT_5_SHIFT)); 1169 1170 1171 /* General TCL state */ 1172 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] = 1173 (R200_SPECULAR_LIGHTS | 1174 R200_DIFFUSE_SPECULAR_COMBINE | 1175 R200_LOCAL_LIGHT_VEC_GL | 1176 R200_LM0_SOURCE_MATERIAL_0 << R200_FRONT_SHININESS_SOURCE_SHIFT | 1177 R200_LM0_SOURCE_MATERIAL_1 << R200_BACK_SHININESS_SOURCE_SHIFT); 1178 1179 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] = 1180 ((R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) | 1181 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_AMBIENT_SOURCE_SHIFT) | 1182 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT) | 1183 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_SPECULAR_SOURCE_SHIFT) | 1184 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_EMISSIVE_SOURCE_SHIFT) | 1185 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_AMBIENT_SOURCE_SHIFT) | 1186 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_DIFFUSE_SOURCE_SHIFT) | 1187 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_SPECULAR_SOURCE_SHIFT)); 1188 1189 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_0] = 0; /* filled in via callbacks */ 1190 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_1] = 0; 1191 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_2] = 0; 1192 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_3] = 0; 1193 1194 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = 1195 (R200_UCP_IN_CLIP_SPACE | 1196 R200_CULL_FRONT_IS_CCW); 1197 1198 /* Texgen/Texmat state */ 1199 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = 0x00ffffff; 1200 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] = 1201 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT) | 1202 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT) | 1203 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT) | 1204 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT) | 1205 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT) | 1206 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT)); 1207 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0; 1208 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] = 1209 ((0 << R200_TEXGEN_0_INPUT_SHIFT) | 1210 (1 << R200_TEXGEN_1_INPUT_SHIFT) | 1211 (2 << R200_TEXGEN_2_INPUT_SHIFT) | 1212 (3 << R200_TEXGEN_3_INPUT_SHIFT) | 1213 (4 << R200_TEXGEN_4_INPUT_SHIFT) | 1214 (5 << R200_TEXGEN_5_INPUT_SHIFT)); 1215 rmesa->hw.tcg.cmd[TCG_TEX_CYL_WRAP_CTL] = 0; 1216 1217 1218 for (i = 0 ; i < 8; i++) { 1219 struct gl_light *l = &ctx->Light.Light[i]; 1220 GLenum p = GL_LIGHT0 + i; 1221 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX; 1222 1223 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient ); 1224 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse ); 1225 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular ); 1226 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL ); 1227 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL ); 1228 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent ); 1229 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff ); 1230 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION, 1231 &l->ConstantAttenuation ); 1232 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION, 1233 &l->LinearAttenuation ); 1234 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION, 1235 &l->QuadraticAttenuation ); 1236 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0; 1237 } 1238 1239 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT, 1240 ctx->Light.Model.Ambient ); 1241 1242 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx ); 1243 1244 for (i = 0 ; i < 6; i++) { 1245 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL ); 1246 } 1247 1248 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL ); 1249 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density ); 1250 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start ); 1251 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End ); 1252 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color ); 1253 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL ); 1254 1255 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE; 1256 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE; 1257 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE; 1258 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE; 1259 1260 rmesa->hw.eye.cmd[EYE_X] = 0; 1261 rmesa->hw.eye.cmd[EYE_Y] = 0; 1262 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE; 1263 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE; 1264 1265 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] = 1266 R200_PS_SE_SEL_STATE | R200_PS_MULT_CONST; 1267 1268 /* ptp_eye is presumably used to calculate the attenuation wrt a different 1269 location? In any case, since point attenuation triggers _needeyecoords, 1270 it is constant. Probably ignored as long as R200_PS_USE_MODEL_EYE_VEC 1271 isn't set */ 1272 rmesa->hw.ptp.cmd[PTP_EYE_X] = 0; 1273 rmesa->hw.ptp.cmd[PTP_EYE_Y] = 0; 1274 rmesa->hw.ptp.cmd[PTP_EYE_Z] = IEEE_ONE | 0x80000000; /* -1.0 */ 1275 rmesa->hw.ptp.cmd[PTP_EYE_3] = 0; 1276 /* no idea what the ptp_vport_scale values are good for, except the 1277 PTSIZE one - hopefully doesn't matter */ 1278 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_0] = IEEE_ONE; 1279 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_1] = IEEE_ONE; 1280 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_PTSIZE] = IEEE_ONE; 1281 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_3] = IEEE_ONE; 1282 rmesa->hw.ptp.cmd[PTP_ATT_CONST_QUAD] = 0; 1283 rmesa->hw.ptp.cmd[PTP_ATT_CONST_LIN] = 0; 1284 rmesa->hw.ptp.cmd[PTP_ATT_CONST_CON] = IEEE_ONE; 1285 rmesa->hw.ptp.cmd[PTP_ATT_CONST_3] = 0; 1286 rmesa->hw.ptp.cmd[PTP_CLAMP_MIN] = IEEE_ONE; 1287 rmesa->hw.ptp.cmd[PTP_CLAMP_MAX] = 0x44ffe000; /* 2047 */ 1288 rmesa->hw.ptp.cmd[PTP_CLAMP_2] = 0; 1289 rmesa->hw.ptp.cmd[PTP_CLAMP_3] = 0; 1290 1291 r200LightingSpaceChange( ctx ); 1292 1293 radeon_init_query_stateobj(&rmesa->radeon, R200_QUERYOBJ_CMDSIZE); 1294 rmesa->radeon.query.queryobj.cmd[R200_QUERYOBJ_CMD_0] = CP_PACKET0(RADEON_RB3D_ZPASS_DATA, 0); 1295 rmesa->radeon.query.queryobj.cmd[R200_QUERYOBJ_DATA_0] = 0; 1296 1297 rmesa->radeon.hw.all_dirty = GL_TRUE; 1298 1299 rcommonInitCmdBuf(&rmesa->radeon); 1300 } 1301
