1 #ifndef COMMON_CMDBUF_H 2 #define COMMON_CMDBUF_H 3 4 GLboolean rcommonEnsureCmdBufSpace(radeonContextPtr rmesa, int dwords, const char *caller); 5 int rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller); 6 int rcommonFlushCmdBufLocked(radeonContextPtr rmesa, const char *caller); 7 void rcommonInitCmdBuf(radeonContextPtr rmesa); 8 void rcommonDestroyCmdBuf(radeonContextPtr rmesa); 9 10 void rcommonBeginBatch(radeonContextPtr rmesa, 11 int n, 12 const char *file, 13 const char *function, 14 int line); 15 16 /* +r6/r7 : code here moved */ 17 18 #define CP_PACKET2 (2 << 30) 19 #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) 20 #define CP_PACKET0_ONE(reg, n) (RADEON_CP_PACKET0 | RADEON_CP_PACKET0_ONE_REG_WR | ((n)<<16) | ((reg)>>2)) 21 #define CP_PACKET3(pkt, n) (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 22 23 /** 24 * Every function writing to the command buffer needs to declare this 25 * to get the necessary local variables. 26 */ 27 #define BATCH_LOCALS(rmesa) \ 28 const radeonContextPtr b_l_rmesa = rmesa 29 30 /** 31 * Prepare writing n dwords to the command buffer. Does not cause automatic 32 * state emits. 33 */ 34 #define BEGIN_BATCH(n) rcommonBeginBatch(b_l_rmesa, n, __FILE__, __func__, __LINE__) 35 36 /** 37 * Write one dword to the command buffer. 38 */ 39 #define OUT_BATCH(data) \ 40 do { \ 41 radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, data);\ 42 } while(0) 43 44 /** 45 * Write a relocated dword to the command buffer. 46 */ 47 #define OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags) \ 48 do { \ 49 int __offset = (offset); \ 50 if (0 && __offset) { \ 51 fprintf(stderr, "(%s:%s:%d) offset : %d\n", \ 52 __FILE__, __func__, __LINE__, __offset); \ 53 } \ 54 radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, __offset); \ 55 radeon_cs_write_reloc(b_l_rmesa->cmdbuf.cs, \ 56 bo, rd, wd, flags); \ 57 } while(0) 58 59 60 /** 61 * Write n dwords from ptr to the command buffer. 62 */ 63 #define OUT_BATCH_TABLE(ptr,n) \ 64 do { \ 65 radeon_cs_write_table(b_l_rmesa->cmdbuf.cs, (ptr), (n));\ 66 } while(0) 67 68 /** 69 * Finish writing dwords to the command buffer. 70 * The number of (direct or indirect) OUT_BATCH calls between the previous 71 * BEGIN_BATCH and END_BATCH must match the number specified at BEGIN_BATCH time. 72 */ 73 #define END_BATCH() \ 74 do { \ 75 radeon_cs_end(b_l_rmesa->cmdbuf.cs, __FILE__, __func__, __LINE__);\ 76 } while(0) 77 78 /** 79 * After the last END_BATCH() of rendering, this indicates that flushing 80 * the command buffer now is okay. 81 */ 82 #define COMMIT_BATCH() \ 83 do { \ 84 } while(0) 85 86 87 /** Single register write to command buffer; requires 2 dwords. */ 88 #define OUT_BATCH_REGVAL(reg, val) \ 89 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), 1)); \ 90 OUT_BATCH((val)) 91 92 /** Continuous register range write to command buffer; requires 1 dword, 93 * expects count dwords afterwards for register contents. */ 94 #define OUT_BATCH_REGSEQ(reg, count) \ 95 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count))) 96 97 /* +r6/r7 : code here moved */ 98 99 /* Fire the buffered vertices no matter what. 100 */ 101 static inline void radeon_firevertices(radeonContextPtr radeon) 102 { 103 if (radeon->cmdbuf.cs->cdw || radeon->dma.flush ) 104 radeon->glCtx.Driver.Flush(&radeon->glCtx); /* +r6/r7 */ 105 } 106 107 #endif 108
