HomeSort by relevance Sort by last modified time
    Searched refs:CTX_PP_CNTL (Results 1 - 10 of 10) sorted by null

  /external/mesa3d/src/mesa/drivers/dri/r200/
r200_fragshader.c 341 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~(R200_MULTI_PASS_ENABLE |
351 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= shader->numArithInstr[0] == 8 ?
355 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_MULTI_PASS_ENABLE;
356 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= shader->numArithInstr[1] == 8 ?
388 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg;
407 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg;
469 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg;
496 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg;
r200_texstate.c 908 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~(R200_TEX_BLEND_ENABLE_MASK | R200_MULTI_PASS_ENABLE);
909 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= rmesa->state.envneeded << R200_TEX_BLEND_0_ENABLE_SHIFT;
952 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~(R200_TEX_0_ENABLE << unit);
    [all...]
r200_state.c 765 uint32_t p = rmesa->hw.ctx.cmd[CTX_PP_CNTL];
814 if ( rmesa->hw.ctx.cmd[CTX_PP_CNTL] != p ) {
816 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = p;
    [all...]
r200_context.h 106 #define CTX_PP_CNTL 9
r200_state_init.c 506 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
    [all...]
  /external/mesa3d/src/mesa/drivers/dri/radeon/
radeon_state.c 568 uint32_t p = rmesa->hw.ctx.cmd[CTX_PP_CNTL];
631 if ( rmesa->hw.ctx.cmd[CTX_PP_CNTL] != p ) {
633 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = p;
    [all...]
radeon_ioctl.c 103 OUT_BATCH(rmesa->hw.ctx.cmd[CTX_PP_CNTL] | RADEON_SCISSOR_ENABLE);
114 OUT_BATCH(rmesa->hw.ctx.cmd[CTX_PP_CNTL] & ~RADEON_SCISSOR_ENABLE);
radeon_context.h 97 #define CTX_PP_CNTL 9
radeon_texstate.c 1004 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |=
    [all...]
radeon_state_init.c 389 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
703 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE |
    [all...]

Completed in 57 milliseconds