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    Searched refs:CTX_RB3D_CNTL (Results 1 - 6 of 6) sorted by null

  /external/mesa3d/src/mesa/drivers/dri/radeon/
radeon_state_init.c 334 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
336 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
340 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
344 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444;
348 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555;
390 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
706 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE |
711 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT;
714 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE;
724 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE
    [all...]
radeon_state.c 146 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_ROP_ENABLE;
148 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ROP_ENABLE;
    [all...]
radeon_context.h 98 #define CTX_RB3D_CNTL 10
  /external/mesa3d/src/mesa/drivers/dri/r200/
r200_state.c 208 GLuint cntl = rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &
221 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ROP_ENABLE;
226 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ALPHA_BLEND_ENABLE | R200_SEPARATE_ALPHA_ENABLE;
229 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl;
685 GLuint flag = rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] & ~R200_PLANE_MASK_ENABLE;
700 if ( rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] != flag ) {
702 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = flag;
    [all...]
r200_state_init.c 450 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
452 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
456 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
460 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444;
464 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555;
507 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
    [all...]
r200_context.h 107 #define CTX_RB3D_CNTL 10

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