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      1 /*
      2  * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
      3  *
      4  * SPDX-License-Identifier: BSD-3-Clause
      5  */
      6 
      7 #ifndef __DDR_RK3368_H__
      8 #define __DDR_RK3368_H__
      9 
     10 #define DDR_PCTL_SCFG		0x0
     11 #define DDR_PCTL_SCTL		0x4
     12 #define DDR_PCTL_STAT		0x8
     13 #define DDR_PCTL_INTRSTAT	0xc
     14 
     15 #define DDR_PCTL_MCMD		0x40
     16 #define DDR_PCTL_POWCTL		0x44
     17 #define DDR_PCTL_POWSTAT	0x48
     18 #define DDR_PCTL_CMDTSTAT	0x4c
     19 #define DDR_PCTL_CMDTSTATEN	0x50
     20 #define DDR_PCTL_MRRCFG0	0x60
     21 #define DDR_PCTL_MRRSTAT0	0x64
     22 #define DDR_PCTL_MRRSTAT1	0x68
     23 #define DDR_PCTL_MCFG1		0x7c
     24 #define DDR_PCTL_MCFG		0x80
     25 #define DDR_PCTL_PPCFG		0x84
     26 #define DDR_PCTL_MSTAT		0x88
     27 #define DDR_PCTL_LPDDR2ZQCFG	0x8c
     28 #define DDR_PCTL_DTUPDES		0x94
     29 #define DDR_PCTL_DTUNA			0x98
     30 #define DDR_PCTL_DTUNE			0x9c
     31 #define DDR_PCTL_DTUPRD0		0xa0
     32 #define DDR_PCTL_DTUPRD1		0xa4
     33 #define DDR_PCTL_DTUPRD2		0xa8
     34 #define DDR_PCTL_DTUPRD3		0xac
     35 #define DDR_PCTL_DTUAWDT		0xb0
     36 #define DDR_PCTL_TOGCNT1U		0xc0
     37 #define DDR_PCTL_TINIT			0xc4
     38 #define DDR_PCTL_TRSTH			0xc8
     39 #define DDR_PCTL_TOGCNT100N		0xcc
     40 #define DDR_PCTL_TREFI			0xd0
     41 #define DDR_PCTL_TMRD			0xd4
     42 #define DDR_PCTL_TRFC			0xd8
     43 #define DDR_PCTL_TRP			0xdc
     44 #define DDR_PCTL_TRTW			0xe0
     45 #define DDR_PCTL_TAL			0xe4
     46 #define DDR_PCTL_TCL			0xe8
     47 #define DDR_PCTL_TCWL			0xec
     48 #define DDR_PCTL_TRAS			0xf0
     49 #define DDR_PCTL_TRC			0xf4
     50 #define DDR_PCTL_TRCD			0xf8
     51 #define DDR_PCTL_TRRD			0xfc
     52 #define DDR_PCTL_TRTP			0x100
     53 #define DDR_PCTL_TWR			0x104
     54 #define DDR_PCTL_TWTR			0x108
     55 #define DDR_PCTL_TEXSR			0x10c
     56 #define DDR_PCTL_TXP			0x110
     57 #define DDR_PCTL_TXPDLL			0x114
     58 #define DDR_PCTL_TZQCS			0x118
     59 #define DDR_PCTL_TZQCSI			0x11c
     60 #define DDR_PCTL_TDQS			0x120
     61 #define DDR_PCTL_TCKSRE			0x124
     62 #define DDR_PCTL_TCKSRX			0x128
     63 #define DDR_PCTL_TCKE			0x12c
     64 #define DDR_PCTL_TMOD			0x130
     65 #define DDR_PCTL_TRSTL			0x134
     66 #define DDR_PCTL_TZQCL			0x138
     67 #define DDR_PCTL_TMRR			0x13c
     68 #define DDR_PCTL_TCKESR			0x140
     69 #define DDR_PCTL_TDPD			0x144
     70 #define DDR_PCTL_TREFI_MEM_DDR3	0x148
     71 #define DDR_PCTL_ECCCFG			0x180
     72 #define DDR_PCTL_ECCTST			0x184
     73 #define DDR_PCTL_ECCCLR			0x188
     74 #define DDR_PCTL_ECCLOG			0x18c
     75 #define DDR_PCTL_DTUWACTL		0x200
     76 #define DDR_PCTL_DTURACTL		0x204
     77 #define DDR_PCTL_DTUCFG			0x208
     78 #define DDR_PCTL_DTUECTL		0x20c
     79 #define DDR_PCTL_DTUWD0			0x210
     80 #define DDR_PCTL_DTUWD1			0x214
     81 #define DDR_PCTL_DTUWD2			0x218
     82 #define DDR_PCTL_DTUWD3			0x21c
     83 #define DDR_PCTL_DTUWDM			0x220
     84 #define DDR_PCTL_DTURD0			0x224
     85 #define DDR_PCTL_DTURD1			0x228
     86 #define DDR_PCTL_DTURD2			0x22c
     87 #define DDR_PCTL_DTURD3			0x230
     88 #define DDR_PCTL_DTULFSRWD		0x234
     89 #define DDR_PCTL_DTULFSRRD		0x238
     90 #define DDR_PCTL_DTUEAF			0x23c
     91 #define DDR_PCTL_DFITCTRLDELAY	0x240
     92 #define DDR_PCTL_DFIODTCFG		0x244
     93 #define DDR_PCTL_DFIODTCFG1		0x248
     94 #define DDR_PCTL_DFIODTRANKMAP		0x24c
     95 #define DDR_PCTL_DFITPHYWRDATA		0x250
     96 #define DDR_PCTL_DFITPHYWRLAT		0x254
     97 #define DDR_PCTL_DFITPHYWRDATALAT	0x258
     98 #define DDR_PCTL_DFITRDDATAEN		0x260
     99 #define DDR_PCTL_DFITPHYRDLAT		0x264
    100 #define DDR_PCTL_DFITPHYUPDTYPE0	0x270
    101 #define DDR_PCTL_DFITPHYUPDTYPE1	0x274
    102 #define DDR_PCTL_DFITPHYUPDTYPE2	0x278
    103 #define DDR_PCTL_DFITPHYUPDTYPE3	0x27c
    104 #define DDR_PCTL_DFITCTRLUPDMIN		0x280
    105 #define DDR_PCTL_DFITCTRLUPDMAX		0x284
    106 #define DDR_PCTL_DFITCTRLUPDDLY		0x288
    107 #define DDR_PCTL_DFIUPDCFG			0x290
    108 #define DDR_PCTL_DFITREFMSKI		0x294
    109 #define DDR_PCTL_DFITCTRLUPDI		0x298
    110 #define DDR_PCTL_DFITRCFG0			0x2ac
    111 #define DDR_PCTL_DFITRSTAT0			0x2b0
    112 #define DDR_PCTL_DFITRWRLVLEN		0x2b4
    113 #define DDR_PCTL_DFITRRDLVLEN		0x2b8
    114 #define DDR_PCTL_DFITRRDLVLGATEEN	0x2bc
    115 #define DDR_PCTL_DFISTSTAT0			0x2c0
    116 #define DDR_PCTL_DFISTCFG0			0x2c4
    117 #define DDR_PCTL_DFISTCFG1			0x2c8
    118 #define DDR_PCTL_DFITDRAMCLKEN		0x2d0
    119 #define DDR_PCTL_DFITDRAMCLKDIS		0x2d4
    120 #define DDR_PCTL_DFISTCFG2			0x2d8
    121 #define DDR_PCTL_DFISTPARCLR		0x2dc
    122 #define DDR_PCTL_DFISTPARLOG		0x2e0
    123 #define DDR_PCTL_DFILPCFG0			0x2f0
    124 #define DDR_PCTL_DFITRWRLVLRESP0	0x300
    125 #define DDR_PCTL_DFITRWRLVLRESP1	0x304
    126 #define DDR_PCTL_DFITRWRLVLRESP2	0x308
    127 #define DDR_PCTL_DFITRRDLVLRESP0	0x30c
    128 #define DDR_PCTL_DFITRRDLVLRESP1	0x310
    129 #define DDR_PCTL_DFITRRDLVLRESP2	0x314
    130 #define DDR_PCTL_DFITRWRLVLDELAY0	0x318
    131 #define DDR_PCTL_DFITRWRLVLDELAY1	0x31c
    132 #define DDR_PCTL_DFITRWRLVLDELAY2	0x320
    133 #define DDR_PCTL_DFITRRDLVLDELAY0	0x324
    134 #define DDR_PCTL_DFITRRDLVLDELAY1	0x328
    135 #define DDR_PCTL_DFITRRDLVLDELAY2	0x32c
    136 #define DDR_PCTL_DFITRRDLVLGATEDELAY0	0x330
    137 #define DDR_PCTL_DFITRRDLVLGATEDELAY1	0x334
    138 #define DDR_PCTL_DFITRRDLVLGATEDELAY2	0x338
    139 #define DDR_PCTL_DFITRCMD			0x33c
    140 #define DDR_PCTL_IPVR				0x3f8
    141 #define DDR_PCTL_IPTR				0x3fc
    142 
    143 /* DDR PHY REG */
    144 #define DDR_PHY_REG0		0x0
    145 #define DDR_PHY_REG1		0x4
    146 #define DDR_PHY_REG2		0x8
    147 #define DDR_PHY_REG3		0xc
    148 #define DDR_PHY_REG4		0x10
    149 #define DDR_PHY_REG5		0x14
    150 #define DDR_PHY_REG6		0x18
    151 #define DDR_PHY_REGB		0x2c
    152 #define DDR_PHY_REGC		0x30
    153 #define DDR_PHY_REG11		0x44
    154 #define DDR_PHY_REG12		0x48
    155 #define DDR_PHY_REG13		0x4c
    156 #define DDR_PHY_REG14		0x50
    157 #define DDR_PHY_REG16		0x58
    158 #define DDR_PHY_REG20		0x80
    159 #define DDR_PHY_REG21		0x84
    160 #define DDR_PHY_REG26		0x98
    161 #define DDR_PHY_REG27		0x9c
    162 #define DDR_PHY_REG28		0xa0
    163 #define DDR_PHY_REG2C		0xb0
    164 #define DDR_PHY_REG30		0xc0
    165 #define DDR_PHY_REG31		0xc4
    166 #define DDR_PHY_REG36		0xd8
    167 #define DDR_PHY_REG37		0xdc
    168 #define DDR_PHY_REG38		0xe0
    169 #define DDR_PHY_REG3C		0xf0
    170 #define DDR_PHY_REG40		0x100
    171 #define DDR_PHY_REG41		0x104
    172 #define DDR_PHY_REG46		0x118
    173 #define DDR_PHY_REG47		0x11c
    174 #define DDR_PHY_REG48		0x120
    175 #define DDR_PHY_REG4C		0x130
    176 #define DDR_PHY_REG50		0x140
    177 #define DDR_PHY_REG51		0x144
    178 #define DDR_PHY_REG56		0x158
    179 #define DDR_PHY_REG57		0x15c
    180 #define DDR_PHY_REG58		0x160
    181 #define DDR_PHY_REG5C		0x170
    182 #define DDR_PHY_REGDLL		0x290
    183 #define DDR_PHY_REGEC		0x3b0
    184 #define DDR_PHY_REGED		0x3b4
    185 #define DDR_PHY_REGEE		0x3b8
    186 #define DDR_PHY_REGEF		0x3bc
    187 #define DDR_PHY_REGF0		0x3c0
    188 #define DDR_PHY_REGF1		0x3c4
    189 #define DDR_PHY_REGF2		0x3c8
    190 #define DDR_PHY_REGFA		0x3e8
    191 #define DDR_PHY_REGFB		0x3ec
    192 #define DDR_PHY_REGFC		0x3f0
    193 #define DDR_PHY_REGFD		0x3f4
    194 #define DDR_PHY_REGFE		0x3f8
    195 #define DDR_PHY_REGFF		0x3fc
    196 
    197 /* MSCH REG define */
    198 #define MSCH_COREID			0x0
    199 #define MSCH_DDRCONF		0x8
    200 #define MSCH_DDRTIMING		0xc
    201 #define MSCH_DDRMODE		0x10
    202 #define MSCH_READLATENCY	0x14
    203 #define MSCH_ACTIVATE		0x38
    204 #define MSCH_DEVTODEV		0x3c
    205 
    206 #define SET_NR(n)      ((0x3f << (8 + 16)) | ((n - 1) << 8))
    207 #define SET_NO(n)      ((0xf << (0 + 16)) | ((n - 1) << 0))
    208 #define SET_NF(n)      ((n - 1) & 0x1fff)
    209 #define SET_NB(n)      ((n - 1) & 0xfff)
    210 #define PLLMODE(n)     ((0x3 << (8 + 16)) | (n << 8))
    211 
    212 /* GRF REG define */
    213 #define GRF_SOC_STATUS0		0x480
    214 #define GRF_DDRPHY_LOCK		(0x1 << 15)
    215 #define GRF_DDRC0_CON0		0x600
    216 
    217 /* CRU softreset ddr pctl, phy */
    218 #define DDRMSCH0_SRSTN_REQ(n)  (((0x1 << 10) << 16) | (n << 10))
    219 #define DDRCTRL0_PSRSTN_REQ(n) (((0x1 << 3) << 16) | (n << 3))
    220 #define DDRCTRL0_SRSTN_REQ(n)  (((0x1 << 2) << 16) | (n << 2))
    221 #define DDRPHY0_PSRSTN_REQ(n)  (((0x1 << 1) << 16) | (n << 1))
    222 #define DDRPHY0_SRSTN_REQ(n)   (((0x1 << 0) << 16) | (n << 0))
    223 
    224 /* CRU_DPLL_CON2 */
    225 #define DPLL_STATUS_LOCK		(1 << 31)
    226 
    227 /* CRU_DPLL_CON3 */
    228 #define DPLL_POWER_DOWN			((0x1 << (1 + 16)) | (0 << 1))
    229 #define DPLL_WORK_NORMAL_MODE		((0x3 << (8 + 16)) | (0 << 8))
    230 #define DPLL_WORK_SLOW_MODE		((0x3 << (8 + 16)) | (1 << 8))
    231 #define DPLL_RESET_CONTROL_NORMAL	((0x1 << (5 + 16)) | (0x0 << 5))
    232 #define DPLL_RESET_CONTROL_RESET	((0x1 << (5 + 16)) | (0x1 << 5))
    233 
    234 /* PMU_PWRDN_CON */
    235 #define PD_PERI_PWRDN_ENABLE		(1 << 13)
    236 
    237 #define DDR_PLL_SRC_MASK		0x13
    238 
    239 /* DDR_PCTL_TREFI */
    240 #define DDR_UPD_REF_ENABLE		(0X1 << 31)
    241 
    242 uint32_t ddr_get_resume_code_size(void);
    243 uint32_t ddr_get_resume_data_size(void);
    244 uint32_t *ddr_get_resume_code_base(void);
    245 void ddr_reg_save(uint32_t pllpdstat, uint64_t base_addr);
    246 
    247 #endif
    248