| /external/valgrind/none/tests/mips64/ |
| shift_instructions.c | 8 DSRAV, DSRL, DSRL32, DSRLV,
114 case DSRL:
115 TEST2("dsrl $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
116 TEST2("dsrl $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
117 TEST2("dsrl $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
118 TEST2("dsrl $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
119 TEST2("dsrl $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
120 TEST2("dsrl $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
121 TEST2("dsrl $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
122 TEST2("dsrl $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1)
[all...] |
| /external/v8/src/mips64/ |
| constants-mips64.h | 456 DSRL = ((7U << 3) + 2),
965 FunctionFieldToBitNumber(SRL) | FunctionFieldToBitNumber(DSRL) |
[all...] |
| assembler-mips64.cc | 1865 void Assembler::dsrl(Register rd, Register rt, uint16_t sa) { function in class:v8::internal::Assembler
[all...] |
| simulator-mips64.cc | [all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.cpp | 72 case Mips::DSRL:
197 case Mips::DSRL:
[all...] |
| /external/pcre/dist2/src/sljit/ |
| sljitNativeMIPS_64.c | 427 EMIT_SHIFT(DSRL, DSRL32, SRL, DSRLV, SRLV);
|
| sljitNativeMIPS_common.c | 136 #define DSRL (HI(0) | LO(58))
[all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | [all...] |
