| /art/compiler/utils/mips64/ |
| assembler_mips64.h | 569 void Bc1eqz(FpuRegister ft, uint16_t imm16);
570 void Bc1nez(FpuRegister ft, uint16_t imm16);
580 void AddS(FpuRegister fd, FpuRegister fs, FpuRegister ft);
581 void SubS(FpuRegister fd, FpuRegister fs, FpuRegister ft);
582 void MulS(FpuRegister fd, FpuRegister fs, FpuRegister ft)
[all...] |
| managed_register_mips64.h | 41 // [R..F[ floating-point registers (enum FpuRegister)
51 // * floating-point register (enum FpuRegister)
63 constexpr FpuRegister AsFpuRegister() const {
65 return static_cast<FpuRegister>(id_ - kNumberOfGpuRegIds);
73 constexpr FpuRegister AsOverlappingFpuRegister() const {
75 return static_cast<FpuRegister>(AsVectorRegister());
112 static constexpr Mips64ManagedRegister FromFpuRegister(FpuRegister r) {
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| assembler_mips64.cc | 164 void Mips64Assembler::EmitFR(int opcode, int fmt, FpuRegister ft, FpuRegister fs, FpuRegister fd,
178 void Mips64Assembler::EmitFI(int opcode, int fmt, FpuRegister ft, uint16_t imm) {
821 void Mips64Assembler::Bc1eqz(FpuRegister ft, uint16_t imm16) {
825 void Mips64Assembler::Bc1nez(FpuRegister ft, uint16_t imm16) {
916 Bc1eqz(static_cast<FpuRegister>(rs), imm16_21);
920 Bc1nez(static_cast<FpuRegister>(rs), imm16_21);
977 void Mips64Assembler::AddS(FpuRegister fd, FpuRegister fs, FpuRegister ft)
[all...] |
| assembler_mips64_test.cc | 40 mips64::FpuRegister,
47 mips64::FpuRegister,
158 fp_registers_.push_back(new mips64::FpuRegister(mips64::F0));
159 fp_registers_.push_back(new mips64::FpuRegister(mips64::F1));
160 fp_registers_.push_back(new mips64::FpuRegister(mips64::F2));
161 fp_registers_.push_back(new mips64::FpuRegister(mips64::F3));
162 fp_registers_.push_back(new mips64::FpuRegister(mips64::F4));
163 fp_registers_.push_back(new mips64::FpuRegister(mips64::F5));
164 fp_registers_.push_back(new mips64::FpuRegister(mips64::F6));
165 fp_registers_.push_back(new mips64::FpuRegister(mips64::F7))
[all...] |
| managed_register_mips64_test.cc | 109 TEST(Mips64ManagedRegister, FpuRegister) {
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| /art/runtime/arch/mips64/ |
| registers_mips64.cc | 40 std::ostream& operator<<(std::ostream& os, const FpuRegister& rhs) {
44 os << "FpuRegister[" << static_cast<int>(rhs) << "]";
|
| registers_mips64.h | 72 enum FpuRegister {
110 std::ostream& operator<<(std::ostream& os, const FpuRegister& rhs);
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| /art/compiler/optimizing/ |
| intrinsics_mips64.cc | 67 FpuRegister trg_reg = trg.AsFpuRegister<FpuRegister>();
152 FpuRegister in = locations->InAt(0).AsFpuRegister<FpuRegister>();
189 FpuRegister out = locations->Out().AsFpuRegister<FpuRegister>();
474 FpuRegister in = locations->InAt(0).AsFpuRegister<FpuRegister>();
475 FpuRegister out = locations->Out().AsFpuRegister<FpuRegister>();
[all...] |
| code_generator_mips64.cc | [all...] |
| code_generator_mips64.h | 36 static constexpr FpuRegister kParameterFpuRegisters[] =
48 static constexpr FpuRegister kRuntimeParameterFpuRegisters[] =
56 static constexpr FpuRegister kFpuCalleeSaves[] =
64 class InvokeDexCallingConvention : public CallingConvention<GpuRegister, FpuRegister> {
92 class InvokeRuntimeCallingConvention : public CallingConvention<GpuRegister, FpuRegister> {
319 FpuRegister dst);
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| code_generator_vector_mips64.cc | 28 return static_cast<VectorRegister>(location.AsFpuRegister<FpuRegister>());
81 locations->InAt(0).AsFpuRegister<FpuRegister>(),
87 locations->InAt(0).AsFpuRegister<FpuRegister>(),
[all...] |
| /art/compiler/jni/quick/mips64/ |
| calling_convention_mips64.cc | 34 static const FpuRegister kFpuArgumentRegisters[] = {
136 FpuRegister arg = kFpuArgumentRegisters[reg_index];
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| /external/swiftshader/third_party/subzero/src/DartARM32/ |
| assembler_arm.h | 445 static const char* FpuRegisterName(FpuRegister reg);
[all...] |
| assembler_arm.cc | [all...] |
