1 /* 2 * Copyright (C) 2014 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef ART_RUNTIME_ARCH_MIPS64_REGISTERS_MIPS64_H_ 18 #define ART_RUNTIME_ARCH_MIPS64_REGISTERS_MIPS64_H_ 19 20 #include <iosfwd> 21 22 #include <android-base/logging.h> 23 24 #include "base/macros.h" 25 #include "globals.h" 26 27 namespace art { 28 namespace mips64 { 29 30 enum GpuRegister { 31 ZERO = 0, 32 AT = 1, // Assembler temporary. 33 V0 = 2, // Values. 34 V1 = 3, 35 A0 = 4, // Arguments. 36 A1 = 5, 37 A2 = 6, 38 A3 = 7, 39 A4 = 8, 40 A5 = 9, 41 A6 = 10, 42 A7 = 11, 43 T0 = 12, // Temporaries. 44 T1 = 13, 45 T2 = 14, 46 T3 = 15, 47 S0 = 16, // Saved values. 48 S1 = 17, 49 S2 = 18, 50 S3 = 19, 51 S4 = 20, 52 S5 = 21, 53 S6 = 22, 54 S7 = 23, 55 T8 = 24, // More temporaries. 56 T9 = 25, 57 K0 = 26, // Reserved for trap handler. 58 K1 = 27, 59 GP = 28, // Global pointer. 60 SP = 29, // Stack pointer. 61 S8 = 30, // Saved value/frame pointer. 62 RA = 31, // Return address. 63 TR = S1, // ART Thread Register 64 TMP = T8, // scratch register (in addition to AT) 65 TMP2 = T3, // scratch register (in addition to AT, reserved for assembler) 66 kNumberOfGpuRegisters = 32, 67 kNoGpuRegister = -1 // Signals an illegal register. 68 }; 69 std::ostream& operator<<(std::ostream& os, const GpuRegister& rhs); 70 71 // Values for floating point registers. 72 enum FpuRegister { 73 F0 = 0, 74 F1 = 1, 75 F2 = 2, 76 F3 = 3, 77 F4 = 4, 78 F5 = 5, 79 F6 = 6, 80 F7 = 7, 81 F8 = 8, 82 F9 = 9, 83 F10 = 10, 84 F11 = 11, 85 F12 = 12, 86 F13 = 13, 87 F14 = 14, 88 F15 = 15, 89 F16 = 16, 90 F17 = 17, 91 F18 = 18, 92 F19 = 19, 93 F20 = 20, 94 F21 = 21, 95 F22 = 22, 96 F23 = 23, 97 F24 = 24, 98 F25 = 25, 99 F26 = 26, 100 F27 = 27, 101 F28 = 28, 102 F29 = 29, 103 F30 = 30, 104 F31 = 31, 105 FTMP = F8, // scratch register 106 FTMP2 = F9, // scratch register (in addition to FTMP, reserved for MSA instructions) 107 kNumberOfFpuRegisters = 32, 108 kNoFpuRegister = -1, 109 }; 110 std::ostream& operator<<(std::ostream& os, const FpuRegister& rhs); 111 112 // Values for vector registers. 113 enum VectorRegister { 114 W0 = 0, 115 W1 = 1, 116 W2 = 2, 117 W3 = 3, 118 W4 = 4, 119 W5 = 5, 120 W6 = 6, 121 W7 = 7, 122 W8 = 8, 123 W9 = 9, 124 W10 = 10, 125 W11 = 11, 126 W12 = 12, 127 W13 = 13, 128 W14 = 14, 129 W15 = 15, 130 W16 = 16, 131 W17 = 17, 132 W18 = 18, 133 W19 = 19, 134 W20 = 20, 135 W21 = 21, 136 W22 = 22, 137 W23 = 23, 138 W24 = 24, 139 W25 = 25, 140 W26 = 26, 141 W27 = 27, 142 W28 = 28, 143 W29 = 29, 144 W30 = 30, 145 W31 = 31, 146 kNumberOfVectorRegisters = 32, 147 kNoVectorRegister = -1, 148 }; 149 std::ostream& operator<<(std::ostream& os, const VectorRegister& rhs); 150 151 } // namespace mips64 152 } // namespace art 153 154 #endif // ART_RUNTIME_ARCH_MIPS64_REGISTERS_MIPS64_H_ 155
