| /art/compiler/utils/mips64/ |
| assembler_mips64.h | 66 void TemplateLoadConst32(Asm* a, GpuRegister rd, int32_t value) {
446 void Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
447 void Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
448 void Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
449 void Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16); // MIPS6
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| assembler_mips64.cc | 99 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd,
113 void Mips64Assembler::EmitRsd(int opcode, GpuRegister rs, GpuRegister rd,
126 void Mips64Assembler::EmitRtd(int opcode, GpuRegister rt, GpuRegister rd,
139 void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) {
149 void Mips64Assembler::EmitI21(int opcode, GpuRegister rs, uint32_t imm21)
[all...] |
| managed_register_mips64.h | 40 // [0..R[ core registers (enum GpuRegister)
50 // * core register (enum GpuRegister)
58 constexpr GpuRegister AsGpuRegister() const {
60 return static_cast<GpuRegister>(id_);
107 static constexpr Mips64ManagedRegister FromGpuRegister(GpuRegister r) {
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| assembler_mips64_test.cc | 32 bool operator()(const mips64::GpuRegister& a, const mips64::GpuRegister& b) const {
39 mips64::GpuRegister,
46 mips64::GpuRegister,
92 registers_.push_back(new mips64::GpuRegister(mips64::ZERO));
93 registers_.push_back(new mips64::GpuRegister(mips64::AT));
94 registers_.push_back(new mips64::GpuRegister(mips64::V0));
95 registers_.push_back(new mips64::GpuRegister(mips64::V1));
96 registers_.push_back(new mips64::GpuRegister(mips64::A0));
97 registers_.push_back(new mips64::GpuRegister(mips64::A1))
[all...] |
| managed_register_mips64_test.cc | 30 TEST(Mips64ManagedRegister, GpuRegister) {
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| /art/compiler/optimizing/ |
| intrinsics_mips64.cc | 62 GpuRegister trg_reg = trg.AsRegister<GpuRegister>();
153 GpuRegister out = locations->Out().AsRegister<GpuRegister>();
188 GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>();
226 GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>();
227 GpuRegister out = locations->Out().AsRegister<GpuRegister>();
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| code_generator_mips64.cc | 44 static constexpr GpuRegister kMethodRegisterArgument = A0;
488 GpuRegister ref_reg = ref_.AsRegister<GpuRegister>();
528 DCHECK_EQ(entrypoint_.AsRegister<GpuRegister>(), T9);
529 __ Jalr(entrypoint_.AsRegister<GpuRegister>());
566 GpuRegister obj,
568 GpuRegister temp1)
583 GpuRegister ref_reg = ref_.AsRegister<GpuRegister>();
649 GpuRegister base = obj_
[all...] |
| code_generator_mips64.h | 32 static constexpr GpuRegister kParameterCoreRegisters[] =
43 static constexpr GpuRegister kRuntimeParameterCoreRegisters[] =
54 static constexpr GpuRegister kCoreCalleeSaves[] =
64 class InvokeDexCallingConvention : public CallingConvention<GpuRegister, FpuRegister> {
92 class InvokeRuntimeCallingConvention : public CallingConvention<GpuRegister, FpuRegister> {
235 void GenerateClassInitializationCheck(SlowPathCodeMIPS64* slow_path, GpuRegister class_reg);
283 GpuRegister obj,
303 GpuRegister dst);
326 void GenPackedSwitchWithCompares(GpuRegister value_reg,
331 void GenTableBasedPackedSwitch(GpuRegister value_reg
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| code_generator_vector_mips64.cc | 63 __ FillB(dst, locations->InAt(0).AsRegister<GpuRegister>());
68 __ FillH(dst, locations->InAt(0).AsRegister<GpuRegister>());
72 __ FillW(dst, locations->InAt(0).AsRegister<GpuRegister>());
76 __ FillD(dst, locations->InAt(0).AsRegister<GpuRegister>());
126 __ Copy_sW(locations->Out().AsRegister<GpuRegister>(), src, 0);
130 __ Copy_sD(locations->Out().AsRegister<GpuRegister>(), src, 0);
[all...] |
| /art/runtime/arch/mips64/ |
| registers_mips64.cc | 31 std::ostream& operator<<(std::ostream& os, const GpuRegister& rhs) {
35 os << "GpuRegister[" << static_cast<int>(rhs) << "]";
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| registers_mips64.h | 30 enum GpuRegister {
69 std::ostream& operator<<(std::ostream& os, const GpuRegister& rhs);
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| /art/compiler/jni/quick/mips64/ |
| calling_convention_mips64.cc | 30 static const GpuRegister kGpuArgumentRegisters[] = {
140 GpuRegister arg = kGpuArgumentRegisters[reg_index];
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