| /toolchain/binutils/binutils-2.27/opcodes/ |
| lm32-opinst.c | 45 { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 },
46 { INPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 },
47 { OUTPUT, "r2", HW_H_GR, CGEN_MODE_SI, OP_ENT (R2), 0, 0 },
53 { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 },
54 { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 },
59 { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 },
61 { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 },
67 { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 },
68 { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 },
74 { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }
[all...] |
| m32r-opinst.c | 45 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
46 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
47 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
53 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
54 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
59 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
61 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
66 { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
68 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
73 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }
[all...] |
| xstormy16-desc.c | 231 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
354 { "Rd", XSTORMY16_OPERAND_RD, HW_H_GR, 12, 4,
358 { "Rdm", XSTORMY16_OPERAND_RDM, HW_H_GR, 13, 3,
362 { "Rm", XSTORMY16_OPERAND_RM, HW_H_GR, 4, 3,
366 { "Rs", XSTORMY16_OPERAND_RS, HW_H_GR, 8, 4,
450 { "psw", XSTORMY16_OPERAND_PSW, HW_H_GR, 0, 0,
458 { "sp", XSTORMY16_OPERAND_SP, HW_H_GR, 0, 0,
462 { "R0", XSTORMY16_OPERAND_R0, HW_H_GR, 0, 0,
466 { "R1", XSTORMY16_OPERAND_R1, HW_H_GR, 0, 0,
470 { "R2", XSTORMY16_OPERAND_R2, HW_H_GR, 0, 0
[all...] |
| lm32-desc.c | 225 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & lm32_cgen_opval_h_gr, { 0, { { { (1<<MACH_BASE), 0 } } } } },
280 { "r0", LM32_OPERAND_R0, HW_H_GR, 25, 5,
284 { "r1", LM32_OPERAND_R1, HW_H_GR, 20, 5,
288 { "r2", LM32_OPERAND_R2, HW_H_GR, 15, 5,
[all...] |
| fr30-desc.c | 264 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
370 { "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4,
374 { "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4,
378 { "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4,
382 { "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4,
[all...] |
| m32r-desc.c | 242 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
318 { "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
322 { "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
326 { "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
330 { "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
[all...] |
| iq2000-desc.c | 225 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & iq2000_cgen_opval_gr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
322 { "rs", IQ2000_OPERAND_RS, HW_H_GR, 25, 5,
326 { "rt", IQ2000_OPERAND_RT, HW_H_GR, 20, 5,
330 { "rd", IQ2000_OPERAND_RD, HW_H_GR, 15, 5,
334 { "rd-rs", IQ2000_OPERAND_RD_RS, HW_H_GR, 15, 10,
338 { "rd-rt", IQ2000_OPERAND_RD_RT, HW_H_GR, 15, 10,
342 { "rt-rs", IQ2000_OPERAND_RT_RS, HW_H_GR, 20, 10,
418 { "base", IQ2000_OPERAND_BASE, HW_H_GR, 25, 5,
[all...] |
| lm32-desc.h | 150 , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CSR
|
| m32r-desc.h | 180 , HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM
|
| xc16x-desc.c | 635 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
744 { "sr", XC16X_OPERAND_SR, HW_H_GR, 11, 4,
748 { "dr", XC16X_OPERAND_DR, HW_H_GR, 15, 4,
752 { "dri", XC16X_OPERAND_DRI, HW_H_GR, 11, 4,
764 { "sr2", XC16X_OPERAND_SR2, HW_H_GR, 9, 2,
768 { "src1", XC16X_OPERAND_SRC1, HW_H_GR, 15, 4,
772 { "src2", XC16X_OPERAND_SRC2, HW_H_GR, 11, 4,
[all...] |
| fr30-desc.h | 202 , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CR
|
| xstormy16-desc.h | 229 , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_RB
|
| iq2000-desc.h | 245 , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_MAX
|
| xc16x-desc.h | 318 , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CR
|
| m32c-desc.h | 175 , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_GR_QI
[all...] |
| frv-desc.c | [all...] |
| frv-desc.h | [all...] |
| m32c-desc.c | 710 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr, { 0|A(CACHE_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
[all...] |
