1 /* CPU data header for m32r. 2 3 THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5 Copyright (C) 1996-2016 Free Software Foundation, Inc. 6 7 This file is part of the GNU Binutils and/or GDB, the GNU debugger. 8 9 This file is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, write to the Free Software Foundation, Inc., 21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 22 23 */ 24 25 #ifndef M32R_CPU_H 26 #define M32R_CPU_H 27 28 #define CGEN_ARCH m32r 29 30 /* Given symbol S, return m32r_cgen_<S>. */ 31 #define CGEN_SYM(s) m32r##_cgen_##s 32 33 34 /* Selected cpu families. */ 35 #define HAVE_CPU_M32RBF 36 #define HAVE_CPU_M32RXF 37 #define HAVE_CPU_M32R2F 38 39 #define CGEN_INSN_LSB0_P 0 40 41 /* Minimum size of any insn (in bytes). */ 42 #define CGEN_MIN_INSN_SIZE 2 43 44 /* Maximum size of any insn (in bytes). */ 45 #define CGEN_MAX_INSN_SIZE 4 46 47 #define CGEN_INT_INSN_P 1 48 49 /* Maximum number of syntax elements in an instruction. */ 50 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15 51 52 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. 53 e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands 54 we can't hash on everything up to the space. */ 55 #define CGEN_MNEMONIC_OPERANDS 56 57 /* Maximum number of fields in an instruction. */ 58 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7 59 60 /* Enums. */ 61 62 /* Enum declaration for insn format enums. */ 63 typedef enum insn_op1 { 64 OP1_0, OP1_1, OP1_2, OP1_3 65 , OP1_4, OP1_5, OP1_6, OP1_7 66 , OP1_8, OP1_9, OP1_10, OP1_11 67 , OP1_12, OP1_13, OP1_14, OP1_15 68 } INSN_OP1; 69 70 /* Enum declaration for op2 enums. */ 71 typedef enum insn_op2 { 72 OP2_0, OP2_1, OP2_2, OP2_3 73 , OP2_4, OP2_5, OP2_6, OP2_7 74 , OP2_8, OP2_9, OP2_10, OP2_11 75 , OP2_12, OP2_13, OP2_14, OP2_15 76 } INSN_OP2; 77 78 /* Enum declaration for . */ 79 typedef enum gr_names { 80 H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0 81 , H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4 82 , H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8 83 , H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12 84 , H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15 85 } GR_NAMES; 86 87 /* Enum declaration for . */ 88 typedef enum cr_names { 89 H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3 90 , H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_EVB = 5 91 , H_CR_CR0 = 0, H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3 92 , H_CR_CR4 = 4, H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7 93 , H_CR_CR8 = 8, H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11 94 , H_CR_CR12 = 12, H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15 95 } CR_NAMES; 96 97 /* Attributes. */ 98 99 /* Enum declaration for machine type selection. */ 100 typedef enum mach_attr { 101 MACH_BASE, MACH_M32R, MACH_M32RX, MACH_M32R2 102 , MACH_MAX 103 } MACH_ATTR; 104 105 /* Enum declaration for instruction set selection. */ 106 typedef enum isa_attr { 107 ISA_M32R, ISA_MAX 108 } ISA_ATTR; 109 110 /* Enum declaration for parallel execution pipeline selection. */ 111 typedef enum pipe_attr { 112 PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS 113 , PIPE_O_OS 114 } PIPE_ATTR; 115 116 /* Number of architecture variants. */ 117 #define MAX_ISAS 1 118 #define MAX_MACHS ((int) MACH_MAX) 119 120 /* Ifield support. */ 121 122 /* Ifield attribute indices. */ 123 124 /* Enum declaration for cgen_ifld attrs. */ 125 typedef enum cgen_ifld_attr { 126 CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED 127 , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS 128 , CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS 129 } CGEN_IFLD_ATTR; 130 131 /* Number of non-boolean elements in cgen_ifld_attr. */ 132 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) 133 134 /* cgen_ifld attribute accessor macros. */ 135 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) 136 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) 137 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) 138 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) 139 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) 140 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) 141 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) 142 #define CGEN_ATTR_CGEN_IFLD_RELOC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RELOC)) != 0) 143 144 /* Enum declaration for m32r ifield types. */ 145 typedef enum ifield_type { 146 M32R_F_NIL, M32R_F_ANYOF, M32R_F_OP1, M32R_F_OP2 147 , M32R_F_COND, M32R_F_R1, M32R_F_R2, M32R_F_SIMM8 148 , M32R_F_SIMM16, M32R_F_SHIFT_OP2, M32R_F_UIMM3, M32R_F_UIMM4 149 , M32R_F_UIMM5, M32R_F_UIMM8, M32R_F_UIMM16, M32R_F_UIMM24 150 , M32R_F_HI16, M32R_F_DISP8, M32R_F_DISP16, M32R_F_DISP24 151 , M32R_F_OP23, M32R_F_OP3, M32R_F_ACC, M32R_F_ACCS 152 , M32R_F_ACCD, M32R_F_BITS67, M32R_F_BIT4, M32R_F_BIT14 153 , M32R_F_IMM1, M32R_F_MAX 154 } IFIELD_TYPE; 155 156 #define MAX_IFLD ((int) M32R_F_MAX) 157 158 /* Hardware attribute indices. */ 159 160 /* Enum declaration for cgen_hw attrs. */ 161 typedef enum cgen_hw_attr { 162 CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE 163 , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS 164 } CGEN_HW_ATTR; 165 166 /* Number of non-boolean elements in cgen_hw_attr. */ 167 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) 168 169 /* cgen_hw attribute accessor macros. */ 170 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) 171 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) 172 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) 173 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) 174 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) 175 176 /* Enum declaration for m32r hardware types. */ 177 typedef enum cgen_hw_type { 178 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR 179 , HW_H_IADDR, HW_H_PC, HW_H_HI16, HW_H_SLO16 180 , HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM 181 , HW_H_ACCUMS, HW_H_COND, HW_H_PSW, HW_H_BPSW 182 , HW_H_BBPSW, HW_H_LOCK, HW_MAX 183 } CGEN_HW_TYPE; 184 185 #define MAX_HW ((int) HW_MAX) 186 187 /* Operand attribute indices. */ 188 189 /* Enum declaration for cgen_operand attrs. */ 190 typedef enum cgen_operand_attr { 191 CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT 192 , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY 193 , CGEN_OPERAND_RELOC, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH 194 , CGEN_OPERAND_END_NBOOLS 195 } CGEN_OPERAND_ATTR; 196 197 /* Number of non-boolean elements in cgen_operand_attr. */ 198 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) 199 200 /* cgen_operand attribute accessor macros. */ 201 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) 202 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) 203 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) 204 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) 205 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) 206 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) 207 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) 208 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) 209 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) 210 #define CGEN_ATTR_CGEN_OPERAND_RELOC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELOC)) != 0) 211 212 /* Enum declaration for m32r operand types. */ 213 typedef enum cgen_operand_type { 214 M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1 215 , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8 216 , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM3, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5 217 , M32R_OPERAND_UIMM8, M32R_OPERAND_UIMM16, M32R_OPERAND_IMM1, M32R_OPERAND_ACCD 218 , M32R_OPERAND_ACCS, M32R_OPERAND_ACC, M32R_OPERAND_HASH, M32R_OPERAND_HI16 219 , M32R_OPERAND_SLO16, M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8 220 , M32R_OPERAND_DISP16, M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM 221 , M32R_OPERAND_MAX 222 } CGEN_OPERAND_TYPE; 223 224 /* Number of operands types. */ 225 #define MAX_OPERANDS 28 226 227 /* Maximum number of operands referenced by any insn. */ 228 #define MAX_OPERAND_INSTANCES 11 229 230 /* Insn attribute indices. */ 231 232 /* Enum declaration for cgen_insn attrs. */ 233 typedef enum cgen_insn_attr { 234 CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI 235 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED 236 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_FILL_SLOT, CGEN_INSN_SPECIAL 237 , CGEN_INSN_SPECIAL_M32R, CGEN_INSN_SPECIAL_FLOAT, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 238 , CGEN_INSN_MACH, CGEN_INSN_PIPE, CGEN_INSN_END_NBOOLS 239 } CGEN_INSN_ATTR; 240 241 /* Number of non-boolean elements in cgen_insn_attr. */ 242 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) 243 244 /* cgen_insn attribute accessor macros. */ 245 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) 246 #define CGEN_ATTR_CGEN_INSN_PIPE_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_PIPE-CGEN_INSN_START_NBOOLS-1].nonbitset) 247 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) 248 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) 249 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) 250 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) 251 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) 252 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) 253 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) 254 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) 255 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) 256 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) 257 #define CGEN_ATTR_CGEN_INSN_FILL_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_FILL_SLOT)) != 0) 258 #define CGEN_ATTR_CGEN_INSN_SPECIAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SPECIAL)) != 0) 259 #define CGEN_ATTR_CGEN_INSN_SPECIAL_M32R_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SPECIAL_M32R)) != 0) 260 #define CGEN_ATTR_CGEN_INSN_SPECIAL_FLOAT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SPECIAL_FLOAT)) != 0) 261 262 /* cgen.h uses things we just defined. */ 263 #include "opcode/cgen.h" 264 265 extern const struct cgen_ifld m32r_cgen_ifld_table[]; 266 267 /* Attributes. */ 268 extern const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[]; 269 extern const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[]; 270 extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[]; 271 extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[]; 272 273 /* Hardware decls. */ 274 275 extern CGEN_KEYWORD m32r_cgen_opval_gr_names; 276 extern CGEN_KEYWORD m32r_cgen_opval_cr_names; 277 extern CGEN_KEYWORD m32r_cgen_opval_h_accums; 278 279 extern const CGEN_HW_ENTRY m32r_cgen_hw_table[]; 280 281 282 283 #endif /* M32R_CPU_H */ 284
