| /frameworks/compile/mclinker/lib/Target/AArch64/ |
| AArch64InsnHelpers.h | 18 typedef uint32_t InsnType;
25 static unsigned getBits(InsnType insn, int pos, int l) {
29 static unsigned getRt(InsnType insn) {
33 static unsigned getRt2(InsnType insn) {
37 static unsigned getRa(InsnType insn) {
41 static unsigned getRd(InsnType insn) {
45 static unsigned getRn(InsnType insn) {
49 static unsigned getRm(InsnType insn) {
53 static unsigned getBit(InsnType insn, int pos) {
57 static unsigned getOp31(InsnType insn)
[all...] |
| /external/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 437 template <typename InsnType>
438 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
441 template <typename InsnType>
443 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
446 template <typename InsnType>
448 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
451 template <typename InsnType>
453 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
456 template <typename InsnType>
458 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address
[all...] |
| /external/capstone/arch/XCore/ |
| XCoreGenDisassemblerTables.inc | 16 #define FieldFromInstruction(fname, InsnType) \
17 static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
19 InsnType fieldMask; \
20 if (numBits == sizeof(InsnType)*8) \
21 fieldMask = (InsnType)(-1LL); \
23 fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
[all...] |
| /external/capstone/arch/Sparc/ |
| SparcGenDisassemblerTables.inc | 16 #define FieldFromInstruction(fname, InsnType) \
17 static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
19 InsnType fieldMask; \
20 if (numBits == sizeof(InsnType)*8) \
21 fieldMask = (InsnType)(-1LL); \
23 fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
[all...] |
| /external/capstone/arch/PowerPC/ |
| PPCGenDisassemblerTables.inc | 16 #define FieldFromInstruction(fname, InsnType) \
17 static InsnType fname(InsnType insn, unsigned startBit, \
20 InsnType fieldMask; \
21 if (numBits == sizeof(InsnType)*8) \
22 fieldMask = (InsnType)(-1LL); \
24 fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
[all...] |
| /external/capstone/arch/SystemZ/ |
| SystemZGenDisassemblerTables.inc | 16 #define FieldFromInstruction(fname, InsnType) \
17 static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
19 InsnType fieldMask; \
20 if (numBits == sizeof(InsnType)*8) \
21 fieldMask = (InsnType)(-1LL); \
23 fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
[all...] |
| /external/capstone/arch/Mips/ |
| MipsGenDisassemblerTables.inc | 16 #define FieldFromInstruction(fname, InsnType) \
17 static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
19 InsnType fieldMask; \
20 if (numBits == sizeof(InsnType)*8) \
21 fieldMask = (InsnType)(-1LL); \
23 fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
[all...] |
| /external/capstone/arch/AArch64/ |
| AArch64GenDisassemblerTables.inc | 16 #define FieldFromInstruction(fname, InsnType) \
17 static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
19 InsnType fieldMask; \
20 if (numBits == sizeof(InsnType)*8) \
21 fieldMask = (InsnType)(-1LL); \
23 fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
[all...] |
| /external/capstone/arch/ARM/ |
| ARMGenDisassemblerTables.inc | 16 #define FieldFromInstruction(fname, InsnType) \
17 static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
19 InsnType fieldMask; \
20 if (numBits == sizeof(InsnType)*8) \
21 fieldMask = (InsnType)(-1LL); \
23 fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
[all...] |
