1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsSubtarget.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "mips-disassembler" 28 29 typedef MCDisassembler::DecodeStatus DecodeStatus; 30 31 namespace { 32 33 class MipsDisassembler : public MCDisassembler { 34 bool IsMicroMips; 35 bool IsBigEndian; 36 public: 37 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 38 : MCDisassembler(STI, Ctx), 39 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 40 IsBigEndian(IsBigEndian) {} 41 42 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; } 43 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 44 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 45 bool hasMips32r6() const { 46 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 47 } 48 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } 49 50 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 51 52 bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; } 53 54 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 55 56 bool hasCOP3() const { 57 // Only present in MIPS-I and MIPS-II 58 return !hasMips32() && !hasMips3(); 59 } 60 61 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 62 ArrayRef<uint8_t> Bytes, uint64_t Address, 63 raw_ostream &VStream, 64 raw_ostream &CStream) const override; 65 }; 66 67 } // end anonymous namespace 68 69 // Forward declare these because the autogenerated code will reference them. 70 // Definitions are further down. 71 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 72 unsigned RegNo, 73 uint64_t Address, 74 const void *Decoder); 75 76 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 77 unsigned RegNo, 78 uint64_t Address, 79 const void *Decoder); 80 81 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 82 unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 86 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 87 unsigned RegNo, 88 uint64_t Address, 89 const void *Decoder); 90 91 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 92 unsigned RegNo, 93 uint64_t Address, 94 const void *Decoder); 95 96 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 97 unsigned RegNo, 98 uint64_t Address, 99 const void *Decoder); 100 101 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 102 unsigned Insn, 103 uint64_t Address, 104 const void *Decoder); 105 106 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 107 unsigned RegNo, 108 uint64_t Address, 109 const void *Decoder); 110 111 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 112 unsigned RegNo, 113 uint64_t Address, 114 const void *Decoder); 115 116 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 117 unsigned RegNo, 118 uint64_t Address, 119 const void *Decoder); 120 121 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 122 unsigned RegNo, 123 uint64_t Address, 124 const void *Decoder); 125 126 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 127 unsigned RegNo, 128 uint64_t Address, 129 const void *Decoder); 130 131 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 132 uint64_t Address, 133 const void *Decoder); 134 135 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 136 unsigned Insn, 137 uint64_t Address, 138 const void *Decoder); 139 140 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 141 unsigned RegNo, 142 uint64_t Address, 143 const void *Decoder); 144 145 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 146 unsigned RegNo, 147 uint64_t Address, 148 const void *Decoder); 149 150 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 151 unsigned RegNo, 152 uint64_t Address, 153 const void *Decoder); 154 155 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 156 unsigned RegNo, 157 uint64_t Address, 158 const void *Decoder); 159 160 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 161 unsigned RegNo, 162 uint64_t Address, 163 const void *Decoder); 164 165 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 166 unsigned RegNo, 167 uint64_t Address, 168 const void *Decoder); 169 170 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 171 unsigned RegNo, 172 uint64_t Address, 173 const void *Decoder); 174 175 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 176 unsigned RegNo, 177 uint64_t Address, 178 const void *Decoder); 179 180 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 181 unsigned RegNo, 182 uint64_t Address, 183 const void *Decoder); 184 185 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 186 unsigned RegNo, 187 uint64_t Address, 188 const void *Decoder); 189 190 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 191 unsigned RegNo, 192 uint64_t Address, 193 const void *Decoder); 194 195 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 196 unsigned Offset, 197 uint64_t Address, 198 const void *Decoder); 199 200 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 201 unsigned Offset, 202 uint64_t Address, 203 const void *Decoder); 204 205 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 206 unsigned Insn, 207 uint64_t Address, 208 const void *Decoder); 209 210 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 211 unsigned Offset, 212 uint64_t Address, 213 const void *Decoder); 214 215 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 216 unsigned Offset, 217 uint64_t Address, 218 const void *Decoder); 219 220 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 221 unsigned Offset, 222 uint64_t Address, 223 const void *Decoder); 224 225 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 226 // shifted left by 1 bit. 227 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 228 unsigned Offset, 229 uint64_t Address, 230 const void *Decoder); 231 232 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 233 // shifted left by 1 bit. 234 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 235 unsigned Offset, 236 uint64_t Address, 237 const void *Decoder); 238 239 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 240 // shifted left by 1 bit. 241 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 242 unsigned Offset, 243 uint64_t Address, 244 const void *Decoder); 245 246 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is 247 // shifted left by 1 bit. 248 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 249 unsigned Offset, 250 uint64_t Address, 251 const void *Decoder); 252 253 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 254 // shifted left by 1 bit. 255 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 256 unsigned Insn, 257 uint64_t Address, 258 const void *Decoder); 259 260 static DecodeStatus DecodeMem(MCInst &Inst, 261 unsigned Insn, 262 uint64_t Address, 263 const void *Decoder); 264 265 static DecodeStatus DecodeMemEVA(MCInst &Inst, 266 unsigned Insn, 267 uint64_t Address, 268 const void *Decoder); 269 270 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 271 unsigned Insn, 272 uint64_t Address, 273 const void *Decoder); 274 275 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 276 unsigned Insn, 277 uint64_t Address, 278 const void *Decoder); 279 280 static DecodeStatus DecodeCacheOp(MCInst &Inst, 281 unsigned Insn, 282 uint64_t Address, 283 const void *Decoder); 284 285 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 286 unsigned Insn, 287 uint64_t Address, 288 const void *Decoder); 289 290 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 291 unsigned Insn, 292 uint64_t Address, 293 const void *Decoder); 294 295 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 296 unsigned Insn, 297 uint64_t Address, 298 const void *Decoder); 299 300 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 301 unsigned Insn, 302 uint64_t Address, 303 const void *Decoder); 304 305 static DecodeStatus DecodeSyncI(MCInst &Inst, 306 unsigned Insn, 307 uint64_t Address, 308 const void *Decoder); 309 310 static DecodeStatus DecodeSynciR6(MCInst &Inst, 311 unsigned Insn, 312 uint64_t Address, 313 const void *Decoder); 314 315 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 316 uint64_t Address, const void *Decoder); 317 318 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 319 unsigned Insn, 320 uint64_t Address, 321 const void *Decoder); 322 323 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 324 unsigned Insn, 325 uint64_t Address, 326 const void *Decoder); 327 328 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 329 unsigned Insn, 330 uint64_t Address, 331 const void *Decoder); 332 333 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 334 unsigned Insn, 335 uint64_t Address, 336 const void *Decoder); 337 338 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 339 unsigned Insn, 340 uint64_t Address, 341 const void *Decoder); 342 343 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 344 unsigned Insn, 345 uint64_t Address, 346 const void *Decoder); 347 348 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 349 unsigned Insn, 350 uint64_t Address, 351 const void *Decoder); 352 353 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 354 uint64_t Address, 355 const void *Decoder); 356 357 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 358 uint64_t Address, 359 const void *Decoder); 360 361 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, 362 uint64_t Address, 363 const void *Decoder); 364 365 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, 366 uint64_t Address, 367 const void *Decoder); 368 369 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 370 uint64_t Address, 371 const void *Decoder); 372 373 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 374 uint64_t Address, 375 const void *Decoder); 376 377 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 378 unsigned Insn, 379 uint64_t Address, 380 const void *Decoder); 381 382 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 383 unsigned Value, 384 uint64_t Address, 385 const void *Decoder); 386 387 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 388 unsigned Value, 389 uint64_t Address, 390 const void *Decoder); 391 392 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 393 unsigned Value, 394 uint64_t Address, 395 const void *Decoder); 396 397 template <unsigned Bits, int Offset, int Scale> 398 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 399 uint64_t Address, 400 const void *Decoder); 401 402 template <unsigned Bits, int Offset> 403 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 404 uint64_t Address, 405 const void *Decoder) { 406 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, 407 Decoder); 408 } 409 410 template <unsigned Bits, int Offset = 0, int ScaleBy = 1> 411 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 412 uint64_t Address, 413 const void *Decoder); 414 415 static DecodeStatus DecodeInsSize(MCInst &Inst, 416 unsigned Insn, 417 uint64_t Address, 418 const void *Decoder); 419 420 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 421 uint64_t Address, const void *Decoder); 422 423 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 424 uint64_t Address, const void *Decoder); 425 426 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 427 uint64_t Address, const void *Decoder); 428 429 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 430 uint64_t Address, const void *Decoder); 431 432 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 433 uint64_t Address, const void *Decoder); 434 435 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 436 /// handle. 437 template <typename InsnType> 438 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 439 const void *Decoder); 440 441 template <typename InsnType> 442 static DecodeStatus 443 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 444 const void *Decoder); 445 446 template <typename InsnType> 447 static DecodeStatus 448 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 449 const void *Decoder); 450 451 template <typename InsnType> 452 static DecodeStatus 453 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 454 const void *Decoder); 455 456 template <typename InsnType> 457 static DecodeStatus 458 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 459 const void *Decoder); 460 461 template <typename InsnType> 462 static DecodeStatus 463 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 464 const void *Decoder); 465 466 template <typename InsnType> 467 static DecodeStatus 468 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 469 const void *Decoder); 470 471 template <typename InsnType> 472 static DecodeStatus 473 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 474 const void *Decoder); 475 476 template <typename InsnType> 477 static DecodeStatus 478 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 479 const void *Decoder); 480 481 template <typename InsnType> 482 static DecodeStatus 483 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 484 const void *Decoder); 485 486 template <typename InsnType> 487 static DecodeStatus 488 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 489 const void *Decoder); 490 491 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 492 uint64_t Address, 493 const void *Decoder); 494 495 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 496 uint64_t Address, 497 const void *Decoder); 498 499 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 500 uint64_t Address, 501 const void *Decoder); 502 503 namespace llvm { 504 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, 505 TheMips64elTarget; 506 } 507 508 static MCDisassembler *createMipsDisassembler( 509 const Target &T, 510 const MCSubtargetInfo &STI, 511 MCContext &Ctx) { 512 return new MipsDisassembler(STI, Ctx, true); 513 } 514 515 static MCDisassembler *createMipselDisassembler( 516 const Target &T, 517 const MCSubtargetInfo &STI, 518 MCContext &Ctx) { 519 return new MipsDisassembler(STI, Ctx, false); 520 } 521 522 extern "C" void LLVMInitializeMipsDisassembler() { 523 // Register the disassembler. 524 TargetRegistry::RegisterMCDisassembler(TheMipsTarget, 525 createMipsDisassembler); 526 TargetRegistry::RegisterMCDisassembler(TheMipselTarget, 527 createMipselDisassembler); 528 TargetRegistry::RegisterMCDisassembler(TheMips64Target, 529 createMipsDisassembler); 530 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget, 531 createMipselDisassembler); 532 } 533 534 #include "MipsGenDisassemblerTables.inc" 535 536 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 537 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 538 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 539 return *(RegInfo->getRegClass(RC).begin() + RegNo); 540 } 541 542 template <typename InsnType> 543 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 544 const void *Decoder) { 545 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *); 546 // The size of the n field depends on the element size 547 // The register class also depends on this. 548 InsnType tmp = fieldFromInstruction(insn, 17, 5); 549 unsigned NSize = 0; 550 DecodeFN RegDecoder = nullptr; 551 if ((tmp & 0x18) == 0x00) { // INSVE_B 552 NSize = 4; 553 RegDecoder = DecodeMSA128BRegisterClass; 554 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 555 NSize = 3; 556 RegDecoder = DecodeMSA128HRegisterClass; 557 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 558 NSize = 2; 559 RegDecoder = DecodeMSA128WRegisterClass; 560 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 561 NSize = 1; 562 RegDecoder = DecodeMSA128DRegisterClass; 563 } else 564 llvm_unreachable("Invalid encoding"); 565 566 assert(NSize != 0 && RegDecoder != nullptr); 567 568 // $wd 569 tmp = fieldFromInstruction(insn, 6, 5); 570 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 571 return MCDisassembler::Fail; 572 // $wd_in 573 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 574 return MCDisassembler::Fail; 575 // $n 576 tmp = fieldFromInstruction(insn, 16, NSize); 577 MI.addOperand(MCOperand::createImm(tmp)); 578 // $ws 579 tmp = fieldFromInstruction(insn, 11, 5); 580 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 581 return MCDisassembler::Fail; 582 // $n2 583 MI.addOperand(MCOperand::createImm(0)); 584 585 return MCDisassembler::Success; 586 } 587 588 template <typename InsnType> 589 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 590 uint64_t Address, 591 const void *Decoder) { 592 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 593 // (otherwise we would have matched the ADDI instruction from the earlier 594 // ISA's instead). 595 // 596 // We have: 597 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 598 // BOVC if rs >= rt 599 // BEQZALC if rs == 0 && rt != 0 600 // BEQC if rs < rt && rs != 0 601 602 InsnType Rs = fieldFromInstruction(insn, 21, 5); 603 InsnType Rt = fieldFromInstruction(insn, 16, 5); 604 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 605 bool HasRs = false; 606 607 if (Rs >= Rt) { 608 MI.setOpcode(Mips::BOVC); 609 HasRs = true; 610 } else if (Rs != 0 && Rs < Rt) { 611 MI.setOpcode(Mips::BEQC); 612 HasRs = true; 613 } else 614 MI.setOpcode(Mips::BEQZALC); 615 616 if (HasRs) 617 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 618 Rs))); 619 620 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 621 Rt))); 622 MI.addOperand(MCOperand::createImm(Imm)); 623 624 return MCDisassembler::Success; 625 } 626 627 template <typename InsnType> 628 static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, 629 uint64_t Address, 630 const void *Decoder) { 631 InsnType Rt = fieldFromInstruction(insn, 21, 5); 632 InsnType Rs = fieldFromInstruction(insn, 16, 5); 633 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; 634 635 if (Rs >= Rt) { 636 MI.setOpcode(Mips::BOVC_MMR6); 637 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 638 Rt))); 639 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 640 Rs))); 641 } else if (Rs != 0 && Rs < Rt) { 642 MI.setOpcode(Mips::BEQC_MMR6); 643 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 644 Rs))); 645 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 646 Rt))); 647 } else { 648 MI.setOpcode(Mips::BEQZALC_MMR6); 649 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 650 Rt))); 651 } 652 653 MI.addOperand(MCOperand::createImm(Imm)); 654 655 return MCDisassembler::Success; 656 } 657 658 template <typename InsnType> 659 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 660 uint64_t Address, 661 const void *Decoder) { 662 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 663 // (otherwise we would have matched the ADDI instruction from the earlier 664 // ISA's instead). 665 // 666 // We have: 667 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 668 // BNVC if rs >= rt 669 // BNEZALC if rs == 0 && rt != 0 670 // BNEC if rs < rt && rs != 0 671 672 InsnType Rs = fieldFromInstruction(insn, 21, 5); 673 InsnType Rt = fieldFromInstruction(insn, 16, 5); 674 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 675 bool HasRs = false; 676 677 if (Rs >= Rt) { 678 MI.setOpcode(Mips::BNVC); 679 HasRs = true; 680 } else if (Rs != 0 && Rs < Rt) { 681 MI.setOpcode(Mips::BNEC); 682 HasRs = true; 683 } else 684 MI.setOpcode(Mips::BNEZALC); 685 686 if (HasRs) 687 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 688 Rs))); 689 690 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 691 Rt))); 692 MI.addOperand(MCOperand::createImm(Imm)); 693 694 return MCDisassembler::Success; 695 } 696 697 template <typename InsnType> 698 static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, 699 uint64_t Address, 700 const void *Decoder) { 701 InsnType Rt = fieldFromInstruction(insn, 21, 5); 702 InsnType Rs = fieldFromInstruction(insn, 16, 5); 703 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; 704 705 if (Rs >= Rt) { 706 MI.setOpcode(Mips::BNVC_MMR6); 707 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 708 Rt))); 709 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 710 Rs))); 711 } else if (Rs != 0 && Rs < Rt) { 712 MI.setOpcode(Mips::BNEC_MMR6); 713 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 714 Rs))); 715 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 716 Rt))); 717 } else { 718 MI.setOpcode(Mips::BNEZALC_MMR6); 719 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 720 Rt))); 721 } 722 723 MI.addOperand(MCOperand::createImm(Imm)); 724 725 return MCDisassembler::Success; 726 } 727 728 template <typename InsnType> 729 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 730 uint64_t Address, 731 const void *Decoder) { 732 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 733 // (otherwise we would have matched the BLEZL instruction from the earlier 734 // ISA's instead). 735 // 736 // We have: 737 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 738 // Invalid if rs == 0 739 // BLEZC if rs == 0 && rt != 0 740 // BGEZC if rs == rt && rt != 0 741 // BGEC if rs != rt && rs != 0 && rt != 0 742 743 InsnType Rs = fieldFromInstruction(insn, 21, 5); 744 InsnType Rt = fieldFromInstruction(insn, 16, 5); 745 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 746 bool HasRs = false; 747 748 if (Rt == 0) 749 return MCDisassembler::Fail; 750 else if (Rs == 0) 751 MI.setOpcode(Mips::BLEZC); 752 else if (Rs == Rt) 753 MI.setOpcode(Mips::BGEZC); 754 else { 755 HasRs = true; 756 MI.setOpcode(Mips::BGEC); 757 } 758 759 if (HasRs) 760 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 761 Rs))); 762 763 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 764 Rt))); 765 766 MI.addOperand(MCOperand::createImm(Imm)); 767 768 return MCDisassembler::Success; 769 } 770 771 template <typename InsnType> 772 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 773 uint64_t Address, 774 const void *Decoder) { 775 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 776 // (otherwise we would have matched the BGTZL instruction from the earlier 777 // ISA's instead). 778 // 779 // We have: 780 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 781 // Invalid if rs == 0 782 // BGTZC if rs == 0 && rt != 0 783 // BLTZC if rs == rt && rt != 0 784 // BLTC if rs != rt && rs != 0 && rt != 0 785 786 bool HasRs = false; 787 788 InsnType Rs = fieldFromInstruction(insn, 21, 5); 789 InsnType Rt = fieldFromInstruction(insn, 16, 5); 790 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 791 792 if (Rt == 0) 793 return MCDisassembler::Fail; 794 else if (Rs == 0) 795 MI.setOpcode(Mips::BGTZC); 796 else if (Rs == Rt) 797 MI.setOpcode(Mips::BLTZC); 798 else { 799 MI.setOpcode(Mips::BLTC); 800 HasRs = true; 801 } 802 803 if (HasRs) 804 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 805 Rs))); 806 807 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 808 Rt))); 809 810 MI.addOperand(MCOperand::createImm(Imm)); 811 812 return MCDisassembler::Success; 813 } 814 815 template <typename InsnType> 816 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 817 uint64_t Address, 818 const void *Decoder) { 819 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 820 // (otherwise we would have matched the BGTZ instruction from the earlier 821 // ISA's instead). 822 // 823 // We have: 824 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 825 // BGTZ if rt == 0 826 // BGTZALC if rs == 0 && rt != 0 827 // BLTZALC if rs != 0 && rs == rt 828 // BLTUC if rs != 0 && rs != rt 829 830 InsnType Rs = fieldFromInstruction(insn, 21, 5); 831 InsnType Rt = fieldFromInstruction(insn, 16, 5); 832 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 833 bool HasRs = false; 834 bool HasRt = false; 835 836 if (Rt == 0) { 837 MI.setOpcode(Mips::BGTZ); 838 HasRs = true; 839 } else if (Rs == 0) { 840 MI.setOpcode(Mips::BGTZALC); 841 HasRt = true; 842 } else if (Rs == Rt) { 843 MI.setOpcode(Mips::BLTZALC); 844 HasRs = true; 845 } else { 846 MI.setOpcode(Mips::BLTUC); 847 HasRs = true; 848 HasRt = true; 849 } 850 851 if (HasRs) 852 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 853 Rs))); 854 855 if (HasRt) 856 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 857 Rt))); 858 859 MI.addOperand(MCOperand::createImm(Imm)); 860 861 return MCDisassembler::Success; 862 } 863 864 template <typename InsnType> 865 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 866 uint64_t Address, 867 const void *Decoder) { 868 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 869 // (otherwise we would have matched the BLEZL instruction from the earlier 870 // ISA's instead). 871 // 872 // We have: 873 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 874 // Invalid if rs == 0 875 // BLEZALC if rs == 0 && rt != 0 876 // BGEZALC if rs == rt && rt != 0 877 // BGEUC if rs != rt && rs != 0 && rt != 0 878 879 InsnType Rs = fieldFromInstruction(insn, 21, 5); 880 InsnType Rt = fieldFromInstruction(insn, 16, 5); 881 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 882 bool HasRs = false; 883 884 if (Rt == 0) 885 return MCDisassembler::Fail; 886 else if (Rs == 0) 887 MI.setOpcode(Mips::BLEZALC); 888 else if (Rs == Rt) 889 MI.setOpcode(Mips::BGEZALC); 890 else { 891 HasRs = true; 892 MI.setOpcode(Mips::BGEUC); 893 } 894 895 if (HasRs) 896 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 897 Rs))); 898 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 899 Rt))); 900 901 MI.addOperand(MCOperand::createImm(Imm)); 902 903 return MCDisassembler::Success; 904 } 905 906 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 907 /// according to the given endianess. 908 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 909 uint64_t &Size, uint32_t &Insn, 910 bool IsBigEndian) { 911 // We want to read exactly 2 Bytes of data. 912 if (Bytes.size() < 2) { 913 Size = 0; 914 return MCDisassembler::Fail; 915 } 916 917 if (IsBigEndian) { 918 Insn = (Bytes[0] << 8) | Bytes[1]; 919 } else { 920 Insn = (Bytes[1] << 8) | Bytes[0]; 921 } 922 923 return MCDisassembler::Success; 924 } 925 926 /// Read four bytes from the ArrayRef and return 32 bit word sorted 927 /// according to the given endianess 928 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 929 uint64_t &Size, uint32_t &Insn, 930 bool IsBigEndian, bool IsMicroMips) { 931 // We want to read exactly 4 Bytes of data. 932 if (Bytes.size() < 4) { 933 Size = 0; 934 return MCDisassembler::Fail; 935 } 936 937 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 938 // always precede the low 16 bits in the instruction stream (that is, they 939 // are placed at lower addresses in the instruction stream). 940 // 941 // microMIPS byte ordering: 942 // Big-endian: 0 | 1 | 2 | 3 943 // Little-endian: 1 | 0 | 3 | 2 944 945 if (IsBigEndian) { 946 // Encoded as a big-endian 32-bit word in the stream. 947 Insn = 948 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 949 } else { 950 if (IsMicroMips) { 951 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 952 (Bytes[1] << 24); 953 } else { 954 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 955 (Bytes[3] << 24); 956 } 957 } 958 959 return MCDisassembler::Success; 960 } 961 962 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 963 ArrayRef<uint8_t> Bytes, 964 uint64_t Address, 965 raw_ostream &VStream, 966 raw_ostream &CStream) const { 967 uint32_t Insn; 968 DecodeStatus Result; 969 970 if (IsMicroMips) { 971 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 972 if (Result == MCDisassembler::Fail) 973 return MCDisassembler::Fail; 974 975 if (hasMips32r6()) { 976 DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 977 // Calling the auto-generated decoder function for microMIPS32R6 978 // (and microMIPS64R6) 16-bit instructions. 979 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 980 Address, this, STI); 981 if (Result != MCDisassembler::Fail) { 982 Size = 2; 983 return Result; 984 } 985 } 986 987 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 988 // Calling the auto-generated decoder function for microMIPS 16-bit 989 // instructions. 990 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 991 this, STI); 992 if (Result != MCDisassembler::Fail) { 993 Size = 2; 994 return Result; 995 } 996 997 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 998 if (Result == MCDisassembler::Fail) 999 return MCDisassembler::Fail; 1000 1001 if (hasMips32r6()) { 1002 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 1003 // Calling the auto-generated decoder function. 1004 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 1005 this, STI); 1006 if (Result != MCDisassembler::Fail) { 1007 Size = 4; 1008 return Result; 1009 } 1010 } 1011 1012 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 1013 // Calling the auto-generated decoder function. 1014 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 1015 this, STI); 1016 if (Result != MCDisassembler::Fail) { 1017 Size = 4; 1018 return Result; 1019 } 1020 1021 if (hasMips32r6() && isFP64()) { 1022 DEBUG(dbgs() << "Trying MicroMips32r6FP64 table (32-bit opcodes):\n"); 1023 Result = decodeInstruction(DecoderTableMicroMips32r6FP6432, Instr, Insn, 1024 Address, this, STI); 1025 if (Result != MCDisassembler::Fail) { 1026 Size = 4; 1027 return Result; 1028 } 1029 } 1030 1031 // This is an invalid instruction. Let the disassembler move forward by the 1032 // minimum instruction size. 1033 Size = 2; 1034 return MCDisassembler::Fail; 1035 } 1036 1037 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 1038 if (Result == MCDisassembler::Fail) { 1039 Size = 4; 1040 return MCDisassembler::Fail; 1041 } 1042 1043 if (hasCOP3()) { 1044 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 1045 Result = 1046 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 1047 if (Result != MCDisassembler::Fail) { 1048 Size = 4; 1049 return Result; 1050 } 1051 } 1052 1053 if (hasMips32r6() && isGP64()) { 1054 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 1055 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 1056 Address, this, STI); 1057 if (Result != MCDisassembler::Fail) { 1058 Size = 4; 1059 return Result; 1060 } 1061 } 1062 1063 if (hasMips32r6() && isPTR64()) { 1064 DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1065 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn, 1066 Address, this, STI); 1067 if (Result != MCDisassembler::Fail) { 1068 Size = 4; 1069 return Result; 1070 } 1071 } 1072 1073 if (hasMips32r6()) { 1074 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 1075 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 1076 Address, this, STI); 1077 if (Result != MCDisassembler::Fail) { 1078 Size = 4; 1079 return Result; 1080 } 1081 } 1082 1083 if (hasMips2() && isPTR64()) { 1084 DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1085 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn, 1086 Address, this, STI); 1087 if (Result != MCDisassembler::Fail) { 1088 Size = 4; 1089 return Result; 1090 } 1091 } 1092 1093 if (hasCnMips()) { 1094 DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 1095 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 1096 Address, this, STI); 1097 if (Result != MCDisassembler::Fail) { 1098 Size = 4; 1099 return Result; 1100 } 1101 } 1102 1103 if (isGP64()) { 1104 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 1105 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 1106 Address, this, STI); 1107 if (Result != MCDisassembler::Fail) { 1108 Size = 4; 1109 return Result; 1110 } 1111 } 1112 1113 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 1114 // Calling the auto-generated decoder function. 1115 Result = 1116 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 1117 if (Result != MCDisassembler::Fail) { 1118 Size = 4; 1119 return Result; 1120 } 1121 1122 Size = 4; 1123 return MCDisassembler::Fail; 1124 } 1125 1126 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 1127 unsigned RegNo, 1128 uint64_t Address, 1129 const void *Decoder) { 1130 1131 return MCDisassembler::Fail; 1132 1133 } 1134 1135 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 1136 unsigned RegNo, 1137 uint64_t Address, 1138 const void *Decoder) { 1139 1140 if (RegNo > 31) 1141 return MCDisassembler::Fail; 1142 1143 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1144 Inst.addOperand(MCOperand::createReg(Reg)); 1145 return MCDisassembler::Success; 1146 } 1147 1148 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1149 unsigned RegNo, 1150 uint64_t Address, 1151 const void *Decoder) { 1152 if (RegNo > 7) 1153 return MCDisassembler::Fail; 1154 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1155 Inst.addOperand(MCOperand::createReg(Reg)); 1156 return MCDisassembler::Success; 1157 } 1158 1159 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1160 unsigned RegNo, 1161 uint64_t Address, 1162 const void *Decoder) { 1163 if (RegNo > 7) 1164 return MCDisassembler::Fail; 1165 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1166 Inst.addOperand(MCOperand::createReg(Reg)); 1167 return MCDisassembler::Success; 1168 } 1169 1170 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1171 unsigned RegNo, 1172 uint64_t Address, 1173 const void *Decoder) { 1174 if (RegNo > 7) 1175 return MCDisassembler::Fail; 1176 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1177 Inst.addOperand(MCOperand::createReg(Reg)); 1178 return MCDisassembler::Success; 1179 } 1180 1181 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1182 unsigned RegNo, 1183 uint64_t Address, 1184 const void *Decoder) { 1185 if (RegNo > 31) 1186 return MCDisassembler::Fail; 1187 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1188 Inst.addOperand(MCOperand::createReg(Reg)); 1189 return MCDisassembler::Success; 1190 } 1191 1192 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1193 unsigned RegNo, 1194 uint64_t Address, 1195 const void *Decoder) { 1196 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1197 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1198 1199 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1200 } 1201 1202 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1203 unsigned RegNo, 1204 uint64_t Address, 1205 const void *Decoder) { 1206 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1207 } 1208 1209 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1210 unsigned RegNo, 1211 uint64_t Address, 1212 const void *Decoder) { 1213 if (RegNo > 31) 1214 return MCDisassembler::Fail; 1215 1216 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1217 Inst.addOperand(MCOperand::createReg(Reg)); 1218 return MCDisassembler::Success; 1219 } 1220 1221 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1222 unsigned RegNo, 1223 uint64_t Address, 1224 const void *Decoder) { 1225 if (RegNo > 31) 1226 return MCDisassembler::Fail; 1227 1228 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1229 Inst.addOperand(MCOperand::createReg(Reg)); 1230 return MCDisassembler::Success; 1231 } 1232 1233 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1234 unsigned RegNo, 1235 uint64_t Address, 1236 const void *Decoder) { 1237 if (RegNo > 31) 1238 return MCDisassembler::Fail; 1239 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1240 Inst.addOperand(MCOperand::createReg(Reg)); 1241 return MCDisassembler::Success; 1242 } 1243 1244 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1245 unsigned RegNo, 1246 uint64_t Address, 1247 const void *Decoder) { 1248 if (RegNo > 7) 1249 return MCDisassembler::Fail; 1250 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1251 Inst.addOperand(MCOperand::createReg(Reg)); 1252 return MCDisassembler::Success; 1253 } 1254 1255 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1256 uint64_t Address, 1257 const void *Decoder) { 1258 if (RegNo > 31) 1259 return MCDisassembler::Fail; 1260 1261 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1262 Inst.addOperand(MCOperand::createReg(Reg)); 1263 return MCDisassembler::Success; 1264 } 1265 1266 static DecodeStatus DecodeMem(MCInst &Inst, 1267 unsigned Insn, 1268 uint64_t Address, 1269 const void *Decoder) { 1270 int Offset = SignExtend32<16>(Insn & 0xffff); 1271 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1272 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1273 1274 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1275 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1276 1277 if (Inst.getOpcode() == Mips::SC || 1278 Inst.getOpcode() == Mips::SCD) 1279 Inst.addOperand(MCOperand::createReg(Reg)); 1280 1281 Inst.addOperand(MCOperand::createReg(Reg)); 1282 Inst.addOperand(MCOperand::createReg(Base)); 1283 Inst.addOperand(MCOperand::createImm(Offset)); 1284 1285 return MCDisassembler::Success; 1286 } 1287 1288 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1289 unsigned Insn, 1290 uint64_t Address, 1291 const void *Decoder) { 1292 int Offset = SignExtend32<9>(Insn >> 7); 1293 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1294 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1295 1296 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1297 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1298 1299 if (Inst.getOpcode() == Mips::SCE) 1300 Inst.addOperand(MCOperand::createReg(Reg)); 1301 1302 Inst.addOperand(MCOperand::createReg(Reg)); 1303 Inst.addOperand(MCOperand::createReg(Base)); 1304 Inst.addOperand(MCOperand::createImm(Offset)); 1305 1306 return MCDisassembler::Success; 1307 } 1308 1309 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 1310 unsigned Insn, 1311 uint64_t Address, 1312 const void *Decoder) { 1313 int Offset = SignExtend32<9>(Insn & 0x1ff); 1314 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1315 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1316 1317 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1318 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1319 1320 Inst.addOperand(MCOperand::createReg(Reg)); 1321 Inst.addOperand(MCOperand::createReg(Base)); 1322 Inst.addOperand(MCOperand::createImm(Offset)); 1323 1324 return MCDisassembler::Success; 1325 } 1326 1327 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1328 unsigned Insn, 1329 uint64_t Address, 1330 const void *Decoder) { 1331 int Offset = SignExtend32<16>(Insn & 0xffff); 1332 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1333 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1334 1335 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1336 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1337 1338 Inst.addOperand(MCOperand::createReg(Reg)); 1339 Inst.addOperand(MCOperand::createReg(Base)); 1340 Inst.addOperand(MCOperand::createImm(Offset)); 1341 1342 return MCDisassembler::Success; 1343 } 1344 1345 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1346 unsigned Insn, 1347 uint64_t Address, 1348 const void *Decoder) { 1349 int Offset = SignExtend32<16>(Insn & 0xffff); 1350 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1351 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1352 1353 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1354 1355 Inst.addOperand(MCOperand::createReg(Base)); 1356 Inst.addOperand(MCOperand::createImm(Offset)); 1357 Inst.addOperand(MCOperand::createImm(Hint)); 1358 1359 return MCDisassembler::Success; 1360 } 1361 1362 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1363 unsigned Insn, 1364 uint64_t Address, 1365 const void *Decoder) { 1366 int Offset = SignExtend32<12>(Insn & 0xfff); 1367 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1368 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1369 1370 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1371 1372 Inst.addOperand(MCOperand::createReg(Base)); 1373 Inst.addOperand(MCOperand::createImm(Offset)); 1374 Inst.addOperand(MCOperand::createImm(Hint)); 1375 1376 return MCDisassembler::Success; 1377 } 1378 1379 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1380 unsigned Insn, 1381 uint64_t Address, 1382 const void *Decoder) { 1383 int Offset = SignExtend32<9>(Insn & 0x1ff); 1384 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1385 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1386 1387 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1388 1389 Inst.addOperand(MCOperand::createReg(Base)); 1390 Inst.addOperand(MCOperand::createImm(Offset)); 1391 Inst.addOperand(MCOperand::createImm(Hint)); 1392 1393 return MCDisassembler::Success; 1394 } 1395 1396 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1397 unsigned Insn, 1398 uint64_t Address, 1399 const void *Decoder) { 1400 int Offset = SignExtend32<9>(Insn >> 7); 1401 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1402 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1403 1404 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1405 1406 Inst.addOperand(MCOperand::createReg(Base)); 1407 Inst.addOperand(MCOperand::createImm(Offset)); 1408 Inst.addOperand(MCOperand::createImm(Hint)); 1409 1410 return MCDisassembler::Success; 1411 } 1412 1413 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 1414 unsigned Insn, 1415 uint64_t Address, 1416 const void *Decoder) { 1417 int Offset = SignExtend32<9>(Insn & 0x1ff); 1418 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1419 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1420 1421 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1422 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1423 1424 Inst.addOperand(MCOperand::createReg(Reg)); 1425 Inst.addOperand(MCOperand::createReg(Base)); 1426 Inst.addOperand(MCOperand::createImm(Offset)); 1427 1428 return MCDisassembler::Success; 1429 } 1430 1431 static DecodeStatus DecodeSyncI(MCInst &Inst, 1432 unsigned Insn, 1433 uint64_t Address, 1434 const void *Decoder) { 1435 int Offset = SignExtend32<16>(Insn & 0xffff); 1436 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1437 1438 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1439 1440 Inst.addOperand(MCOperand::createReg(Base)); 1441 Inst.addOperand(MCOperand::createImm(Offset)); 1442 1443 return MCDisassembler::Success; 1444 } 1445 1446 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1447 unsigned Insn, 1448 uint64_t Address, 1449 const void *Decoder) { 1450 int Immediate = SignExtend32<16>(Insn & 0xffff); 1451 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1452 1453 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1454 1455 Inst.addOperand(MCOperand::createReg(Base)); 1456 Inst.addOperand(MCOperand::createImm(Immediate)); 1457 1458 return MCDisassembler::Success; 1459 } 1460 1461 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1462 uint64_t Address, const void *Decoder) { 1463 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1464 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1465 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1466 1467 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1468 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1469 1470 Inst.addOperand(MCOperand::createReg(Reg)); 1471 Inst.addOperand(MCOperand::createReg(Base)); 1472 1473 // The immediate field of an LD/ST instruction is scaled which means it must 1474 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1475 // data format. 1476 // .b - 1 byte 1477 // .h - 2 bytes 1478 // .w - 4 bytes 1479 // .d - 8 bytes 1480 switch(Inst.getOpcode()) 1481 { 1482 default: 1483 assert (0 && "Unexpected instruction"); 1484 return MCDisassembler::Fail; 1485 break; 1486 case Mips::LD_B: 1487 case Mips::ST_B: 1488 Inst.addOperand(MCOperand::createImm(Offset)); 1489 break; 1490 case Mips::LD_H: 1491 case Mips::ST_H: 1492 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1493 break; 1494 case Mips::LD_W: 1495 case Mips::ST_W: 1496 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1497 break; 1498 case Mips::LD_D: 1499 case Mips::ST_D: 1500 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1501 break; 1502 } 1503 1504 return MCDisassembler::Success; 1505 } 1506 1507 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1508 unsigned Insn, 1509 uint64_t Address, 1510 const void *Decoder) { 1511 unsigned Offset = Insn & 0xf; 1512 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1513 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1514 1515 switch (Inst.getOpcode()) { 1516 case Mips::LBU16_MM: 1517 case Mips::LHU16_MM: 1518 case Mips::LW16_MM: 1519 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1520 == MCDisassembler::Fail) 1521 return MCDisassembler::Fail; 1522 break; 1523 case Mips::SB16_MM: 1524 case Mips::SB16_MMR6: 1525 case Mips::SH16_MM: 1526 case Mips::SH16_MMR6: 1527 case Mips::SW16_MM: 1528 case Mips::SW16_MMR6: 1529 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1530 == MCDisassembler::Fail) 1531 return MCDisassembler::Fail; 1532 break; 1533 } 1534 1535 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1536 == MCDisassembler::Fail) 1537 return MCDisassembler::Fail; 1538 1539 switch (Inst.getOpcode()) { 1540 case Mips::LBU16_MM: 1541 if (Offset == 0xf) 1542 Inst.addOperand(MCOperand::createImm(-1)); 1543 else 1544 Inst.addOperand(MCOperand::createImm(Offset)); 1545 break; 1546 case Mips::SB16_MM: 1547 case Mips::SB16_MMR6: 1548 Inst.addOperand(MCOperand::createImm(Offset)); 1549 break; 1550 case Mips::LHU16_MM: 1551 case Mips::SH16_MM: 1552 case Mips::SH16_MMR6: 1553 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1554 break; 1555 case Mips::LW16_MM: 1556 case Mips::SW16_MM: 1557 case Mips::SW16_MMR6: 1558 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1559 break; 1560 } 1561 1562 return MCDisassembler::Success; 1563 } 1564 1565 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1566 unsigned Insn, 1567 uint64_t Address, 1568 const void *Decoder) { 1569 unsigned Offset = Insn & 0x1F; 1570 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1571 1572 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1573 1574 Inst.addOperand(MCOperand::createReg(Reg)); 1575 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1576 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1577 1578 return MCDisassembler::Success; 1579 } 1580 1581 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1582 unsigned Insn, 1583 uint64_t Address, 1584 const void *Decoder) { 1585 unsigned Offset = Insn & 0x7F; 1586 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1587 1588 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1589 1590 Inst.addOperand(MCOperand::createReg(Reg)); 1591 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1592 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1593 1594 return MCDisassembler::Success; 1595 } 1596 1597 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1598 unsigned Insn, 1599 uint64_t Address, 1600 const void *Decoder) { 1601 int Offset; 1602 switch (Inst.getOpcode()) { 1603 case Mips::LWM16_MMR6: 1604 case Mips::SWM16_MMR6: 1605 Offset = fieldFromInstruction(Insn, 4, 4); 1606 break; 1607 default: 1608 Offset = SignExtend32<4>(Insn & 0xf); 1609 break; 1610 } 1611 1612 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1613 == MCDisassembler::Fail) 1614 return MCDisassembler::Fail; 1615 1616 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1617 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1618 1619 return MCDisassembler::Success; 1620 } 1621 1622 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1623 unsigned Insn, 1624 uint64_t Address, 1625 const void *Decoder) { 1626 int Offset = SignExtend32<9>(Insn & 0x1ff); 1627 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1628 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1629 1630 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1631 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1632 1633 if (Inst.getOpcode() == Mips::SCE_MM) 1634 Inst.addOperand(MCOperand::createReg(Reg)); 1635 1636 Inst.addOperand(MCOperand::createReg(Reg)); 1637 Inst.addOperand(MCOperand::createReg(Base)); 1638 Inst.addOperand(MCOperand::createImm(Offset)); 1639 1640 return MCDisassembler::Success; 1641 } 1642 1643 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1644 unsigned Insn, 1645 uint64_t Address, 1646 const void *Decoder) { 1647 int Offset = SignExtend32<12>(Insn & 0x0fff); 1648 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1649 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1650 1651 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1652 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1653 1654 switch (Inst.getOpcode()) { 1655 case Mips::SWM32_MM: 1656 case Mips::LWM32_MM: 1657 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1658 == MCDisassembler::Fail) 1659 return MCDisassembler::Fail; 1660 Inst.addOperand(MCOperand::createReg(Base)); 1661 Inst.addOperand(MCOperand::createImm(Offset)); 1662 break; 1663 case Mips::SC_MM: 1664 Inst.addOperand(MCOperand::createReg(Reg)); 1665 // fallthrough 1666 default: 1667 Inst.addOperand(MCOperand::createReg(Reg)); 1668 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM || 1669 Inst.getOpcode() == Mips::LWP_MMR6 || Inst.getOpcode() == Mips::SWP_MMR6) 1670 Inst.addOperand(MCOperand::createReg(Reg+1)); 1671 1672 Inst.addOperand(MCOperand::createReg(Base)); 1673 Inst.addOperand(MCOperand::createImm(Offset)); 1674 } 1675 1676 return MCDisassembler::Success; 1677 } 1678 1679 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1680 unsigned Insn, 1681 uint64_t Address, 1682 const void *Decoder) { 1683 int Offset = SignExtend32<16>(Insn & 0xffff); 1684 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1685 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1686 1687 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1688 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1689 1690 Inst.addOperand(MCOperand::createReg(Reg)); 1691 Inst.addOperand(MCOperand::createReg(Base)); 1692 Inst.addOperand(MCOperand::createImm(Offset)); 1693 1694 return MCDisassembler::Success; 1695 } 1696 1697 static DecodeStatus DecodeFMem(MCInst &Inst, 1698 unsigned Insn, 1699 uint64_t Address, 1700 const void *Decoder) { 1701 int Offset = SignExtend32<16>(Insn & 0xffff); 1702 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1703 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1704 1705 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1706 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1707 1708 Inst.addOperand(MCOperand::createReg(Reg)); 1709 Inst.addOperand(MCOperand::createReg(Base)); 1710 Inst.addOperand(MCOperand::createImm(Offset)); 1711 1712 return MCDisassembler::Success; 1713 } 1714 1715 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 1716 uint64_t Address, const void *Decoder) { 1717 // This function is the same as DecodeFMem but with the Reg and Base fields 1718 // swapped according to microMIPS spec. 1719 int Offset = SignExtend32<16>(Insn & 0xffff); 1720 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1721 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1722 1723 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1724 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1725 1726 Inst.addOperand(MCOperand::createReg(Reg)); 1727 Inst.addOperand(MCOperand::createReg(Base)); 1728 Inst.addOperand(MCOperand::createImm(Offset)); 1729 1730 return MCDisassembler::Success; 1731 } 1732 1733 static DecodeStatus DecodeFMem2(MCInst &Inst, 1734 unsigned Insn, 1735 uint64_t Address, 1736 const void *Decoder) { 1737 int Offset = SignExtend32<16>(Insn & 0xffff); 1738 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1739 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1740 1741 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1742 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1743 1744 Inst.addOperand(MCOperand::createReg(Reg)); 1745 Inst.addOperand(MCOperand::createReg(Base)); 1746 Inst.addOperand(MCOperand::createImm(Offset)); 1747 1748 return MCDisassembler::Success; 1749 } 1750 1751 static DecodeStatus DecodeFMem3(MCInst &Inst, 1752 unsigned Insn, 1753 uint64_t Address, 1754 const void *Decoder) { 1755 int Offset = SignExtend32<16>(Insn & 0xffff); 1756 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1757 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1758 1759 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1760 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1761 1762 Inst.addOperand(MCOperand::createReg(Reg)); 1763 Inst.addOperand(MCOperand::createReg(Base)); 1764 Inst.addOperand(MCOperand::createImm(Offset)); 1765 1766 return MCDisassembler::Success; 1767 } 1768 1769 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 1770 unsigned Insn, 1771 uint64_t Address, 1772 const void *Decoder) { 1773 int Offset = SignExtend32<11>(Insn & 0x07ff); 1774 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1775 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1776 1777 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1778 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1779 1780 Inst.addOperand(MCOperand::createReg(Reg)); 1781 Inst.addOperand(MCOperand::createReg(Base)); 1782 Inst.addOperand(MCOperand::createImm(Offset)); 1783 1784 return MCDisassembler::Success; 1785 } 1786 1787 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 1788 uint64_t Address, const void *Decoder) { 1789 int Offset = SignExtend32<11>(Insn & 0x07ff); 1790 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1791 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1792 1793 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1794 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1795 1796 Inst.addOperand(MCOperand::createReg(Reg)); 1797 Inst.addOperand(MCOperand::createReg(Base)); 1798 Inst.addOperand(MCOperand::createImm(Offset)); 1799 1800 return MCDisassembler::Success; 1801 } 1802 1803 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 1804 unsigned Insn, 1805 uint64_t Address, 1806 const void *Decoder) { 1807 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 1808 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 1809 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1810 1811 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 1812 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1813 1814 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 1815 Inst.addOperand(MCOperand::createReg(Rt)); 1816 } 1817 1818 Inst.addOperand(MCOperand::createReg(Rt)); 1819 Inst.addOperand(MCOperand::createReg(Base)); 1820 Inst.addOperand(MCOperand::createImm(Offset)); 1821 1822 return MCDisassembler::Success; 1823 } 1824 1825 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 1826 unsigned RegNo, 1827 uint64_t Address, 1828 const void *Decoder) { 1829 // Currently only hardware register 29 is supported. 1830 if (RegNo != 29) 1831 return MCDisassembler::Fail; 1832 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 1833 return MCDisassembler::Success; 1834 } 1835 1836 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 1837 unsigned RegNo, 1838 uint64_t Address, 1839 const void *Decoder) { 1840 if (RegNo > 30 || RegNo %2) 1841 return MCDisassembler::Fail; 1842 1843 ; 1844 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 1845 Inst.addOperand(MCOperand::createReg(Reg)); 1846 return MCDisassembler::Success; 1847 } 1848 1849 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 1850 unsigned RegNo, 1851 uint64_t Address, 1852 const void *Decoder) { 1853 if (RegNo >= 4) 1854 return MCDisassembler::Fail; 1855 1856 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 1857 Inst.addOperand(MCOperand::createReg(Reg)); 1858 return MCDisassembler::Success; 1859 } 1860 1861 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 1862 unsigned RegNo, 1863 uint64_t Address, 1864 const void *Decoder) { 1865 if (RegNo >= 4) 1866 return MCDisassembler::Fail; 1867 1868 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 1869 Inst.addOperand(MCOperand::createReg(Reg)); 1870 return MCDisassembler::Success; 1871 } 1872 1873 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 1874 unsigned RegNo, 1875 uint64_t Address, 1876 const void *Decoder) { 1877 if (RegNo >= 4) 1878 return MCDisassembler::Fail; 1879 1880 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 1881 Inst.addOperand(MCOperand::createReg(Reg)); 1882 return MCDisassembler::Success; 1883 } 1884 1885 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 1886 unsigned RegNo, 1887 uint64_t Address, 1888 const void *Decoder) { 1889 if (RegNo > 31) 1890 return MCDisassembler::Fail; 1891 1892 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 1893 Inst.addOperand(MCOperand::createReg(Reg)); 1894 return MCDisassembler::Success; 1895 } 1896 1897 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 1898 unsigned RegNo, 1899 uint64_t Address, 1900 const void *Decoder) { 1901 if (RegNo > 31) 1902 return MCDisassembler::Fail; 1903 1904 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 1905 Inst.addOperand(MCOperand::createReg(Reg)); 1906 return MCDisassembler::Success; 1907 } 1908 1909 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 1910 unsigned RegNo, 1911 uint64_t Address, 1912 const void *Decoder) { 1913 if (RegNo > 31) 1914 return MCDisassembler::Fail; 1915 1916 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 1917 Inst.addOperand(MCOperand::createReg(Reg)); 1918 return MCDisassembler::Success; 1919 } 1920 1921 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 1922 unsigned RegNo, 1923 uint64_t Address, 1924 const void *Decoder) { 1925 if (RegNo > 31) 1926 return MCDisassembler::Fail; 1927 1928 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 1929 Inst.addOperand(MCOperand::createReg(Reg)); 1930 return MCDisassembler::Success; 1931 } 1932 1933 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 1934 unsigned RegNo, 1935 uint64_t Address, 1936 const void *Decoder) { 1937 if (RegNo > 7) 1938 return MCDisassembler::Fail; 1939 1940 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 1941 Inst.addOperand(MCOperand::createReg(Reg)); 1942 return MCDisassembler::Success; 1943 } 1944 1945 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 1946 unsigned RegNo, 1947 uint64_t Address, 1948 const void *Decoder) { 1949 if (RegNo > 31) 1950 return MCDisassembler::Fail; 1951 1952 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 1953 Inst.addOperand(MCOperand::createReg(Reg)); 1954 return MCDisassembler::Success; 1955 } 1956 1957 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 1958 unsigned RegNo, 1959 uint64_t Address, 1960 const void *Decoder) { 1961 if (RegNo > 31) 1962 return MCDisassembler::Fail; 1963 1964 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 1965 Inst.addOperand(MCOperand::createReg(Reg)); 1966 return MCDisassembler::Success; 1967 } 1968 1969 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 1970 unsigned Offset, 1971 uint64_t Address, 1972 const void *Decoder) { 1973 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 1974 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1975 return MCDisassembler::Success; 1976 } 1977 1978 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 1979 unsigned Offset, 1980 uint64_t Address, 1981 const void *Decoder) { 1982 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2); 1983 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1984 return MCDisassembler::Success; 1985 } 1986 1987 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 1988 unsigned Insn, 1989 uint64_t Address, 1990 const void *Decoder) { 1991 1992 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 1993 Inst.addOperand(MCOperand::createImm(JumpOffset)); 1994 return MCDisassembler::Success; 1995 } 1996 1997 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 1998 unsigned Offset, 1999 uint64_t Address, 2000 const void *Decoder) { 2001 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2002 2003 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2004 return MCDisassembler::Success; 2005 } 2006 2007 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 2008 unsigned Offset, 2009 uint64_t Address, 2010 const void *Decoder) { 2011 int32_t BranchOffset = SignExtend32<21>(Offset) << 1; 2012 2013 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2014 return MCDisassembler::Success; 2015 } 2016 2017 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 2018 unsigned Offset, 2019 uint64_t Address, 2020 const void *Decoder) { 2021 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4; 2022 2023 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2024 return MCDisassembler::Success; 2025 } 2026 2027 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 2028 unsigned Offset, 2029 uint64_t Address, 2030 const void *Decoder) { 2031 int32_t BranchOffset = SignExtend32<7>(Offset) << 1; 2032 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2033 return MCDisassembler::Success; 2034 } 2035 2036 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 2037 unsigned Offset, 2038 uint64_t Address, 2039 const void *Decoder) { 2040 int32_t BranchOffset = SignExtend32<10>(Offset) << 1; 2041 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2042 return MCDisassembler::Success; 2043 } 2044 2045 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 2046 unsigned Offset, 2047 uint64_t Address, 2048 const void *Decoder) { 2049 int32_t BranchOffset = SignExtend32<16>(Offset) * 2; 2050 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2051 return MCDisassembler::Success; 2052 } 2053 2054 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 2055 unsigned Offset, 2056 uint64_t Address, 2057 const void *Decoder) { 2058 int32_t BranchOffset = SignExtend32<26>(Offset) << 1; 2059 2060 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2061 return MCDisassembler::Success; 2062 } 2063 2064 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 2065 unsigned Insn, 2066 uint64_t Address, 2067 const void *Decoder) { 2068 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 2069 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2070 return MCDisassembler::Success; 2071 } 2072 2073 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 2074 unsigned Value, 2075 uint64_t Address, 2076 const void *Decoder) { 2077 if (Value == 0) 2078 Inst.addOperand(MCOperand::createImm(1)); 2079 else if (Value == 0x7) 2080 Inst.addOperand(MCOperand::createImm(-1)); 2081 else 2082 Inst.addOperand(MCOperand::createImm(Value << 2)); 2083 return MCDisassembler::Success; 2084 } 2085 2086 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 2087 unsigned Value, 2088 uint64_t Address, 2089 const void *Decoder) { 2090 if (Value == 0x7F) 2091 Inst.addOperand(MCOperand::createImm(-1)); 2092 else 2093 Inst.addOperand(MCOperand::createImm(Value)); 2094 return MCDisassembler::Success; 2095 } 2096 2097 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 2098 unsigned Value, 2099 uint64_t Address, 2100 const void *Decoder) { 2101 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 2102 return MCDisassembler::Success; 2103 } 2104 2105 template <unsigned Bits, int Offset, int Scale> 2106 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2107 uint64_t Address, 2108 const void *Decoder) { 2109 Value &= ((1 << Bits) - 1); 2110 Value *= Scale; 2111 Inst.addOperand(MCOperand::createImm(Value + Offset)); 2112 return MCDisassembler::Success; 2113 } 2114 2115 template <unsigned Bits, int Offset, int ScaleBy> 2116 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2117 uint64_t Address, 2118 const void *Decoder) { 2119 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; 2120 Inst.addOperand(MCOperand::createImm(Imm + Offset)); 2121 return MCDisassembler::Success; 2122 } 2123 2124 static DecodeStatus DecodeInsSize(MCInst &Inst, 2125 unsigned Insn, 2126 uint64_t Address, 2127 const void *Decoder) { 2128 // First we need to grab the pos(lsb) from MCInst. 2129 int Pos = Inst.getOperand(2).getImm(); 2130 int Size = (int) Insn - Pos + 1; 2131 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 2132 return MCDisassembler::Success; 2133 } 2134 2135 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 2136 uint64_t Address, const void *Decoder) { 2137 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 2138 return MCDisassembler::Success; 2139 } 2140 2141 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 2142 uint64_t Address, const void *Decoder) { 2143 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 2144 return MCDisassembler::Success; 2145 } 2146 2147 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 2148 uint64_t Address, const void *Decoder) { 2149 int32_t DecodedValue; 2150 switch (Insn) { 2151 case 0: DecodedValue = 256; break; 2152 case 1: DecodedValue = 257; break; 2153 case 510: DecodedValue = -258; break; 2154 case 511: DecodedValue = -257; break; 2155 default: DecodedValue = SignExtend32<9>(Insn); break; 2156 } 2157 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 2158 return MCDisassembler::Success; 2159 } 2160 2161 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 2162 uint64_t Address, const void *Decoder) { 2163 // Insn must be >= 0, since it is unsigned that condition is always true. 2164 assert(Insn < 16); 2165 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 2166 255, 32768, 65535}; 2167 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 2168 return MCDisassembler::Success; 2169 } 2170 2171 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 2172 unsigned Insn, 2173 uint64_t Address, 2174 const void *Decoder) { 2175 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2176 Mips::S6, Mips::S7, Mips::FP}; 2177 unsigned RegNum; 2178 2179 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2180 2181 // Empty register lists are not allowed. 2182 if (RegLst == 0) 2183 return MCDisassembler::Fail; 2184 2185 RegNum = RegLst & 0xf; 2186 2187 // RegLst values 10-15, and 26-31 are reserved. 2188 if (RegNum > 9) 2189 return MCDisassembler::Fail; 2190 2191 for (unsigned i = 0; i < RegNum; i++) 2192 Inst.addOperand(MCOperand::createReg(Regs[i])); 2193 2194 if (RegLst & 0x10) 2195 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2196 2197 return MCDisassembler::Success; 2198 } 2199 2200 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2201 uint64_t Address, 2202 const void *Decoder) { 2203 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2204 unsigned RegLst; 2205 switch(Inst.getOpcode()) { 2206 default: 2207 RegLst = fieldFromInstruction(Insn, 4, 2); 2208 break; 2209 case Mips::LWM16_MMR6: 2210 case Mips::SWM16_MMR6: 2211 RegLst = fieldFromInstruction(Insn, 8, 2); 2212 break; 2213 } 2214 unsigned RegNum = RegLst & 0x3; 2215 2216 for (unsigned i = 0; i <= RegNum; i++) 2217 Inst.addOperand(MCOperand::createReg(Regs[i])); 2218 2219 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2220 2221 return MCDisassembler::Success; 2222 } 2223 2224 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 2225 uint64_t Address, const void *Decoder) { 2226 2227 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 2228 2229 switch (RegPair) { 2230 default: 2231 return MCDisassembler::Fail; 2232 case 0: 2233 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2234 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2235 break; 2236 case 1: 2237 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2238 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2239 break; 2240 case 2: 2241 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2242 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2243 break; 2244 case 3: 2245 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2246 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2247 break; 2248 case 4: 2249 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2250 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2251 break; 2252 case 5: 2253 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2254 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2255 break; 2256 case 6: 2257 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2258 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2259 break; 2260 case 7: 2261 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2262 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2263 break; 2264 } 2265 2266 return MCDisassembler::Success; 2267 } 2268 2269 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2270 uint64_t Address, const void *Decoder) { 2271 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2272 return MCDisassembler::Success; 2273 } 2274 2275 template <typename InsnType> 2276 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, 2277 uint64_t Address, 2278 const void *Decoder) { 2279 // We have: 2280 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii 2281 // Invalid if rt == 0 2282 // BGTZALC_MMR6 if rs == 0 && rt != 0 2283 // BLTZALC_MMR6 if rs != 0 && rs == rt 2284 // BLTUC_MMR6 if rs != 0 && rs != rt 2285 2286 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2287 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2288 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; 2289 bool HasRs = false; 2290 bool HasRt = false; 2291 2292 if (Rt == 0) 2293 return MCDisassembler::Fail; 2294 else if (Rs == 0) { 2295 MI.setOpcode(Mips::BGTZALC_MMR6); 2296 HasRt = true; 2297 } 2298 else if (Rs == Rt) { 2299 MI.setOpcode(Mips::BLTZALC_MMR6); 2300 HasRs = true; 2301 } 2302 else { 2303 MI.setOpcode(Mips::BLTUC_MMR6); 2304 HasRs = true; 2305 HasRt = true; 2306 } 2307 2308 if (HasRs) 2309 MI.addOperand( 2310 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2311 2312 if (HasRt) 2313 MI.addOperand( 2314 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2315 2316 MI.addOperand(MCOperand::createImm(Imm)); 2317 2318 return MCDisassembler::Success; 2319 } 2320 2321 template <typename InsnType> 2322 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, 2323 uint64_t Address, 2324 const void *Decoder) { 2325 // We have: 2326 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii 2327 // Invalid if rs == 0 2328 // BLEZALC_MMR6 if rs == 0 && rt != 0 2329 // BGEZALC_MMR6 if rs == rt && rt != 0 2330 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 2331 2332 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2333 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2334 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; 2335 bool HasRs = false; 2336 2337 if (Rt == 0) 2338 return MCDisassembler::Fail; 2339 else if (Rs == 0) 2340 MI.setOpcode(Mips::BLEZALC_MMR6); 2341 else if (Rs == Rt) 2342 MI.setOpcode(Mips::BGEZALC_MMR6); 2343 else { 2344 HasRs = true; 2345 MI.setOpcode(Mips::BGEUC_MMR6); 2346 } 2347 2348 if (HasRs) 2349 MI.addOperand( 2350 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2351 MI.addOperand( 2352 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2353 2354 MI.addOperand(MCOperand::createImm(Imm)); 2355 2356 return MCDisassembler::Success; 2357 } 2358
