| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) {
74 switch ((Imm >> 6) & 0x7) {
85 static inline unsigned getShiftValue(unsigned Imm) {
86 return Imm & 0x3f;
90 /// imm: 6-bit shift amount
97 /// {5-0} = imm
99 unsigned Imm) {
100 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!");
110 return (STEnc << 6) | (Imm & 0x3f)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 105 // reg [asr|lsl|lsr|ror|rrx] imm
108 // reg, the second is the shift amount (or reg0 if not present or imm). The
109 // third operand encodes the shift opcode and the imm if a reg isn't present.
111 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
112 return ShOp | (Imm << 3);
121 /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
122 /// the 8-bit imm value.
123 static inline unsigned getSOImmValImm(unsigned Imm) {
124 return Imm & 0xFF
[all...] |
| /external/capstone/arch/AArch64/ |
| AArch64AddressingModes.h | 69 static inline AArch64_AM_ShiftExtendType AArch64_AM_getShiftType(unsigned Imm)
71 switch ((Imm >> 6) & 0x7) {
82 static inline unsigned AArch64_AM_getShiftValue(unsigned Imm)
84 return Imm & 0x3f;
92 static inline unsigned AArch64_AM_getArithShiftValue(unsigned Imm)
94 return Imm & 0x7;
98 static inline AArch64_AM_ShiftExtendType AArch64_AM_getExtendType(unsigned Imm)
100 // assert((Imm & 0x7) == Imm && "invalid immediate!");
101 switch (Imm) {
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZTargetTransformInfo.cpp | 34 int SystemZTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
46 if (Imm == 0)
49 if (Imm.getBitWidth() <= 64) {
51 if (isInt<32>(Imm.getSExtValue()))
54 if (isUInt<32>(Imm.getZExtValue()))
57 if ((Imm.getZExtValue() & 0xffffffff) == 0)
67 const APInt &Imm, Type *Ty) {
90 if (Idx == 0 && Imm.getBitWidth() <= 64) {
95 if (isInt<16>(Imm.getSExtValue()))
100 if (Idx == 1 && Imm.getBitWidth() <= 64)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/Utils/ |
| X86ShuffleDecode.h | 30 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<unsigned> &ShuffleMask);
40 void DecodePSHUFMask(unsigned NElts, unsigned Imm,
43 void DecodePSHUFHWMask(unsigned Imm,
46 void DecodePSHUFLWMask(unsigned Imm,
67 void DecodeSHUFPSMask(unsigned NElts, unsigned Imm,
90 void DecodeVPERMILPSMask(unsigned NElts, unsigned Imm,
97 void DecodeVPERMILPDMask(unsigned NElts, unsigned Imm,
100 void DecodeVPERM2F128Mask(unsigned Imm,
102 void DecodeVPERM2F128Mask(EVT VT, unsigned Imm,
|
| X86ShuffleDecode.cpp | 23 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<unsigned> &ShuffleMask) {
31 unsigned ZMask = Imm & 15;
32 unsigned CountD = (Imm >> 4) & 3;
33 unsigned CountS = (Imm >> 6) & 3;
66 void DecodePSHUFMask(unsigned NElts, unsigned Imm,
69 ShuffleMask.push_back(Imm % NElts);
70 Imm /= NElts;
74 void DecodePSHUFHWMask(unsigned Imm,
81 ShuffleMask.push_back(4+(Imm & 3));
82 Imm >>= 2
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsAnalyzeImmediate.cpp | 29 void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize,
31 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs);
32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL));
35 void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize,
37 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs);
38 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL));
41 void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize,
43 unsigned Shamt = countTrailingZeros(Imm);
44 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs);
48 void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigned RemSize
[all...] |
| MipsISelDAGToDAG.h | 56 /// (reg + imm).
88 virtual bool selectVSplat(SDNode *N, APInt &Imm,
91 virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const;
93 virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const;
95 virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const;
97 virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const;
99 virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const;
101 virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const;
103 virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const;
105 virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const
[all...] |
| MipsAnalyzeImmediate.h | 25 /// Analyze - Get an instruction sequence to load immediate Imm. The last
28 const InstSeq &Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu);
36 /// load immediate Imm
37 void GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
40 /// load immediate Imm
41 void GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
44 /// load immediate Imm
45 void GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
47 /// GetInstSeqLs - Get instruction sequences to load immediate Imm.
48 void GetInstSeqLs(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs)
[all...] |
| MipsSEISelDAGToDAG.h | 89 bool selectVSplat(SDNode *N, APInt &Imm,
92 bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
95 bool selectVSplatUimm1(SDValue N, SDValue &Imm) const override;
97 bool selectVSplatUimm2(SDValue N, SDValue &Imm) const override;
99 bool selectVSplatUimm3(SDValue N, SDValue &Imm) const override;
101 bool selectVSplatUimm4(SDValue N, SDValue &Imm) const override;
103 bool selectVSplatUimm5(SDValue N, SDValue &Imm) const override;
105 bool selectVSplatUimm6(SDValue N, SDValue &Imm) const override;
107 bool selectVSplatUimm8(SDValue N, SDValue &Imm) const override;
109 bool selectVSplatSimm5(SDValue N, SDValue &Imm) const override
[all...] |
| MipsISelDAGToDAG.cpp | 129 bool MipsDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm,
135 bool MipsDAGToDAGISel::selectVSplatUimm1(SDValue N, SDValue &Imm) const {
140 bool MipsDAGToDAGISel::selectVSplatUimm2(SDValue N, SDValue &Imm) const {
145 bool MipsDAGToDAGISel::selectVSplatUimm3(SDValue N, SDValue &Imm) const {
150 bool MipsDAGToDAGISel::selectVSplatUimm4(SDValue N, SDValue &Imm) const {
155 bool MipsDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &Imm) const {
160 bool MipsDAGToDAGISel::selectVSplatUimm6(SDValue N, SDValue &Imm) const {
165 bool MipsDAGToDAGISel::selectVSplatUimm8(SDValue N, SDValue &Imm) const {
170 bool MipsDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &Imm) const {
175 bool MipsDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const
[all...] |
| /external/capstone/arch/ARM/ |
| ARMAddressingModes.h | 109 // reg [asr|lsl|lsr|ror|rrx] imm
112 // reg, the second is the shift amount (or reg0 if not present or imm). The
113 // third operand encodes the shift opcode and the imm if a reg isn't present.
115 static inline unsigned getSORegOpc(ARM_AM_ShiftOpc ShOp, unsigned Imm)
117 return ShOp | (Imm << 3);
130 /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
131 /// the 8-bit imm value.
132 static inline unsigned getSOImmValImm(unsigned Imm)
134 return Imm & 0xFF
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 106 // reg [asr|lsl|lsr|ror|rrx] imm
109 // reg, the second is the shift amount (or reg0 if not present or imm). The
110 // third operand encodes the shift opcode and the imm if a reg isn't present.
112 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
113 return ShOp | (Imm << 3);
122 /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
123 /// the 8-bit imm value.
124 static inline unsigned getSOImmValImm(unsigned Imm) {
125 return Imm & 0xFF
[all...] |
| /external/llvm/lib/MC/ |
| MCInstrAnalysis.cpp | 19 int64_t Imm = Inst.getOperand(0).getImm();
20 Target = Addr+Size+Imm;
|
| /external/swiftshader/third_party/LLVM/lib/MC/ |
| MCInstrAnalysis.cpp | 19 int64_t Imm = Inst.getOperand(0).getImm();
20 return Addr+Size+Imm;
|
| /external/llvm/lib/Target/X86/Utils/ |
| X86ShuffleDecode.h | 31 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
52 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
54 void DecodePSRLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
56 void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
61 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
66 void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
71 void DecodePSHUFLWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
79 void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
101 void DecodeBLENDMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
103 void DecodeVPERM2X128Mask(MVT VT, unsigned Imm,
[all...] |
| /external/llvm/test/MC/Mips/ |
| sym-expr.s | 11 jal __start + 0x4 # CHECK: instruction: [jal, Imm<__start+4>]
12 jal __start + (-0x10) # CHECK: instruction: [jal, Imm<__start-16>]
13 jal (__start + (-0x10)) # CHECK: instruction: [jal, Imm<__start-16>]
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonInstPrinter.cpp | 130 int64_t Imm;
131 bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm);
132 Imm = SignExtend64<9>(Imm);
134 assert(((Imm & 0x3f) == 0) && "Lower 6 bits must be ZERO.");
135 O << formatImm(Imm/64);
140 int64_t Imm;
141 bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm);
142 Imm = SignExtend64<10>(Imm);
[all...] |
| /external/llvm/test/MC/Lanai/ |
| memory.s | 12 ! CHECK-NEXT: <MCOperand Imm:0>
13 ! CHECK-NEXT: <MCOperand Imm:0>
20 ! CHECK-NEXT: <MCOperand Imm:0>
21 ! CHECK-NEXT: <MCOperand Imm:0>
28 ! CHECK-NEXT: <MCOperand Imm:0>
29 ! CHECK-NEXT: <MCOperand Imm:0>
36 ! CHECK-NEXT: <MCOperand Imm:291>
37 ! CHECK-NEXT: <MCOperand Imm:128>
44 ! CHECK-NEXT: <MCOperand Imm:-4>
45 ! CHECK-NEXT: <MCOperand Imm:128
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCTargetTransformInfo.cpp | 45 int PPCTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
47 return BaseT::getIntImmCost(Imm, Ty);
55 if (Imm == 0)
58 if (Imm.getBitWidth() <= 64) {
59 if (isInt<16>(Imm.getSExtValue()))
62 if (isInt<32>(Imm.getSExtValue())) {
64 if ((Imm.getZExtValue() & 0xFFFF) == 0)
74 int PPCTTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
77 return BaseT::getIntImmCost(IID, Idx, Imm, Ty);
92 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<16>(Imm.getSExtValue())
[all...] |
| /external/capstone/arch/SystemZ/ |
| SystemZDisassembler.c | 96 static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm)
98 //assert(isUInt<N>(Imm) && "Invalid immediate");
99 MCOperand_CreateImm0(Inst, Imm);
103 static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm, unsigned N)
105 //assert(isUInt<N>(Imm) && "Invalid immediate");
106 MCOperand_CreateImm0(Inst, SignExtend64(Imm, N));
110 static DecodeStatus decodeAccessRegOperand(MCInst *Inst, uint64_t Imm,
113 return decodeUImmOperand(Inst, Imm);
116 static DecodeStatus decodeU4ImmOperand(MCInst *Inst, uint64_t Imm,
119 return decodeUImmOperand(Inst, Imm);
[all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.cpp | 74 int64_t Imm = MI->getOperand(Op).getImm();
75 switch (Imm) {
114 int64_t Imm = MI->getOperand(Op).getImm();
115 switch (Imm) {
130 int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
131 switch (Imm) {
169 int64_t Imm = Op.getImm();
170 O << markup("<imm:") << '$' << formatImm(Imm) << markup(">");
178 if (CommentStream && !HasCustomInstComment && (Imm > 255 || Imm < -256))
[all...] |
| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| SystemZDisassembler.cpp | 154 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) {
155 if (!isUInt<N>(Imm))
157 Inst.addOperand(MCOperand::createImm(Imm));
162 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) {
163 if (!isUInt<N>(Imm))
165 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
169 static DecodeStatus decodeAccessRegOperand(MCInst &Inst, uint64_t Imm,
172 return decodeUImmOperand<4>(Inst, Imm);
175 static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm,
177 return decodeUImmOperand<1>(Inst, Imm);
[all...] |
| /external/llvm/lib/Target/AMDGPU/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 101 uint16_t Imm = MI->getOperand(OpNo).getImm();
102 if (Imm != 0) {
307 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm, raw_ostream &O) {
308 int32_t SImm = static_cast<int32_t>(Imm);
314 if (Imm == FloatToBits(0.0f))
316 else if (Imm == FloatToBits(1.0f))
318 else if (Imm == FloatToBits(-1.0f))
320 else if (Imm == FloatToBits(0.5f))
322 else if (Imm == FloatToBits(-0.5f))
324 else if (Imm == FloatToBits(2.0f)
[all...] |
| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 89 static uint32_t getIntInlineImmEncoding(IntTy Imm) {
90 if (Imm >= 0 && Imm <= 64)
91 return 128 + Imm;
93 if (Imm >= -16 && Imm <= -1)
94 return 192 + std::abs(Imm);
166 int64_t Imm;
172 Imm = C->getValue();
180 Imm = MO.getImm()
[all...] |
