| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.h | 70 virtual uint32_t reg_reg(int Rm, int type, int Rs);
94 int Rd, int Rm, int Rs, int Rn);
96 int Rd, int Rm, int Rs);
98 int RdLo, int RdHi, int Rm, int Rs);
100 int RdLo, int RdHi, int Rm, int Rs);
102 int RdLo, int RdHi, int Rm, int Rs);
104 int RdLo, int RdHi, int Rm, int Rs);
148 int Rd, int Rm, int Rs);
150 int Rd, int Rm, int Rs);
152 int Rd, int Rm, int Rs, int Rn)
[all...] |
| ARMAssemblerInterface.h | 83 virtual uint32_t reg_reg(int Rm, int type, int Rs) = 0;
129 int Rd, int Rm, int Rs, int Rn) = 0;
131 int Rd, int Rm, int Rs) = 0;
133 int RdLo, int RdHi, int Rm, int Rs) = 0;
135 int RdLo, int RdHi, int Rm, int Rs) = 0;
137 int RdLo, int RdHi, int Rm, int Rs) = 0;
139 int RdLo, int RdHi, int Rm, int Rs) = 0;
205 int Rd, int Rm, int Rs) = 0;
207 int Rd, int Rm, int Rs) = 0;
209 int Rd, int Rm, int Rs, int Rn) = 0
[all...] |
| MIPSAssembler.cpp | 247 int Rs __unused)
608 int Rd, int Rm, int Rs, int Rn) {
612 mMips->MUL(R_at, Rm, Rs);
621 int Rd, int Rm, int Rs) {
623 mMips->MUL(Rd, Rm, Rs);
631 int RdLo, int RdHi, int Rm, int Rs) {
633 mMips->MULT(Rm, Rs);
644 int RdLo __unused, int RdHi, int Rm __unused, int Rs __unused) {
646 "UMUAL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs);
648 // (RdHi<<16) | (RdLo<<12) | (Rs<<8) | 0x90 | Rm
[all...] |
| ARMAssemblerProxy.cpp | 103 uint32_t ARMAssemblerProxy::reg_reg(int Rm, int type, int Rs)
105 return mTarget->reg_reg(Rm, type, Rs);
166 void ARMAssemblerProxy::MLA(int cc, int s, int Rd, int Rm, int Rs, int Rn) {
167 mTarget->MLA(cc, s, Rd, Rm, Rs, Rn);
169 void ARMAssemblerProxy::MUL(int cc, int s, int Rd, int Rm, int Rs) {
170 mTarget->MUL(cc, s, Rd, Rm, Rs);
173 int RdLo, int RdHi, int Rm, int Rs) {
174 mTarget->UMULL(cc, s, RdLo, RdHi, Rm, Rs);
177 int RdLo, int RdHi, int Rm, int Rs) {
178 mTarget->UMUAL(cc, s, RdLo, RdHi, Rm, Rs);
[all...] |
| ARMAssembler.cpp | 215 int Rd, int Rm, int Rs, int Rn) {
216 if (Rd == Rm) { int t = Rm; Rm=Rs; Rs=t; }
217 LOG_FATAL_IF(Rd==Rm, "MLA(r%u,r%u,r%u,r%u)", Rd,Rm,Rs,Rn);
219 (Rd<<16) | (Rn<<12) | (Rs<<8) | 0x90 | Rm;
222 int Rd, int Rm, int Rs) {
223 if (Rd == Rm) { int t = Rm; Rm=Rs; Rs=t; }
224 LOG_FATAL_IF(Rd==Rm, "MUL(r%u,r%u,r%u)", Rd,Rm,Rs);
225 *mPC++ = (cc<<28) | (s<<20) | (Rd<<16) | (Rs<<8) | 0x90 | Rm
[all...] |
| ARMAssembler.h | 72 virtual uint32_t reg_reg(int Rm, int type, int Rs);
94 int Rd, int Rm, int Rs, int Rn);
96 int Rd, int Rm, int Rs);
98 int RdLo, int RdHi, int Rm, int Rs);
100 int RdLo, int RdHi, int Rm, int Rs);
102 int RdLo, int RdHi, int Rm, int Rs);
104 int RdLo, int RdHi, int Rm, int Rs);
149 int Rd, int Rm, int Rs);
151 int Rd, int Rm, int Rs);
153 int Rd, int Rm, int Rs, int Rn)
[all...] |
| ARMAssemblerProxy.h | 61 virtual uint32_t reg_reg(int Rm, int type, int Rs);
83 int Rd, int Rm, int Rs, int Rn);
85 int Rd, int Rm, int Rs);
87 int RdLo, int RdHi, int Rm, int Rs);
89 int RdLo, int RdHi, int Rm, int Rs);
91 int RdLo, int RdHi, int Rm, int Rs);
93 int RdLo, int RdHi, int Rm, int Rs);
136 int Rd, int Rm, int Rs);
138 int Rd, int Rm, int Rs);
140 int Rd, int Rm, int Rs, int Rn)
[all...] |
| MIPS64Assembler.h | 75 virtual uint32_t reg_reg(int Rm, int type, int Rs);
99 int Rd, int Rm, int Rs, int Rn);
101 int Rd, int Rm, int Rs);
103 int RdLo, int RdHi, int Rm, int Rs);
105 int RdLo, int RdHi, int Rm, int Rs);
107 int RdLo, int RdHi, int Rm, int Rs);
109 int RdLo, int RdHi, int Rm, int Rs);
153 int Rd, int Rm, int Rs);
155 int Rd, int Rm, int Rs);
157 int Rd, int Rm, int Rs, int Rn)
[all...] |
| MIPS64Assembler.cpp | 236 int Rs __unused)
595 int Rd, int Rm, int Rs, int Rn) {
600 mMips->MUL(R_at, Rm, Rs);
609 int Rd, int Rm, int Rs) {
611 mMips->MUL(Rd, Rm, Rs);
619 int RdLo, int RdHi, int Rm, int Rs) {
621 mMips->MUH(RdHi, Rm, Rs);
622 mMips->MUL(RdLo, Rm, Rs);
632 int RdLo __unused, int RdHi, int Rm __unused, int Rs __unused) {
634 "UMUAL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs);
[all...] |
| Arm64Assembler.h | 85 virtual uint32_t reg_reg(int Rm, int type, int Rs);
102 int Rd, int Rm, int Rs, int Rn);
104 int Rd, int Rm, int Rs);
106 int RdLo, int RdHi, int Rm, int Rs);
108 int RdLo, int RdHi, int Rm, int Rs);
110 int RdLo, int RdHi, int Rm, int Rs);
112 int RdLo, int RdHi, int Rm, int Rs);
166 int Rd, int Rm, int Rs);
168 int Rd, int Rm, int Rs);
170 int Rd, int Rm, int Rs, int Rn)
[all...] |
| Arm64Assembler.cpp | 518 void ArmToArm64Assembler::MLA(int cc, int s,int Rd, int Rm, int Rs, int Rn)
522 *mPC++ = A64_MADD_W(Rd, Rm, Rs, Rn);
526 void ArmToArm64Assembler::MUL(int cc, int s, int Rd, int Rm, int Rs)
530 *mPC++ = A64_MADD_W(Rd, Rm, Rs, mZeroReg);
533 int /*RdLo*/, int /*RdHi*/, int /*Rm*/, int /*Rs*/)
538 int /*RdLo*/, int /*RdHi*/, int /*Rm*/, int /*Rs*/)
543 int /*RdLo*/, int /*RdHi*/, int /*Rm*/, int /*Rs*/)
548 int /*RdLo*/, int /*RdHi*/, int /*Rm*/, int /*Rs*/)
774 int Rd, int Rm, int Rs)
784 *mPC++ = A64_SBFM_W(mTmpReg2, Rs, 16, 31)
[all...] |
| GGLAssembler.cpp | 390 int Rs = scratches.obtain();
392 CONTEXT_LOAD(Rs, state.buffers.color.stride);
394 SMLABB(AL, Rs, Ry, Rs, Rx); // Rs = Rx + Ry*Rs
395 base_offset(parts.cbPtr, parts.cbPtr, Rs);
396 scratches.recycle(Rs);
426 int Rs = dzdx;
428 CONTEXT_LOAD(Rs, state.buffers.depth.stride)
[all...] |
| /external/mesa3d/src/gallium/state_trackers/clover/util/ |
| algorithm.hpp | 74 template<typename... Rs>
75 adaptor_range<zips, Rs...>
76 zip(Rs &&... rs) {
77 return map(zips(), std::forward<Rs>(rs)...);
95 /// \a rs.
100 template<typename F, typename... Rs>
102 for_each(F &&f, Rs &&... rs) {
[all...] |
| range.hpp | 244 template<typename G, typename... Rs>
245 adaptor_range(G &&f, Rs &&... os) :
246 f(std::forward<G>(f)), os(std::forward<Rs>(os)...) {
367 /// source ranges \a rs element-wise using a provided functor \a f.
371 template<typename F, typename... Rs>
372 adaptor_range<F, Rs...>
373 map(F &&f, Rs &&... rs) {
374 return { std::forward<F>(f), std::forward<Rs>(rs)... }
[all...] |
| /prebuilts/go/darwin-x86/src/runtime/ |
| vlop_arm.s | 100 #define Rs R2 // three temporary variables
110 CLZ Rq, Rs // find normalizing shift
111 MOVW.S Rq<<Rs, Ra
116 SUB.S $7, Rs
118 MOVW.PL Ra<<Rs, Rq
128 MOVW.NE $0, Rs
129 MULAL.NE Rq, Ra, (Rq,Rs)
133 MULLU Rq, Rr, (Rq,Rs) // q = (r * q) >> 32
147 DIVUHW Rq, Rr, Rs
148 MUL Rs, Rq, R
[all...] |
| /prebuilts/go/linux-x86/src/runtime/ |
| vlop_arm.s | 100 #define Rs R2 // three temporary variables
110 CLZ Rq, Rs // find normalizing shift
111 MOVW.S Rq<<Rs, Ra
116 SUB.S $7, Rs
118 MOVW.PL Ra<<Rs, Rq
128 MOVW.NE $0, Rs
129 MULAL.NE Rq, Ra, (Rq,Rs)
133 MULLU Rq, Rr, (Rq,Rs) // q = (r * q) >> 32
147 DIVUHW Rq, Rr, Rs
148 MUL Rs, Rq, R
[all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCCompound.cpp | 113 // P0 = cmp.eq(Rs,#u2)
125 // Rd = Rs
166 // Rd=Rs ; jump #r9:2
207 MCOperand Rs, Rt;
229 Rs = L.getOperand(1);
235 CompoundInsn->addOperand(Rs);
242 Rs = L.getOperand(1);
248 CompoundInsn->addOperand(Rs);
255 Rs = L.getOperand(1);
261 CompoundInsn->addOperand(Rs);
[all...] |
| /toolchain/binutils/binutils-2.27/opcodes/ |
| aarch64-tbl.h | [all...] |
| /device/linaro/bootloader/edk2/BaseTools/Source/Python/Table/ |
| Table.py | 58 for Rs in self.Cur:
59 EdkLogger.verbose(str(Rs))
|
| /external/capstone/arch/Mips/ |
| MipsDisassembler.c | 532 // BOVC if rs >= rt
533 // BEQZALC if rs == 0 && rt != 0
534 // BEQC if rs < rt && rs != 0
536 uint32_t Rs = fieldFromInstruction(insn, 21, 5);
541 if (Rs >= Rt) {
544 } else if (Rs != 0 && Rs < Rt) {
551 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
568 // BNVC if rs >= r
[all...] |
| /development/tools/findunused/ |
| findunusedstrings | 32 for i in $(grep -Rs "\(string\|plurals\) name=" res | sed 's/.*string name=\"//' | sed 's/.*plurals name=\"//'|sed 's/".*$//'|sort -u)
|
| /external/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 598 // BOVC if rs >= rt
599 // BEQZALC if rs == 0 && rt != 0
600 // BEQC if rs < rt && rs != 0
602 InsnType Rs = fieldFromInstruction(insn, 21, 5);
607 if (Rs >= Rt) {
610 } else if (Rs != 0 && Rs < Rt) {
618 Rs)));
632 InsnType Rs = fieldFromInstruction(insn, 16, 5)
[all...] |
| /frameworks/av/media/libstagefright/codecs/m4v_h263/enc/src/ |
| rate_control.h | 36 Int Rs; /*bit rate for the sequence (or segment) e.g., 24000 bits/sec */
|
| /external/swiftshader/third_party/subzero/src/ |
| IceAssemblerMIPS32.cpp | 209 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName);
212 Opcode |= Rs << 21;
222 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName);
224 Opcode |= Rs << 21;
237 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName);
248 Opcode |= Rs << 21;
259 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName)
[all...] |
| /system/core/libpixelflinger/tests/arch-arm64/assembler/ |
| arm64_assembler_test.cpp | 414 uint32_t Rn = 1, uint32_t Rm = 2, uint32_t Rs = 3)
429 regs[Rs] = test.RsValue;
455 case INSTR_MUL: a64asm->MUL(test.cond, test.setFlags, Rd,Rm,Rs); break;
456 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break;
460 case INSTR_SMULBB:a64asm->SMULBB(test.cond, Rd,Rm,Rs); break;
461 case INSTR_SMULBT:a64asm->SMULBT(test.cond, Rd,Rm,Rs); break;
462 case INSTR_SMULTB:a64asm->SMULTB(test.cond, Rd,Rm,Rs); break;
463 case INSTR_SMULTT:a64asm->SMULTT(test.cond, Rd,Rm,Rs); break;
464 case INSTR_SMULWB:a64asm->SMULWB(test.cond, Rd,Rm,Rs); break;
465 case INSTR_SMULWT:a64asm->SMULWT(test.cond, Rd,Rm,Rs); break
[all...] |
