| /external/llvm/lib/Target/XCore/Disassembler/ |
| XCoreDisassembler.cpp | 46 uint64_t &Size, uint16_t &Insn) {
53 Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
58 uint64_t &Size, uint32_t &Insn) {
65 Insn =
93 unsigned Insn,
98 unsigned Insn,
103 unsigned Insn,
108 unsigned Insn,
113 unsigned Insn,
118 unsigned Insn,
[all...] |
| /external/capstone/arch/XCore/ |
| XCoreDisassembler.c | 35 static bool readInstruction16(const uint8_t *code, size_t code_len, uint16_t *insn)
42 *insn = (code[0] << 0) | (code[1] << 8);
46 static bool readInstruction32(const uint8_t *code, size_t code_len, uint32_t *insn)
53 *insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | (code[3] << 24);
75 static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn,
78 static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn,
81 static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn,
84 static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn,
87 static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn,
90 static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn,
[all...] |
| /external/llvm/lib/Target/Lanai/Disassembler/ |
| LanaiDisassembler.cpp | 53 static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn,
56 static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn,
59 static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn,
62 static DecodeStatus decodeBranch(MCInst &Inst, unsigned Insn, uint64_t Address,
69 static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn,
75 uint64_t &Size, uint32_t &Insn) {
83 Insn =
89 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) {
100 AluOp = (Insn >> 8) & 0x7;
104 AluOp |= 0x20 | (((Insn >> 3) & 0xf) << 1)
[all...] |
| /dalvik/dexgen/src/com/android/dexgen/rop/code/ |
| InsnList.java | 22 * List of {@link Insn} instances.
43 public Insn get(int n) {
44 return (Insn) get0(n);
51 * @param insn {@code non-null;} the instruction to set at {@code n}
53 public void set(int n, Insn insn) {
54 set0(n, insn);
63 public Insn getLast() {
72 public void forEach(Insn.Visitor visitor) {
82 * The blocks must have the same number of insns, and each Insn mus
[all...] |
| SwitchInsn.java | 28 extends Insn {
76 public Insn withAddedCatch(Type type) {
82 public Insn withRegisterOffset(int delta) {
96 public boolean contentEquals(Insn b) {
102 public Insn withNewRegisters(RegisterSpec result,
|
| CstInsn.java | 25 extends Insn {
66 public boolean contentEquals(Insn b) {
69 * Insn.contentEquals compares classes of this and b.
|
| FillArrayDataInsn.java | 31 extends Insn {
96 public Insn withAddedCatch(Type type) {
102 public Insn withRegisterOffset(int delta) {
110 public Insn withNewRegisters(RegisterSpec result,
|
| ThrowingInsn.java | 29 extends Insn {
98 public Insn withAddedCatch(Type type) {
105 public Insn withRegisterOffset(int delta) {
113 public Insn withNewRegisters(RegisterSpec result,
|
| PlainInsn.java | 30 extends Insn {
84 public Insn withAddedCatch(Type type) {
90 public Insn withRegisterOffset(int delta) {
98 public Insn withLastSourceLiteral() {
132 public Insn withNewRegisters(RegisterSpec result,
|
| PlainCstInsn.java | 63 public Insn withAddedCatch(Type type) {
69 public Insn withRegisterOffset(int delta) {
78 public Insn withNewRegisters(RegisterSpec result,
|
| ThrowingCstInsn.java | 78 public Insn withAddedCatch(Type type) {
86 public Insn withRegisterOffset(int delta) {
95 public Insn withNewRegisters(RegisterSpec result,
|
| BasicBlock.java | 86 Insn lastInsn = insns.get(sz - 1);
200 public Insn getFirstInsn() {
210 public Insn getLastInsn() {
235 Insn lastInsn = insns.getLast();
250 Insn lastInsn = insns.getLast();
|
| /dalvik/dx/src/com/android/dx/rop/code/ |
| InsnList.java | 22 * List of {@link Insn} instances.
43 public Insn get(int n) {
44 return (Insn) get0(n);
51 * @param insn {@code non-null;} the instruction to set at {@code n}
53 public void set(int n, Insn insn) {
54 set0(n, insn);
63 public Insn getLast() {
72 public void forEach(Insn.Visitor visitor) {
82 * The blocks must have the same number of insns, and each Insn mus
[all...] |
| SwitchInsn.java | 28 extends Insn {
76 public Insn withAddedCatch(Type type) {
82 public Insn withRegisterOffset(int delta) {
96 public boolean contentEquals(Insn b) {
102 public Insn withNewRegisters(RegisterSpec result,
|
| CstInsn.java | 25 extends Insn {
66 public boolean contentEquals(Insn b) {
69 * Insn.contentEquals compares classes of this and b.
|
| FillArrayDataInsn.java | 30 extends Insn {
95 public Insn withAddedCatch(Type type) {
101 public Insn withRegisterOffset(int delta) {
109 public Insn withNewRegisters(RegisterSpec result,
|
| ThrowingInsn.java | 29 extends Insn {
98 public Insn withAddedCatch(Type type) {
105 public Insn withRegisterOffset(int delta) {
113 public Insn withNewRegisters(RegisterSpec result,
|
| PlainCstInsn.java | 63 public Insn withAddedCatch(Type type) {
69 public Insn withRegisterOffset(int delta) {
78 public Insn withNewRegisters(RegisterSpec result,
|
| /external/capstone/arch/ARM/ |
| ARMDisassembler.c | 172 static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Insn,
174 static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn,
177 unsigned Insn, uint64_t Address, const void *Decoder);
178 static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Insn,
180 static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst,unsigned Insn,
182 static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Insn,
184 static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Insn,
187 unsigned Insn, uint64_t Adddress, const void *Decoder);
188 static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn,
190 static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn,
449 uint32_t insn, i; local
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 143 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
145 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
148 unsigned Insn,
151 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
153 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
155 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
157 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
161 unsigned Insn,
164 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
166 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
357 uint32_t insn = (bytes[3] << 24) | local
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 186 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
188 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
191 unsigned Insn,
194 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
196 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
198 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
200 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
204 unsigned Insn,
207 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
209 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
[all...] |
| /external/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 102 unsigned Insn,
136 unsigned Insn,
206 unsigned Insn,
256 unsigned Insn,
261 unsigned Insn,
266 unsigned Insn,
271 unsigned Insn,
276 unsigned Insn,
281 unsigned Insn,
286 unsigned Insn,
[all...] |
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| PseudoLoweringEmitter.cpp | 27 addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn,
46 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec)
50 Insn.Operands[BaseIdx + i].Rec->getName() + "'");
54 for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
56 OpsAdded += Insn.Operands[i].MINumOperands;
65 addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i);
93 CodeGenInstruction Insn(Operator);
95 if (Insn.isCodeGenOnly || Insn.isPseudo)
99 if (Insn.Operands.size() != Dag->getNumArgs()
[all...] |
| /external/capstone/arch/Mips/ |
| MipsDisassembler.c | 77 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
113 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
129 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
132 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
135 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
138 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
141 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
144 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
146 static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn,
149 static DecodeStatus DecodeCOP2Mem(MCInst *Inst, unsigned Insn,
[all...] |
| /external/llvm/utils/TableGen/ |
| PseudoLoweringEmitter.cpp | 56 CodeGenInstruction &Insn,
74 addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn,
93 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec)
97 Insn.Operands[BaseIdx + i].Rec->getName() + "'");
101 for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
103 OpsAdded += Insn.Operands[i].MINumOperands;
112 addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i);
140 CodeGenInstruction Insn(Operator);
142 if (Insn.isCodeGenOnly || Insn.isPseudo
[all...] |
