1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 /* Capstone Disassembly Engine */ 11 /* By Nguyen Anh Quynh <aquynh (at) gmail.com>, 2013-2014 */ 12 13 #ifdef CAPSTONE_HAS_ARM 14 15 #include <stdio.h> 16 #include <string.h> 17 #include <stdlib.h> 18 #include <platform.h> 19 20 #include "ARMAddressingModes.h" 21 #include "ARMBaseInfo.h" 22 #include "../../MCFixedLenDisassembler.h" 23 #include "../../MCInst.h" 24 #include "../../MCInstrDesc.h" 25 #include "../../MCRegisterInfo.h" 26 #include "../../LEB128.h" 27 #include "../../MCDisassembler.h" 28 #include "../../cs_priv.h" 29 #include "../../utils.h" 30 31 #include "ARMDisassembler.h" 32 33 //#define GET_REGINFO_ENUM 34 //#include "X86GenRegisterInfo.inc" 35 36 #define GET_SUBTARGETINFO_ENUM 37 #include "ARMGenSubtargetInfo.inc" 38 39 #define GET_INSTRINFO_MC_DESC 40 #include "ARMGenInstrInfo.inc" 41 42 #define GET_INSTRINFO_ENUM 43 #include "ARMGenInstrInfo.inc" 44 45 static bool ITStatus_push_back(ARM_ITStatus *it, char v) 46 { 47 if (it->size >= sizeof(it->ITStates)) { 48 // TODO: consider warning user. 49 it->size = 0; 50 } 51 it->ITStates[it->size] = v; 52 it->size++; 53 54 return true; 55 } 56 57 // Returns true if the current instruction is in an IT block 58 static bool ITStatus_instrInITBlock(ARM_ITStatus *it) 59 { 60 //return !ITStates.empty(); 61 return (it->size > 0); 62 } 63 64 // Returns true if current instruction is the last instruction in an IT block 65 static bool ITStatus_instrLastInITBlock(ARM_ITStatus *it) 66 { 67 return (it->size == 1); 68 } 69 70 // Handles the condition code status of instructions in IT blocks 71 72 // Returns the condition code for instruction in IT block 73 static unsigned ITStatus_getITCC(ARM_ITStatus *it) 74 { 75 unsigned CC = ARMCC_AL; 76 if (ITStatus_instrInITBlock(it)) 77 //CC = ITStates.back(); 78 CC = it->ITStates[it->size-1]; 79 return CC; 80 } 81 82 // Advances the IT block state to the next T or E 83 static void ITStatus_advanceITState(ARM_ITStatus *it) 84 { 85 //ITStates.pop_back(); 86 it->size--; 87 } 88 89 // Called when decoding an IT instruction. Sets the IT state for the following 90 // instructions that for the IT block. Firstcond and Mask correspond to the 91 // fields in the IT instruction encoding. 92 static void ITStatus_setITState(ARM_ITStatus *it, char Firstcond, char Mask) 93 { 94 // (3 - the number of trailing zeros) is the number of then / else. 95 unsigned CondBit0 = Firstcond & 1; 96 unsigned NumTZ = CountTrailingZeros_32(Mask); 97 unsigned char CCBits = (unsigned char)Firstcond & 0xf; 98 unsigned Pos; 99 //assert(NumTZ <= 3 && "Invalid IT mask!"); 100 // push condition codes onto the stack the correct order for the pops 101 for (Pos = NumTZ+1; Pos <= 3; ++Pos) { 102 bool T = ((Mask >> Pos) & 1) == (int)CondBit0; 103 if (T) 104 ITStatus_push_back(it, CCBits); 105 else 106 ITStatus_push_back(it, CCBits ^ 1); 107 } 108 ITStatus_push_back(it, CCBits); 109 } 110 111 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 112 113 static bool Check(DecodeStatus *Out, DecodeStatus In) 114 { 115 switch (In) { 116 case MCDisassembler_Success: 117 // Out stays the same. 118 return true; 119 case MCDisassembler_SoftFail: 120 *Out = In; 121 return true; 122 case MCDisassembler_Fail: 123 *Out = In; 124 return false; 125 default: // never reached 126 return false; 127 } 128 } 129 130 // Forward declare these because the autogenerated code will reference them. 131 // Definitions are further down. 132 static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo, 133 uint64_t Address, const void *Decoder); 134 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, 135 unsigned RegNo, uint64_t Address, const void *Decoder); 136 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, 137 unsigned RegNo, uint64_t Address, const void *Decoder); 138 static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo, 139 uint64_t Address, const void *Decoder); 140 static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo, 141 uint64_t Address, const void *Decoder); 142 static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo, 143 uint64_t Address, const void *Decoder); 144 static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo, 145 uint64_t Address, const void *Decoder); 146 static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo, 147 uint64_t Address, const void *Decoder); 148 static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo, 149 uint64_t Address, const void *Decoder); 150 static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo, 151 uint64_t Address, const void *Decoder); 152 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst *Inst, 153 unsigned RegNo, uint64_t Address, const void *Decoder); 154 static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo, 157 uint64_t Address, const void *Decoder); 158 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst, 159 unsigned RegNo, uint64_t Address, const void *Decoder); 160 static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val, 161 uint64_t Address, const void *Decoder); 162 static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val, 163 uint64_t Address, const void *Decoder); 164 static DecodeStatus DecodeSOImmOperand(MCInst *Inst, unsigned Val, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Insn, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, 177 unsigned Insn, uint64_t Address, const void *Decoder); 178 static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Insn, 179 uint64_t Address, const void *Decoder); 180 static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst,unsigned Insn, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Insn, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Insn, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst * Inst, 187 unsigned Insn, uint64_t Adddress, const void *Decoder); 188 static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val, 201 uint64_t Address, const void *Decoder); 202 static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val, 203 uint64_t Address, const void *Decoder); 204 static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn, 205 uint64_t Address, const void *Decoder); 206 static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst,unsigned Insn, 207 uint64_t Address, const void *Decoder); 208 static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val, 209 uint64_t Address, const void *Decoder); 210 static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Val, 211 uint64_t Address, const void *Decoder); 212 static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Val, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Val, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Val, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Val, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Val, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Val, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Val, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Val, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Val, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeNEONModImmInstruction(MCInst *Inst,unsigned Val, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Val, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Insn, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Insn, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Insn, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Insn, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Val, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn, 313 uint64_t Address, const void* Decoder); 314 static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn, 315 uint64_t Address, const void* Decoder); 316 static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn, 317 uint64_t Address, const void* Decoder); 318 static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn, 319 uint64_t Address, const void* Decoder); 320 static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst,unsigned Val, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Val, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Insn, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Val, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Val, 345 uint64_t Address, const void *Decoder); 346 static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val, 347 uint64_t Address, const void *Decoder); 348 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst,unsigned Val, 349 uint64_t Address, const void *Decoder); 350 static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val, 351 uint64_t Address, const void *Decoder); 352 static DecodeStatus DecodeIT(MCInst *Inst, unsigned Val, 353 uint64_t Address, const void *Decoder); 354 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst,unsigned Insn, 355 uint64_t Address, const void *Decoder); 356 static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst,unsigned Insn, 357 uint64_t Address, const void *Decoder); 358 static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Val, 359 uint64_t Address, const void *Decoder); 360 static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Val, 361 uint64_t Address, const void *Decoder); 362 static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val, 363 uint64_t Address, const void *Decoder); 364 365 static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val, 366 uint64_t Address, const void *Decoder); 367 static DecodeStatus DecodeMRRC2(MCInst *Inst, unsigned Val, 368 uint64_t Address, const void *Decoder); 369 370 // Hacky: enable all features for disassembler 371 uint64_t ARM_getFeatureBits(unsigned int mode) 372 { 373 uint64_t Bits = (uint64_t)-1; // everything by default 374 375 // FIXME: ARM_FeatureVFPOnlySP is conflicting with everything else?? 376 Bits &= (~ARM_FeatureVFPOnlySP); 377 378 // FIXME: no Armv8 support? 379 //Bits -= ARM_HasV7Ops; 380 //Bits &= ~ARM_FeatureMP; 381 if ((mode & CS_MODE_V8) == 0) 382 Bits &= ~ARM_HasV8Ops; 383 //Bits &= ~ARM_HasV6Ops; 384 385 if ((mode & CS_MODE_MCLASS) == 0) 386 Bits &= (~ARM_FeatureMClass); 387 388 // some features are mutually exclusive 389 if (mode & CS_MODE_THUMB) { 390 //Bits &= ~ARM_HasV6Ops; 391 //Bits &= ~ARM_FeatureCRC; 392 //Bits &= ~ARM_HasV5TEOps; 393 //Bits &= ~ARM_HasV4TOps; 394 //Bits &= ~ARM_HasV6T2Ops; 395 //Bits &= ~ARM_FeatureDB; 396 //Bits &= ~ARM_FeatureHWDivARM; 397 //Bits &= ~ARM_FeatureNaClTrap; 398 //Bits &= ~ARM_FeatureMClass; 399 // ArmV8 400 } else { // ARM mode 401 Bits &= ~ARM_ModeThumb; 402 Bits &= ~ARM_FeatureThumb2; 403 } 404 405 return Bits; 406 } 407 408 #include "ARMGenDisassemblerTables.inc" 409 410 static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val, 411 uint64_t Address, const void *Decoder) 412 { 413 if (Val == 0xF) return MCDisassembler_Fail; 414 // AL predicate is not allowed on Thumb1 branches. 415 if (MCInst_getOpcode(Inst) == ARM_tBcc && Val == 0xE) 416 return MCDisassembler_Fail; 417 MCOperand_CreateImm0(Inst, Val); 418 if (Val == ARMCC_AL) { 419 MCOperand_CreateReg0(Inst, 0); 420 } else 421 MCOperand_CreateReg0(Inst, ARM_CPSR); 422 return MCDisassembler_Success; 423 } 424 425 #define GET_REGINFO_MC_DESC 426 #include "ARMGenRegisterInfo.inc" 427 void ARM_init(MCRegisterInfo *MRI) 428 { 429 /* 430 InitMCRegisterInfo(ARMRegDesc, 289, 431 RA, PC, 432 ARMMCRegisterClasses, 100, 433 ARMRegUnitRoots, 77, ARMRegDiffLists, ARMRegStrings, 434 ARMSubRegIdxLists, 57, 435 ARMSubRegIdxRanges, ARMRegEncodingTable); 436 */ 437 438 MCRegisterInfo_InitMCRegisterInfo(MRI, ARMRegDesc, 289, 439 0, 0, 440 ARMMCRegisterClasses, 100, 441 0, 0, ARMRegDiffLists, 0, 442 ARMSubRegIdxLists, 57, 443 0); 444 } 445 446 static DecodeStatus _ARM_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len, 447 uint16_t *Size, uint64_t Address) 448 { 449 uint32_t insn, i; 450 uint8_t bytes[4]; 451 DecodeStatus result; 452 453 if (code_len < 4) 454 // not enough data 455 return MCDisassembler_Fail; 456 457 if (MI->flat_insn->detail) { 458 memset(&MI->flat_insn->detail->arm, 0, sizeof(cs_arm)); 459 for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) 460 MI->flat_insn->detail->arm.operands[i].vector_index = -1; 461 } 462 463 memcpy(bytes, code, 4); 464 465 if (ud->big_endian) 466 insn = (bytes[3] << 0) | 467 (bytes[2] << 8) | 468 (bytes[1] << 16) | 469 (bytes[0] << 24); 470 else 471 insn = (bytes[3] << 24) | 472 (bytes[2] << 16) | 473 (bytes[1] << 8) | 474 (bytes[0] << 0); 475 476 // Calling the auto-generated decoder function. 477 result = decodeInstruction_4(DecoderTableARM32, MI, insn, Address, NULL, ud->mode); 478 if (result != MCDisassembler_Fail) { 479 *Size = 4; 480 return result; 481 } 482 483 // VFP and NEON instructions, similarly, are shared between ARM 484 // and Thumb modes. 485 MCInst_clear(MI); 486 result = decodeInstruction_4(DecoderTableVFP32, MI, insn, Address, NULL, ud->mode); 487 if (result != MCDisassembler_Fail) { 488 *Size = 4; 489 return result; 490 } 491 492 MCInst_clear(MI); 493 result = decodeInstruction_4(DecoderTableVFPV832, MI, insn, Address, NULL, ud->mode); 494 if (result != MCDisassembler_Fail) { 495 *Size = 4; 496 return result; 497 } 498 499 MCInst_clear(MI); 500 result = decodeInstruction_4(DecoderTableNEONData32, MI, insn, Address, NULL, ud->mode); 501 if (result != MCDisassembler_Fail) { 502 *Size = 4; 503 // Add a fake predicate operand, because we share these instruction 504 // definitions with Thumb2 where these instructions are predicable. 505 if (!DecodePredicateOperand(MI, 0xE, Address, NULL)) 506 return MCDisassembler_Fail; 507 return result; 508 } 509 510 MCInst_clear(MI); 511 result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, insn, Address, NULL, ud->mode); 512 if (result != MCDisassembler_Fail) { 513 *Size = 4; 514 // Add a fake predicate operand, because we share these instruction 515 // definitions with Thumb2 where these instructions are predicable. 516 if (!DecodePredicateOperand(MI, 0xE, Address, NULL)) 517 return MCDisassembler_Fail; 518 return result; 519 } 520 521 MCInst_clear(MI); 522 result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn, Address, NULL, ud->mode); 523 if (result != MCDisassembler_Fail) { 524 *Size = 4; 525 // Add a fake predicate operand, because we share these instruction 526 // definitions with Thumb2 where these instructions are predicable. 527 if (!DecodePredicateOperand(MI, 0xE, Address, NULL)) 528 return MCDisassembler_Fail; 529 return result; 530 } 531 532 MCInst_clear(MI); 533 result = decodeInstruction_4(DecoderTablev8NEON32, MI, insn, Address, NULL, ud->mode); 534 if (result != MCDisassembler_Fail) { 535 *Size = 4; 536 return result; 537 } 538 539 MCInst_clear(MI); 540 result = decodeInstruction_4(DecoderTablev8Crypto32, MI, insn, Address, NULL, ud->mode); 541 if (result != MCDisassembler_Fail) { 542 *Size = 4; 543 return result; 544 } 545 546 MCInst_clear(MI); 547 *Size = 0; 548 return MCDisassembler_Fail; 549 } 550 551 // Thumb1 instructions don't have explicit S bits. Rather, they 552 // implicitly set CPSR. Since it's not represented in the encoding, the 553 // auto-generated decoder won't inject the CPSR operand. We need to fix 554 // that as a post-pass. 555 static void AddThumb1SBit(MCInst *MI, bool InITBlock) 556 { 557 MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; 558 unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; 559 unsigned i; 560 561 for (i = 0; i < NumOps; ++i) { 562 if (i == MCInst_getNumOperands(MI)) break; 563 if (MCOperandInfo_isOptionalDef(&OpInfo[i]) && OpInfo[i].RegClass == ARM_CCRRegClassID) { 564 if (i > 0 && MCOperandInfo_isPredicate(&OpInfo[i-1])) continue; 565 MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR)); 566 return; 567 } 568 } 569 570 //MI.insert(I, MCOperand_CreateReg0(Inst, InITBlock ? 0 : ARM_CPSR)); 571 MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR)); 572 } 573 574 // Most Thumb instructions don't have explicit predicates in the 575 // encoding, but rather get their predicates from IT context. We need 576 // to fix up the predicate operands using this context information as a 577 // post-pass. 578 static DecodeStatus AddThumbPredicate(cs_struct *ud, MCInst *MI) 579 { 580 DecodeStatus S = MCDisassembler_Success; 581 MCOperandInfo *OpInfo; 582 unsigned short NumOps; 583 unsigned int i; 584 unsigned CC; 585 586 // A few instructions actually have predicates encoded in them. Don't 587 // try to overwrite it if we're seeing one of those. 588 switch (MCInst_getOpcode(MI)) { 589 case ARM_tBcc: 590 case ARM_t2Bcc: 591 case ARM_tCBZ: 592 case ARM_tCBNZ: 593 case ARM_tCPS: 594 case ARM_t2CPS3p: 595 case ARM_t2CPS2p: 596 case ARM_t2CPS1p: 597 case ARM_tMOVSr: 598 case ARM_tSETEND: 599 // Some instructions (mostly conditional branches) are not 600 // allowed in IT blocks. 601 if (ITStatus_instrInITBlock(&(ud->ITBlock))) 602 S = MCDisassembler_SoftFail; 603 else 604 return MCDisassembler_Success; 605 break; 606 case ARM_tB: 607 case ARM_t2B: 608 case ARM_t2TBB: 609 case ARM_t2TBH: 610 // Some instructions (mostly unconditional branches) can 611 // only appears at the end of, or outside of, an IT. 612 //if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 613 if (ITStatus_instrInITBlock(&(ud->ITBlock)) && !ITStatus_instrLastInITBlock(&(ud->ITBlock))) 614 S = MCDisassembler_SoftFail; 615 break; 616 default: 617 break; 618 } 619 620 // If we're in an IT block, base the predicate on that. Otherwise, 621 // assume a predicate of AL. 622 CC = ITStatus_getITCC(&(ud->ITBlock)); 623 if (CC == 0xF) 624 CC = ARMCC_AL; 625 if (ITStatus_instrInITBlock(&(ud->ITBlock))) 626 ITStatus_advanceITState(&(ud->ITBlock)); 627 628 OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; 629 NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; 630 631 for (i = 0; i < NumOps; ++i) { 632 if (i == MCInst_getNumOperands(MI)) break; 633 if (MCOperandInfo_isPredicate(&OpInfo[i])) { 634 MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC)); 635 if (CC == ARMCC_AL) 636 MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, 0)); 637 else 638 MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, ARM_CPSR)); 639 return S; 640 } 641 } 642 643 MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC)); 644 if (CC == ARMCC_AL) 645 MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, 0)); 646 else 647 MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, ARM_CPSR)); 648 649 return S; 650 } 651 652 // Thumb VFP instructions are a special case. Because we share their 653 // encodings between ARM and Thumb modes, and they are predicable in ARM 654 // mode, the auto-generated decoder will give them an (incorrect) 655 // predicate operand. We need to rewrite these operands based on the IT 656 // context as a post-pass. 657 static void UpdateThumbVFPPredicate(cs_struct *ud, MCInst *MI) 658 { 659 unsigned CC; 660 unsigned short NumOps; 661 MCOperandInfo *OpInfo; 662 unsigned i; 663 664 CC = ITStatus_getITCC(&(ud->ITBlock)); 665 if (ITStatus_instrInITBlock(&(ud->ITBlock))) 666 ITStatus_advanceITState(&(ud->ITBlock)); 667 668 OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; 669 NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; 670 671 for (i = 0; i < NumOps; ++i) { 672 if (MCOperandInfo_isPredicate(&OpInfo[i])) { 673 MCOperand_setImm(MCInst_getOperand(MI, i), CC); 674 if (CC == ARMCC_AL) 675 MCOperand_setReg(MCInst_getOperand(MI, i+1), 0); 676 else 677 MCOperand_setReg(MCInst_getOperand(MI, i+1), ARM_CPSR); 678 return; 679 } 680 } 681 } 682 683 static DecodeStatus _Thumb_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len, 684 uint16_t *Size, uint64_t Address) 685 { 686 uint8_t bytes[4]; 687 uint16_t insn16; 688 DecodeStatus result; 689 bool InITBlock; 690 unsigned Firstcond, Mask; 691 uint32_t NEONLdStInsn, insn32, NEONDataInsn, NEONCryptoInsn, NEONv8Insn; 692 size_t i; 693 694 // We want to read exactly 2 bytes of data. 695 if (code_len < 2) 696 // not enough data 697 return MCDisassembler_Fail; 698 699 if (MI->flat_insn->detail) { 700 memset(&MI->flat_insn->detail->arm, 0, sizeof(cs_arm)); 701 for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) 702 MI->flat_insn->detail->arm.operands[i].vector_index = -1; 703 } 704 705 memcpy(bytes, code, 2); 706 707 if (ud->big_endian) 708 insn16 = (bytes[0] << 8) | bytes[1]; 709 else 710 insn16 = (bytes[1] << 8) | bytes[0]; 711 712 result = decodeInstruction_2(DecoderTableThumb16, MI, insn16, Address, NULL, ud->mode); 713 if (result != MCDisassembler_Fail) { 714 *Size = 2; 715 Check(&result, AddThumbPredicate(ud, MI)); 716 return result; 717 } 718 719 MCInst_clear(MI); 720 result = decodeInstruction_2(DecoderTableThumbSBit16, MI, insn16, Address, NULL, ud->mode); 721 if (result) { 722 *Size = 2; 723 InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock)); 724 Check(&result, AddThumbPredicate(ud, MI)); 725 AddThumb1SBit(MI, InITBlock); 726 return result; 727 } 728 729 MCInst_clear(MI); 730 result = decodeInstruction_2(DecoderTableThumb216, MI, insn16, Address, NULL, ud->mode); 731 if (result != MCDisassembler_Fail) { 732 *Size = 2; 733 734 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 735 // the Thumb predicate. 736 if (MCInst_getOpcode(MI) == ARM_t2IT && ITStatus_instrInITBlock(&(ud->ITBlock))) 737 return MCDisassembler_SoftFail; 738 Check(&result, AddThumbPredicate(ud, MI)); 739 740 // If we find an IT instruction, we need to parse its condition 741 // code and mask operands so that we can apply them correctly 742 // to the subsequent instructions. 743 if (MCInst_getOpcode(MI) == ARM_t2IT) { 744 745 Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 0)); 746 Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 1)); 747 ITStatus_setITState(&(ud->ITBlock), (char)Firstcond, (char)Mask); 748 } 749 750 return result; 751 } 752 753 // We want to read exactly 4 bytes of data. 754 if (code_len < 4) 755 // not enough data 756 return MCDisassembler_Fail; 757 758 memcpy(bytes, code, 4); 759 760 if (ud->big_endian) 761 insn32 = (bytes[3] << 0) | 762 (bytes[2] << 8) | 763 (bytes[1] << 16) | 764 (bytes[0] << 24); 765 else 766 insn32 = (bytes[3] << 8) | 767 (bytes[2] << 0) | 768 (bytes[1] << 24) | 769 (bytes[0] << 16); 770 771 MCInst_clear(MI); 772 result = decodeInstruction_4(DecoderTableThumb32, MI, insn32, Address, NULL, ud->mode); 773 if (result != MCDisassembler_Fail) { 774 *Size = 4; 775 InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock)); 776 Check(&result, AddThumbPredicate(ud, MI)); 777 AddThumb1SBit(MI, InITBlock); 778 return result; 779 } 780 781 MCInst_clear(MI); 782 result = decodeInstruction_4(DecoderTableThumb232, MI, insn32, Address, NULL, ud->mode); 783 if (result != MCDisassembler_Fail) { 784 *Size = 4; 785 Check(&result, AddThumbPredicate(ud, MI)); 786 return result; 787 } 788 789 MCInst_clear(MI); 790 result = decodeInstruction_4(DecoderTableVFP32, MI, insn32, Address, NULL, ud->mode); 791 if (result != MCDisassembler_Fail) { 792 *Size = 4; 793 UpdateThumbVFPPredicate(ud, MI); 794 return result; 795 } 796 797 if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) { 798 MCInst_clear(MI); 799 result = decodeInstruction_4(DecoderTableVFP32, MI, insn32, Address, NULL, ud->mode); 800 if (result != MCDisassembler_Fail) { 801 *Size = 4; 802 UpdateThumbVFPPredicate(ud, MI); 803 return result; 804 } 805 } 806 807 MCInst_clear(MI); 808 result = decodeInstruction_4(DecoderTableVFPV832, MI, insn32, Address, NULL, ud->mode); 809 if (result != MCDisassembler_Fail) { 810 *Size = 4; 811 return result; 812 } 813 814 if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) { 815 MCInst_clear(MI); 816 result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn32, Address, NULL, ud->mode); 817 if (result != MCDisassembler_Fail) { 818 *Size = 4; 819 Check(&result, AddThumbPredicate(ud, MI)); 820 return result; 821 } 822 } 823 824 if (fieldFromInstruction_4(insn32, 24, 8) == 0xF9) { 825 MCInst_clear(MI); 826 NEONLdStInsn = insn32; 827 NEONLdStInsn &= 0xF0FFFFFF; 828 NEONLdStInsn |= 0x04000000; 829 result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, Address, NULL, ud->mode); 830 if (result != MCDisassembler_Fail) { 831 *Size = 4; 832 Check(&result, AddThumbPredicate(ud, MI)); 833 return result; 834 } 835 } 836 837 if (fieldFromInstruction_4(insn32, 24, 4) == 0xF) { 838 MCInst_clear(MI); 839 NEONDataInsn = insn32; 840 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 841 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 842 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 843 result = decodeInstruction_4(DecoderTableNEONData32, MI, NEONDataInsn, Address, NULL, ud->mode); 844 if (result != MCDisassembler_Fail) { 845 *Size = 4; 846 Check(&result, AddThumbPredicate(ud, MI)); 847 return result; 848 } 849 } 850 851 MCInst_clear(MI); 852 NEONCryptoInsn = insn32; 853 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 854 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 855 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 856 result = decodeInstruction_4(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 857 Address, NULL, ud->mode); 858 if (result != MCDisassembler_Fail) { 859 *Size = 4; 860 return result; 861 } 862 863 MCInst_clear(MI); 864 NEONv8Insn = insn32; 865 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 866 result = decodeInstruction_4(DecoderTablev8NEON32, MI, NEONv8Insn, Address, NULL, ud->mode); 867 if (result != MCDisassembler_Fail) { 868 *Size = 4; 869 return result; 870 } 871 872 MCInst_clear(MI); 873 *Size = 0; 874 return MCDisassembler_Fail; 875 } 876 877 bool Thumb_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, 878 uint16_t *size, uint64_t address, void *info) 879 { 880 DecodeStatus status = _Thumb_getInstruction((cs_struct *)ud, instr, code, code_len, size, address); 881 882 //return status == MCDisassembler_Success; 883 return status != MCDisassembler_Fail; 884 } 885 886 bool ARM_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, 887 uint16_t *size, uint64_t address, void *info) 888 { 889 DecodeStatus status = _ARM_getInstruction((cs_struct *)ud, instr, code, code_len, size, address); 890 891 //return status == MCDisassembler_Success; 892 return status != MCDisassembler_Fail; 893 } 894 895 static const uint16_t GPRDecoderTable[] = { 896 ARM_R0, ARM_R1, ARM_R2, ARM_R3, 897 ARM_R4, ARM_R5, ARM_R6, ARM_R7, 898 ARM_R8, ARM_R9, ARM_R10, ARM_R11, 899 ARM_R12, ARM_SP, ARM_LR, ARM_PC 900 }; 901 902 static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo, 903 uint64_t Address, const void *Decoder) 904 { 905 unsigned Register; 906 if (RegNo > 15) 907 return MCDisassembler_Fail; 908 909 Register = GPRDecoderTable[RegNo]; 910 MCOperand_CreateReg0(Inst, Register); 911 return MCDisassembler_Success; 912 } 913 914 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, unsigned RegNo, 915 uint64_t Address, const void *Decoder) 916 { 917 DecodeStatus S = MCDisassembler_Success; 918 919 if (RegNo == 15) 920 S = MCDisassembler_SoftFail; 921 922 Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 923 924 return S; 925 } 926 927 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, unsigned RegNo, 928 uint64_t Address, const void *Decoder) 929 { 930 DecodeStatus S = MCDisassembler_Success; 931 932 if (RegNo == 15) { 933 MCOperand_CreateReg0(Inst, ARM_APSR_NZCV); 934 return MCDisassembler_Success; 935 } 936 937 Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 938 return S; 939 } 940 941 static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo, 942 uint64_t Address, const void *Decoder) 943 { 944 if (RegNo > 7) 945 return MCDisassembler_Fail; 946 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 947 } 948 949 static const uint16_t GPRPairDecoderTable[] = { 950 ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, 951 ARM_R8_R9, ARM_R10_R11, ARM_R12_SP 952 }; 953 954 static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo, 955 uint64_t Address, const void *Decoder) 956 { 957 unsigned RegisterPair; 958 DecodeStatus S = MCDisassembler_Success; 959 960 if (RegNo > 13) 961 return MCDisassembler_Fail; 962 963 if ((RegNo & 1) || RegNo == 0xe) 964 S = MCDisassembler_SoftFail; 965 966 RegisterPair = GPRPairDecoderTable[RegNo/2]; 967 MCOperand_CreateReg0(Inst, RegisterPair); 968 return S; 969 } 970 971 static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo, 972 uint64_t Address, const void *Decoder) 973 { 974 unsigned Register = 0; 975 switch (RegNo) { 976 case 0: 977 Register = ARM_R0; 978 break; 979 case 1: 980 Register = ARM_R1; 981 break; 982 case 2: 983 Register = ARM_R2; 984 break; 985 case 3: 986 Register = ARM_R3; 987 break; 988 case 9: 989 Register = ARM_R9; 990 break; 991 case 12: 992 Register = ARM_R12; 993 break; 994 default: 995 return MCDisassembler_Fail; 996 } 997 998 MCOperand_CreateReg0(Inst, Register); 999 return MCDisassembler_Success; 1000 } 1001 1002 static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo, 1003 uint64_t Address, const void *Decoder) 1004 { 1005 DecodeStatus S = MCDisassembler_Success; 1006 if (RegNo == 13 || RegNo == 15) 1007 S = MCDisassembler_SoftFail; 1008 Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1009 return S; 1010 } 1011 1012 static const uint16_t SPRDecoderTable[] = { 1013 ARM_S0, ARM_S1, ARM_S2, ARM_S3, 1014 ARM_S4, ARM_S5, ARM_S6, ARM_S7, 1015 ARM_S8, ARM_S9, ARM_S10, ARM_S11, 1016 ARM_S12, ARM_S13, ARM_S14, ARM_S15, 1017 ARM_S16, ARM_S17, ARM_S18, ARM_S19, 1018 ARM_S20, ARM_S21, ARM_S22, ARM_S23, 1019 ARM_S24, ARM_S25, ARM_S26, ARM_S27, 1020 ARM_S28, ARM_S29, ARM_S30, ARM_S31 1021 }; 1022 1023 static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo, 1024 uint64_t Address, const void *Decoder) 1025 { 1026 unsigned Register; 1027 if (RegNo > 31) 1028 return MCDisassembler_Fail; 1029 1030 Register = SPRDecoderTable[RegNo]; 1031 MCOperand_CreateReg0(Inst, Register); 1032 return MCDisassembler_Success; 1033 } 1034 1035 static const uint16_t DPRDecoderTable[] = { 1036 ARM_D0, ARM_D1, ARM_D2, ARM_D3, 1037 ARM_D4, ARM_D5, ARM_D6, ARM_D7, 1038 ARM_D8, ARM_D9, ARM_D10, ARM_D11, 1039 ARM_D12, ARM_D13, ARM_D14, ARM_D15, 1040 ARM_D16, ARM_D17, ARM_D18, ARM_D19, 1041 ARM_D20, ARM_D21, ARM_D22, ARM_D23, 1042 ARM_D24, ARM_D25, ARM_D26, ARM_D27, 1043 ARM_D28, ARM_D29, ARM_D30, ARM_D31 1044 }; 1045 1046 static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo, 1047 uint64_t Address, const void *Decoder) 1048 { 1049 unsigned Register = 0; 1050 if (RegNo > 31) 1051 return MCDisassembler_Fail; 1052 1053 Register = DPRDecoderTable[RegNo]; 1054 MCOperand_CreateReg0(Inst, Register); 1055 return MCDisassembler_Success; 1056 } 1057 1058 static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo, 1059 uint64_t Address, const void *Decoder) 1060 { 1061 if (RegNo > 7) 1062 return MCDisassembler_Fail; 1063 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1064 } 1065 1066 static DecodeStatus 1067 DecodeDPR_VFP2RegisterClass(MCInst *Inst, unsigned RegNo, 1068 uint64_t Address, const void *Decoder) 1069 { 1070 if (RegNo > 15) 1071 return MCDisassembler_Fail; 1072 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1073 } 1074 1075 static const uint16_t QPRDecoderTable[] = { 1076 ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, 1077 ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, 1078 ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, 1079 ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15 1080 }; 1081 1082 static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo, 1083 uint64_t Address, const void *Decoder) 1084 { 1085 unsigned Register; 1086 if (RegNo > 31 || (RegNo & 1) != 0) 1087 return MCDisassembler_Fail; 1088 RegNo >>= 1; 1089 1090 Register = QPRDecoderTable[RegNo]; 1091 MCOperand_CreateReg0(Inst, Register); 1092 return MCDisassembler_Success; 1093 } 1094 1095 static const uint16_t DPairDecoderTable[] = { 1096 ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, 1097 ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, 1098 ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, ARM_Q8, ARM_D17_D18, 1099 ARM_Q9, ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24, 1100 ARM_Q12, ARM_D25_D26, ARM_Q13, ARM_D27_D28, ARM_Q14, ARM_D29_D30, 1101 ARM_Q15 1102 }; 1103 1104 static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo, 1105 uint64_t Address, const void *Decoder) 1106 { 1107 unsigned Register; 1108 if (RegNo > 30) 1109 return MCDisassembler_Fail; 1110 1111 Register = DPairDecoderTable[RegNo]; 1112 MCOperand_CreateReg0(Inst, Register); 1113 return MCDisassembler_Success; 1114 } 1115 1116 static const uint16_t DPairSpacedDecoderTable[] = { 1117 ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, 1118 ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, 1119 ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, 1120 ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17, 1121 ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21, 1122 ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25, 1123 ARM_D24_D26, ARM_D25_D27, ARM_D26_D28, ARM_D27_D29, 1124 ARM_D28_D30, ARM_D29_D31 1125 }; 1126 1127 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst, 1128 unsigned RegNo, uint64_t Address, const void *Decoder) 1129 { 1130 unsigned Register; 1131 if (RegNo > 29) 1132 return MCDisassembler_Fail; 1133 1134 Register = DPairSpacedDecoderTable[RegNo]; 1135 MCOperand_CreateReg0(Inst, Register); 1136 return MCDisassembler_Success; 1137 } 1138 1139 static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val, 1140 uint64_t Address, const void *Decoder) 1141 { 1142 if (Val) 1143 MCOperand_CreateReg0(Inst, ARM_CPSR); 1144 else 1145 MCOperand_CreateReg0(Inst, 0); 1146 return MCDisassembler_Success; 1147 } 1148 1149 static DecodeStatus DecodeSOImmOperand(MCInst *Inst, unsigned Val, 1150 uint64_t Address, const void *Decoder) 1151 { 1152 uint32_t imm = Val & 0xFF; 1153 uint32_t rot = (Val & 0xF00) >> 7; 1154 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1155 MCOperand_CreateImm0(Inst, rot_imm); 1156 return MCDisassembler_Success; 1157 } 1158 1159 static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Val, 1160 uint64_t Address, const void *Decoder) 1161 { 1162 DecodeStatus S = MCDisassembler_Success; 1163 ARM_AM_ShiftOpc Shift; 1164 unsigned Op; 1165 unsigned Rm = fieldFromInstruction_4(Val, 0, 4); 1166 unsigned type = fieldFromInstruction_4(Val, 5, 2); 1167 unsigned imm = fieldFromInstruction_4(Val, 7, 5); 1168 1169 // Register-immediate 1170 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1171 return MCDisassembler_Fail; 1172 1173 Shift = ARM_AM_lsl; 1174 switch (type) { 1175 case 0: 1176 Shift = ARM_AM_lsl; 1177 break; 1178 case 1: 1179 Shift = ARM_AM_lsr; 1180 break; 1181 case 2: 1182 Shift = ARM_AM_asr; 1183 break; 1184 case 3: 1185 Shift = ARM_AM_ror; 1186 break; 1187 } 1188 1189 if (Shift == ARM_AM_ror && imm == 0) 1190 Shift = ARM_AM_rrx; 1191 1192 Op = Shift | (imm << 3); 1193 MCOperand_CreateImm0(Inst, Op); 1194 1195 return S; 1196 } 1197 1198 static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Val, 1199 uint64_t Address, const void *Decoder) 1200 { 1201 DecodeStatus S = MCDisassembler_Success; 1202 ARM_AM_ShiftOpc Shift; 1203 1204 unsigned Rm = fieldFromInstruction_4(Val, 0, 4); 1205 unsigned type = fieldFromInstruction_4(Val, 5, 2); 1206 unsigned Rs = fieldFromInstruction_4(Val, 8, 4); 1207 1208 // Register-register 1209 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1210 return MCDisassembler_Fail; 1211 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1212 return MCDisassembler_Fail; 1213 1214 Shift = ARM_AM_lsl; 1215 switch (type) { 1216 case 0: 1217 Shift = ARM_AM_lsl; 1218 break; 1219 case 1: 1220 Shift = ARM_AM_lsr; 1221 break; 1222 case 2: 1223 Shift = ARM_AM_asr; 1224 break; 1225 case 3: 1226 Shift = ARM_AM_ror; 1227 break; 1228 } 1229 1230 MCOperand_CreateImm0(Inst, Shift); 1231 1232 return S; 1233 } 1234 1235 static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val, 1236 uint64_t Address, const void *Decoder) 1237 { 1238 unsigned i; 1239 DecodeStatus S = MCDisassembler_Success; 1240 unsigned opcode; 1241 1242 bool NeedDisjointWriteback = false; 1243 unsigned WritebackReg = 0; 1244 1245 opcode = MCInst_getOpcode(Inst); 1246 switch (opcode) { 1247 default: 1248 break; 1249 case ARM_LDMIA_UPD: 1250 case ARM_LDMDB_UPD: 1251 case ARM_LDMIB_UPD: 1252 case ARM_LDMDA_UPD: 1253 case ARM_t2LDMIA_UPD: 1254 case ARM_t2LDMDB_UPD: 1255 case ARM_t2STMIA_UPD: 1256 case ARM_t2STMDB_UPD: 1257 NeedDisjointWriteback = true; 1258 WritebackReg = MCOperand_getReg(MCInst_getOperand(Inst, 0)); 1259 break; 1260 } 1261 1262 // Empty register lists are not allowed. 1263 if (Val == 0) return MCDisassembler_Fail; 1264 for (i = 0; i < 16; ++i) { 1265 if (Val & (1 << i)) { 1266 if (!Check(&S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1267 return MCDisassembler_Fail; 1268 // Writeback not allowed if Rn is in the target list. 1269 if (NeedDisjointWriteback && WritebackReg == MCOperand_getReg(&(Inst->Operands[Inst->size-1]))) 1270 Check(&S, MCDisassembler_SoftFail); 1271 } 1272 } 1273 1274 if (opcode == ARM_t2LDMIA_UPD && WritebackReg == ARM_SP) { 1275 if (Val & (1 << 13) || ((Val & (1 << 15)) && (Val & (1 << 14)))) { 1276 // invalid thumb2 pop 1277 // needs no sp in reglist and not both pc and lr set at the same time 1278 return MCDisassembler_Fail; 1279 } 1280 } 1281 1282 return S; 1283 } 1284 1285 static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val, 1286 uint64_t Address, const void *Decoder) 1287 { 1288 DecodeStatus S = MCDisassembler_Success; 1289 unsigned i; 1290 unsigned Vd = fieldFromInstruction_4(Val, 8, 5); 1291 unsigned regs = fieldFromInstruction_4(Val, 0, 8); 1292 1293 // In case of unpredictable encoding, tweak the operands. 1294 if (regs == 0 || (Vd + regs) > 32) { 1295 regs = Vd + regs > 32 ? 32 - Vd : regs; 1296 regs = (1u > regs? 1u : regs); 1297 S = MCDisassembler_SoftFail; 1298 } 1299 1300 if (!Check(&S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1301 return MCDisassembler_Fail; 1302 for (i = 0; i < (regs - 1); ++i) { 1303 if (!Check(&S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1304 return MCDisassembler_Fail; 1305 } 1306 1307 return S; 1308 } 1309 1310 static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val, 1311 uint64_t Address, const void *Decoder) 1312 { 1313 DecodeStatus S = MCDisassembler_Success; 1314 unsigned i; 1315 unsigned Vd = fieldFromInstruction_4(Val, 8, 5); 1316 unsigned regs = fieldFromInstruction_4(Val, 1, 7); 1317 1318 // In case of unpredictable encoding, tweak the operands. 1319 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1320 regs = Vd + regs > 32 ? 32 - Vd : regs; 1321 regs = (1u > regs? 1u : regs); 1322 regs = (16u > regs? regs : 16u); 1323 S = MCDisassembler_SoftFail; 1324 } 1325 1326 if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1327 return MCDisassembler_Fail; 1328 1329 for (i = 0; i < (regs - 1); ++i) { 1330 if (!Check(&S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1331 return MCDisassembler_Fail; 1332 } 1333 1334 return S; 1335 } 1336 1337 static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Val, 1338 uint64_t Address, const void *Decoder) 1339 { 1340 // This operand encodes a mask of contiguous zeros between a specified MSB 1341 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1342 // the mask of all bits LSB-and-lower, and then xor them to create 1343 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1344 // create the final mask. 1345 unsigned msb = fieldFromInstruction_4(Val, 5, 5); 1346 unsigned lsb = fieldFromInstruction_4(Val, 0, 5); 1347 uint32_t lsb_mask, msb_mask; 1348 1349 DecodeStatus S = MCDisassembler_Success; 1350 if (lsb > msb) { 1351 Check(&S, MCDisassembler_SoftFail); 1352 // The check above will cause the warning for the "potentially undefined 1353 // instruction encoding" but we can't build a bad MCOperand value here 1354 // with a lsb > msb or else printing the MCInst will cause a crash. 1355 lsb = msb; 1356 } 1357 1358 msb_mask = 0xFFFFFFFF; 1359 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1360 lsb_mask = (1U << lsb) - 1; 1361 1362 MCOperand_CreateImm0(Inst, ~(msb_mask ^ lsb_mask)); 1363 return S; 1364 } 1365 1366 static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn, 1367 uint64_t Address, const void *Decoder) 1368 { 1369 DecodeStatus S = MCDisassembler_Success; 1370 1371 unsigned pred = fieldFromInstruction_4(Insn, 28, 4); 1372 unsigned CRd = fieldFromInstruction_4(Insn, 12, 4); 1373 unsigned coproc = fieldFromInstruction_4(Insn, 8, 4); 1374 unsigned imm = fieldFromInstruction_4(Insn, 0, 8); 1375 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 1376 unsigned U = fieldFromInstruction_4(Insn, 23, 1); 1377 1378 switch (MCInst_getOpcode(Inst)) { 1379 case ARM_LDC_OFFSET: 1380 case ARM_LDC_PRE: 1381 case ARM_LDC_POST: 1382 case ARM_LDC_OPTION: 1383 case ARM_LDCL_OFFSET: 1384 case ARM_LDCL_PRE: 1385 case ARM_LDCL_POST: 1386 case ARM_LDCL_OPTION: 1387 case ARM_STC_OFFSET: 1388 case ARM_STC_PRE: 1389 case ARM_STC_POST: 1390 case ARM_STC_OPTION: 1391 case ARM_STCL_OFFSET: 1392 case ARM_STCL_PRE: 1393 case ARM_STCL_POST: 1394 case ARM_STCL_OPTION: 1395 case ARM_t2LDC_OFFSET: 1396 case ARM_t2LDC_PRE: 1397 case ARM_t2LDC_POST: 1398 case ARM_t2LDC_OPTION: 1399 case ARM_t2LDCL_OFFSET: 1400 case ARM_t2LDCL_PRE: 1401 case ARM_t2LDCL_POST: 1402 case ARM_t2LDCL_OPTION: 1403 case ARM_t2STC_OFFSET: 1404 case ARM_t2STC_PRE: 1405 case ARM_t2STC_POST: 1406 case ARM_t2STC_OPTION: 1407 case ARM_t2STCL_OFFSET: 1408 case ARM_t2STCL_PRE: 1409 case ARM_t2STCL_POST: 1410 case ARM_t2STCL_OPTION: 1411 if (coproc == 0xA || coproc == 0xB) 1412 return MCDisassembler_Fail; 1413 break; 1414 default: 1415 break; 1416 } 1417 1418 MCOperand_CreateImm0(Inst, coproc); 1419 MCOperand_CreateImm0(Inst, CRd); 1420 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1421 return MCDisassembler_Fail; 1422 1423 switch (MCInst_getOpcode(Inst)) { 1424 case ARM_t2LDC2_OFFSET: 1425 case ARM_t2LDC2L_OFFSET: 1426 case ARM_t2LDC2_PRE: 1427 case ARM_t2LDC2L_PRE: 1428 case ARM_t2STC2_OFFSET: 1429 case ARM_t2STC2L_OFFSET: 1430 case ARM_t2STC2_PRE: 1431 case ARM_t2STC2L_PRE: 1432 case ARM_LDC2_OFFSET: 1433 case ARM_LDC2L_OFFSET: 1434 case ARM_LDC2_PRE: 1435 case ARM_LDC2L_PRE: 1436 case ARM_STC2_OFFSET: 1437 case ARM_STC2L_OFFSET: 1438 case ARM_STC2_PRE: 1439 case ARM_STC2L_PRE: 1440 case ARM_t2LDC_OFFSET: 1441 case ARM_t2LDCL_OFFSET: 1442 case ARM_t2LDC_PRE: 1443 case ARM_t2LDCL_PRE: 1444 case ARM_t2STC_OFFSET: 1445 case ARM_t2STCL_OFFSET: 1446 case ARM_t2STC_PRE: 1447 case ARM_t2STCL_PRE: 1448 case ARM_LDC_OFFSET: 1449 case ARM_LDCL_OFFSET: 1450 case ARM_LDC_PRE: 1451 case ARM_LDCL_PRE: 1452 case ARM_STC_OFFSET: 1453 case ARM_STCL_OFFSET: 1454 case ARM_STC_PRE: 1455 case ARM_STCL_PRE: 1456 imm = ARM_AM_getAM5Opc(U ? ARM_AM_add : ARM_AM_sub, (unsigned char)imm); 1457 MCOperand_CreateImm0(Inst, imm); 1458 break; 1459 case ARM_t2LDC2_POST: 1460 case ARM_t2LDC2L_POST: 1461 case ARM_t2STC2_POST: 1462 case ARM_t2STC2L_POST: 1463 case ARM_LDC2_POST: 1464 case ARM_LDC2L_POST: 1465 case ARM_STC2_POST: 1466 case ARM_STC2L_POST: 1467 case ARM_t2LDC_POST: 1468 case ARM_t2LDCL_POST: 1469 case ARM_t2STC_POST: 1470 case ARM_t2STCL_POST: 1471 case ARM_LDC_POST: 1472 case ARM_LDCL_POST: 1473 case ARM_STC_POST: 1474 case ARM_STCL_POST: 1475 imm |= U << 8; 1476 // fall through. 1477 default: 1478 // The 'option' variant doesn't encode 'U' in the immediate since 1479 // the immediate is unsigned [0,255]. 1480 MCOperand_CreateImm0(Inst, imm); 1481 break; 1482 } 1483 1484 switch (MCInst_getOpcode(Inst)) { 1485 case ARM_LDC_OFFSET: 1486 case ARM_LDC_PRE: 1487 case ARM_LDC_POST: 1488 case ARM_LDC_OPTION: 1489 case ARM_LDCL_OFFSET: 1490 case ARM_LDCL_PRE: 1491 case ARM_LDCL_POST: 1492 case ARM_LDCL_OPTION: 1493 case ARM_STC_OFFSET: 1494 case ARM_STC_PRE: 1495 case ARM_STC_POST: 1496 case ARM_STC_OPTION: 1497 case ARM_STCL_OFFSET: 1498 case ARM_STCL_PRE: 1499 case ARM_STCL_POST: 1500 case ARM_STCL_OPTION: 1501 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1502 return MCDisassembler_Fail; 1503 break; 1504 default: 1505 break; 1506 } 1507 1508 return S; 1509 } 1510 1511 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn, 1512 uint64_t Address, const void *Decoder) 1513 { 1514 DecodeStatus S = MCDisassembler_Success; 1515 ARM_AM_AddrOpc Op; 1516 ARM_AM_ShiftOpc Opc; 1517 bool writeback; 1518 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 1519 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); 1520 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); 1521 unsigned imm = fieldFromInstruction_4(Insn, 0, 12); 1522 unsigned pred = fieldFromInstruction_4(Insn, 28, 4); 1523 unsigned reg = fieldFromInstruction_4(Insn, 25, 1); 1524 unsigned P = fieldFromInstruction_4(Insn, 24, 1); 1525 unsigned W = fieldFromInstruction_4(Insn, 21, 1); 1526 unsigned idx_mode = 0, amt, tmp; 1527 1528 // On stores, the writeback operand precedes Rt. 1529 switch (MCInst_getOpcode(Inst)) { 1530 case ARM_STR_POST_IMM: 1531 case ARM_STR_POST_REG: 1532 case ARM_STRB_POST_IMM: 1533 case ARM_STRB_POST_REG: 1534 case ARM_STRT_POST_REG: 1535 case ARM_STRT_POST_IMM: 1536 case ARM_STRBT_POST_REG: 1537 case ARM_STRBT_POST_IMM: 1538 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1539 return MCDisassembler_Fail; 1540 break; 1541 default: 1542 break; 1543 } 1544 1545 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1546 return MCDisassembler_Fail; 1547 1548 // On loads, the writeback operand comes after Rt. 1549 switch (MCInst_getOpcode(Inst)) { 1550 case ARM_LDR_POST_IMM: 1551 case ARM_LDR_POST_REG: 1552 case ARM_LDRB_POST_IMM: 1553 case ARM_LDRB_POST_REG: 1554 case ARM_LDRBT_POST_REG: 1555 case ARM_LDRBT_POST_IMM: 1556 case ARM_LDRT_POST_REG: 1557 case ARM_LDRT_POST_IMM: 1558 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1559 return MCDisassembler_Fail; 1560 break; 1561 default: 1562 break; 1563 } 1564 1565 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1566 return MCDisassembler_Fail; 1567 1568 Op = ARM_AM_add; 1569 if (!fieldFromInstruction_4(Insn, 23, 1)) 1570 Op = ARM_AM_sub; 1571 1572 writeback = (P == 0) || (W == 1); 1573 if (P && writeback) 1574 idx_mode = ARMII_IndexModePre; 1575 else if (!P && writeback) 1576 idx_mode = ARMII_IndexModePost; 1577 1578 if (writeback && (Rn == 15 || Rn == Rt)) 1579 S = MCDisassembler_SoftFail; // UNPREDICTABLE 1580 1581 if (reg) { 1582 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1583 return MCDisassembler_Fail; 1584 Opc = ARM_AM_lsl; 1585 switch( fieldFromInstruction_4(Insn, 5, 2)) { 1586 case 0: 1587 Opc = ARM_AM_lsl; 1588 break; 1589 case 1: 1590 Opc = ARM_AM_lsr; 1591 break; 1592 case 2: 1593 Opc = ARM_AM_asr; 1594 break; 1595 case 3: 1596 Opc = ARM_AM_ror; 1597 break; 1598 default: 1599 return MCDisassembler_Fail; 1600 } 1601 amt = fieldFromInstruction_4(Insn, 7, 5); 1602 if (Opc == ARM_AM_ror && amt == 0) 1603 Opc = ARM_AM_rrx; 1604 imm = ARM_AM_getAM2Opc(Op, amt, Opc, idx_mode); 1605 1606 MCOperand_CreateImm0(Inst, imm); 1607 } else { 1608 MCOperand_CreateReg0(Inst, 0); 1609 tmp = ARM_AM_getAM2Opc(Op, imm, ARM_AM_lsl, idx_mode); 1610 MCOperand_CreateImm0(Inst, tmp); 1611 } 1612 1613 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1614 return MCDisassembler_Fail; 1615 1616 return S; 1617 } 1618 1619 static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Val, 1620 uint64_t Address, const void *Decoder) 1621 { 1622 DecodeStatus S = MCDisassembler_Success; 1623 ARM_AM_ShiftOpc ShOp; 1624 unsigned shift; 1625 unsigned Rn = fieldFromInstruction_4(Val, 13, 4); 1626 unsigned Rm = fieldFromInstruction_4(Val, 0, 4); 1627 unsigned type = fieldFromInstruction_4(Val, 5, 2); 1628 unsigned imm = fieldFromInstruction_4(Val, 7, 5); 1629 unsigned U = fieldFromInstruction_4(Val, 12, 1); 1630 1631 ShOp = ARM_AM_lsl; 1632 switch (type) { 1633 case 0: 1634 ShOp = ARM_AM_lsl; 1635 break; 1636 case 1: 1637 ShOp = ARM_AM_lsr; 1638 break; 1639 case 2: 1640 ShOp = ARM_AM_asr; 1641 break; 1642 case 3: 1643 ShOp = ARM_AM_ror; 1644 break; 1645 } 1646 1647 if (ShOp == ARM_AM_ror && imm == 0) 1648 ShOp = ARM_AM_rrx; 1649 1650 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1651 return MCDisassembler_Fail; 1652 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1653 return MCDisassembler_Fail; 1654 if (U) 1655 shift = ARM_AM_getAM2Opc(ARM_AM_add, imm, ShOp, 0); 1656 else 1657 shift = ARM_AM_getAM2Opc(ARM_AM_sub, imm, ShOp, 0); 1658 MCOperand_CreateImm0(Inst, shift); 1659 1660 return S; 1661 } 1662 1663 static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst, unsigned Insn, 1664 uint64_t Address, const void *Decoder) 1665 { 1666 DecodeStatus S = MCDisassembler_Success; 1667 1668 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); 1669 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 1670 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); 1671 unsigned type = fieldFromInstruction_4(Insn, 22, 1); 1672 unsigned imm = fieldFromInstruction_4(Insn, 8, 4); 1673 unsigned U = ((~fieldFromInstruction_4(Insn, 23, 1)) & 1) << 8; 1674 unsigned pred = fieldFromInstruction_4(Insn, 28, 4); 1675 unsigned W = fieldFromInstruction_4(Insn, 21, 1); 1676 unsigned P = fieldFromInstruction_4(Insn, 24, 1); 1677 unsigned Rt2 = Rt + 1; 1678 1679 bool writeback = (W == 1) | (P == 0); 1680 1681 // For {LD,ST}RD, Rt must be even, else undefined. 1682 switch (MCInst_getOpcode(Inst)) { 1683 case ARM_STRD: 1684 case ARM_STRD_PRE: 1685 case ARM_STRD_POST: 1686 case ARM_LDRD: 1687 case ARM_LDRD_PRE: 1688 case ARM_LDRD_POST: 1689 if (Rt & 0x1) S = MCDisassembler_SoftFail; 1690 break; 1691 default: 1692 break; 1693 } 1694 switch (MCInst_getOpcode(Inst)) { 1695 case ARM_STRD: 1696 case ARM_STRD_PRE: 1697 case ARM_STRD_POST: 1698 if (P == 0 && W == 1) 1699 S = MCDisassembler_SoftFail; 1700 1701 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1702 S = MCDisassembler_SoftFail; 1703 if (type && Rm == 15) 1704 S = MCDisassembler_SoftFail; 1705 if (Rt2 == 15) 1706 S = MCDisassembler_SoftFail; 1707 if (!type && fieldFromInstruction_4(Insn, 8, 4)) 1708 S = MCDisassembler_SoftFail; 1709 break; 1710 case ARM_STRH: 1711 case ARM_STRH_PRE: 1712 case ARM_STRH_POST: 1713 if (Rt == 15) 1714 S = MCDisassembler_SoftFail; 1715 if (writeback && (Rn == 15 || Rn == Rt)) 1716 S = MCDisassembler_SoftFail; 1717 if (!type && Rm == 15) 1718 S = MCDisassembler_SoftFail; 1719 break; 1720 case ARM_LDRD: 1721 case ARM_LDRD_PRE: 1722 case ARM_LDRD_POST: 1723 if (type && Rn == 15){ 1724 if (Rt2 == 15) 1725 S = MCDisassembler_SoftFail; 1726 break; 1727 } 1728 if (P == 0 && W == 1) 1729 S = MCDisassembler_SoftFail; 1730 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1731 S = MCDisassembler_SoftFail; 1732 if (!type && writeback && Rn == 15) 1733 S = MCDisassembler_SoftFail; 1734 if (writeback && (Rn == Rt || Rn == Rt2)) 1735 S = MCDisassembler_SoftFail; 1736 break; 1737 case ARM_LDRH: 1738 case ARM_LDRH_PRE: 1739 case ARM_LDRH_POST: 1740 if (type && Rn == 15){ 1741 if (Rt == 15) 1742 S = MCDisassembler_SoftFail; 1743 break; 1744 } 1745 if (Rt == 15) 1746 S = MCDisassembler_SoftFail; 1747 if (!type && Rm == 15) 1748 S = MCDisassembler_SoftFail; 1749 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1750 S = MCDisassembler_SoftFail; 1751 break; 1752 case ARM_LDRSH: 1753 case ARM_LDRSH_PRE: 1754 case ARM_LDRSH_POST: 1755 case ARM_LDRSB: 1756 case ARM_LDRSB_PRE: 1757 case ARM_LDRSB_POST: 1758 if (type && Rn == 15){ 1759 if (Rt == 15) 1760 S = MCDisassembler_SoftFail; 1761 break; 1762 } 1763 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1764 S = MCDisassembler_SoftFail; 1765 if (!type && (Rt == 15 || Rm == 15)) 1766 S = MCDisassembler_SoftFail; 1767 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1768 S = MCDisassembler_SoftFail; 1769 break; 1770 default: 1771 break; 1772 } 1773 1774 if (writeback) { // Writeback 1775 Inst->writeback = true; 1776 if (P) 1777 U |= ARMII_IndexModePre << 9; 1778 else 1779 U |= ARMII_IndexModePost << 9; 1780 1781 // On stores, the writeback operand precedes Rt. 1782 switch (MCInst_getOpcode(Inst)) { 1783 case ARM_STRD: 1784 case ARM_STRD_PRE: 1785 case ARM_STRD_POST: 1786 case ARM_STRH: 1787 case ARM_STRH_PRE: 1788 case ARM_STRH_POST: 1789 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1790 return MCDisassembler_Fail; 1791 break; 1792 default: 1793 break; 1794 } 1795 } 1796 1797 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1798 return MCDisassembler_Fail; 1799 switch (MCInst_getOpcode(Inst)) { 1800 case ARM_STRD: 1801 case ARM_STRD_PRE: 1802 case ARM_STRD_POST: 1803 case ARM_LDRD: 1804 case ARM_LDRD_PRE: 1805 case ARM_LDRD_POST: 1806 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1807 return MCDisassembler_Fail; 1808 break; 1809 default: 1810 break; 1811 } 1812 1813 if (writeback) { 1814 // On loads, the writeback operand comes after Rt. 1815 switch (MCInst_getOpcode(Inst)) { 1816 case ARM_LDRD: 1817 case ARM_LDRD_PRE: 1818 case ARM_LDRD_POST: 1819 case ARM_LDRH: 1820 case ARM_LDRH_PRE: 1821 case ARM_LDRH_POST: 1822 case ARM_LDRSH: 1823 case ARM_LDRSH_PRE: 1824 case ARM_LDRSH_POST: 1825 case ARM_LDRSB: 1826 case ARM_LDRSB_PRE: 1827 case ARM_LDRSB_POST: 1828 case ARM_LDRHTr: 1829 case ARM_LDRSBTr: 1830 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1831 return MCDisassembler_Fail; 1832 break; 1833 default: 1834 break; 1835 } 1836 } 1837 1838 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1839 return MCDisassembler_Fail; 1840 1841 if (type) { 1842 MCOperand_CreateReg0(Inst, 0); 1843 MCOperand_CreateImm0(Inst, U | (imm << 4) | Rm); 1844 } else { 1845 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1846 return MCDisassembler_Fail; 1847 MCOperand_CreateImm0(Inst, U); 1848 } 1849 1850 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1851 return MCDisassembler_Fail; 1852 1853 return S; 1854 } 1855 1856 static DecodeStatus DecodeRFEInstruction(MCInst *Inst, unsigned Insn, 1857 uint64_t Address, const void *Decoder) 1858 { 1859 DecodeStatus S = MCDisassembler_Success; 1860 1861 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 1862 unsigned mode = fieldFromInstruction_4(Insn, 23, 2); 1863 1864 switch (mode) { 1865 case 0: 1866 mode = ARM_AM_da; 1867 break; 1868 case 1: 1869 mode = ARM_AM_ia; 1870 break; 1871 case 2: 1872 mode = ARM_AM_db; 1873 break; 1874 case 3: 1875 mode = ARM_AM_ib; 1876 break; 1877 } 1878 1879 MCOperand_CreateImm0(Inst, mode); 1880 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1881 return MCDisassembler_Fail; 1882 1883 return S; 1884 } 1885 1886 static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn, 1887 uint64_t Address, const void *Decoder) 1888 { 1889 DecodeStatus S = MCDisassembler_Success; 1890 1891 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); 1892 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); 1893 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 1894 unsigned pred = fieldFromInstruction_4(Insn, 28, 4); 1895 1896 if (pred == 0xF) 1897 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1898 1899 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1900 return MCDisassembler_Fail; 1901 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1902 return MCDisassembler_Fail; 1903 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1904 return MCDisassembler_Fail; 1905 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1906 return MCDisassembler_Fail; 1907 return S; 1908 } 1909 1910 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst *Inst, 1911 unsigned Insn, uint64_t Address, const void *Decoder) 1912 { 1913 DecodeStatus S = MCDisassembler_Success; 1914 1915 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 1916 unsigned pred = fieldFromInstruction_4(Insn, 28, 4); 1917 unsigned reglist = fieldFromInstruction_4(Insn, 0, 16); 1918 1919 if (pred == 0xF) { 1920 // Ambiguous with RFE and SRS 1921 switch (MCInst_getOpcode(Inst)) { 1922 case ARM_LDMDA: 1923 MCInst_setOpcode(Inst, ARM_RFEDA); 1924 break; 1925 case ARM_LDMDA_UPD: 1926 MCInst_setOpcode(Inst, ARM_RFEDA_UPD); 1927 break; 1928 case ARM_LDMDB: 1929 MCInst_setOpcode(Inst, ARM_RFEDB); 1930 break; 1931 case ARM_LDMDB_UPD: 1932 MCInst_setOpcode(Inst, ARM_RFEDB_UPD); 1933 break; 1934 case ARM_LDMIA: 1935 MCInst_setOpcode(Inst, ARM_RFEIA); 1936 break; 1937 case ARM_LDMIA_UPD: 1938 MCInst_setOpcode(Inst, ARM_RFEIA_UPD); 1939 break; 1940 case ARM_LDMIB: 1941 MCInst_setOpcode(Inst, ARM_RFEIB); 1942 break; 1943 case ARM_LDMIB_UPD: 1944 MCInst_setOpcode(Inst, ARM_RFEIB_UPD); 1945 break; 1946 case ARM_STMDA: 1947 MCInst_setOpcode(Inst, ARM_SRSDA); 1948 break; 1949 case ARM_STMDA_UPD: 1950 MCInst_setOpcode(Inst, ARM_SRSDA_UPD); 1951 break; 1952 case ARM_STMDB: 1953 MCInst_setOpcode(Inst, ARM_SRSDB); 1954 break; 1955 case ARM_STMDB_UPD: 1956 MCInst_setOpcode(Inst, ARM_SRSDB_UPD); 1957 break; 1958 case ARM_STMIA: 1959 MCInst_setOpcode(Inst, ARM_SRSIA); 1960 break; 1961 case ARM_STMIA_UPD: 1962 MCInst_setOpcode(Inst, ARM_SRSIA_UPD); 1963 break; 1964 case ARM_STMIB: 1965 MCInst_setOpcode(Inst, ARM_SRSIB); 1966 break; 1967 case ARM_STMIB_UPD: 1968 MCInst_setOpcode(Inst, ARM_SRSIB_UPD); 1969 break; 1970 default: 1971 return MCDisassembler_Fail; 1972 } 1973 1974 // For stores (which become SRS's, the only operand is the mode. 1975 if (fieldFromInstruction_4(Insn, 20, 1) == 0) { 1976 // Check SRS encoding constraints 1977 if (!(fieldFromInstruction_4(Insn, 22, 1) == 1 && 1978 fieldFromInstruction_4(Insn, 20, 1) == 0)) 1979 return MCDisassembler_Fail; 1980 1981 MCOperand_CreateImm0(Inst, fieldFromInstruction_4(Insn, 0, 4)); 1982 return S; 1983 } 1984 1985 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1986 } 1987 1988 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1989 return MCDisassembler_Fail; 1990 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1991 return MCDisassembler_Fail; // Tied 1992 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1993 return MCDisassembler_Fail; 1994 if (!Check(&S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1995 return MCDisassembler_Fail; 1996 1997 return S; 1998 } 1999 2000 static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn, 2001 uint64_t Address, const void *Decoder) 2002 { 2003 unsigned imod = fieldFromInstruction_4(Insn, 18, 2); 2004 unsigned M = fieldFromInstruction_4(Insn, 17, 1); 2005 unsigned iflags = fieldFromInstruction_4(Insn, 6, 3); 2006 unsigned mode = fieldFromInstruction_4(Insn, 0, 5); 2007 2008 DecodeStatus S = MCDisassembler_Success; 2009 2010 // This decoder is called from multiple location that do not check 2011 // the full encoding is valid before they do. 2012 if (fieldFromInstruction_4(Insn, 5, 1) != 0 || 2013 fieldFromInstruction_4(Insn, 16, 1) != 0 || 2014 fieldFromInstruction_4(Insn, 20, 8) != 0x10) 2015 return MCDisassembler_Fail; 2016 2017 // imod == '01' --> UNPREDICTABLE 2018 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2019 // return failure here. The '01' imod value is unprintable, so there's 2020 // nothing useful we could do even if we returned UNPREDICTABLE. 2021 2022 if (imod == 1) return MCDisassembler_Fail; 2023 2024 if (imod && M) { 2025 MCInst_setOpcode(Inst, ARM_CPS3p); 2026 MCOperand_CreateImm0(Inst, imod); 2027 MCOperand_CreateImm0(Inst, iflags); 2028 MCOperand_CreateImm0(Inst, mode); 2029 } else if (imod && !M) { 2030 MCInst_setOpcode(Inst, ARM_CPS2p); 2031 MCOperand_CreateImm0(Inst, imod); 2032 MCOperand_CreateImm0(Inst, iflags); 2033 if (mode) S = MCDisassembler_SoftFail; 2034 } else if (!imod && M) { 2035 MCInst_setOpcode(Inst, ARM_CPS1p); 2036 MCOperand_CreateImm0(Inst, mode); 2037 if (iflags) S = MCDisassembler_SoftFail; 2038 } else { 2039 // imod == '00' && M == '0' --> UNPREDICTABLE 2040 MCInst_setOpcode(Inst, ARM_CPS1p); 2041 MCOperand_CreateImm0(Inst, mode); 2042 S = MCDisassembler_SoftFail; 2043 } 2044 2045 return S; 2046 } 2047 2048 static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn, 2049 uint64_t Address, const void *Decoder) 2050 { 2051 unsigned imod = fieldFromInstruction_4(Insn, 9, 2); 2052 unsigned M = fieldFromInstruction_4(Insn, 8, 1); 2053 unsigned iflags = fieldFromInstruction_4(Insn, 5, 3); 2054 unsigned mode = fieldFromInstruction_4(Insn, 0, 5); 2055 2056 DecodeStatus S = MCDisassembler_Success; 2057 2058 // imod == '01' --> UNPREDICTABLE 2059 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2060 // return failure here. The '01' imod value is unprintable, so there's 2061 // nothing useful we could do even if we returned UNPREDICTABLE. 2062 2063 if (imod == 1) return MCDisassembler_Fail; 2064 2065 if (imod && M) { 2066 MCInst_setOpcode(Inst, ARM_t2CPS3p); 2067 MCOperand_CreateImm0(Inst, imod); 2068 MCOperand_CreateImm0(Inst, iflags); 2069 MCOperand_CreateImm0(Inst, mode); 2070 } else if (imod && !M) { 2071 MCInst_setOpcode(Inst, ARM_t2CPS2p); 2072 MCOperand_CreateImm0(Inst, imod); 2073 MCOperand_CreateImm0(Inst, iflags); 2074 if (mode) S = MCDisassembler_SoftFail; 2075 } else if (!imod && M) { 2076 MCInst_setOpcode(Inst, ARM_t2CPS1p); 2077 MCOperand_CreateImm0(Inst, mode); 2078 if (iflags) S = MCDisassembler_SoftFail; 2079 } else { 2080 // imod == '00' && M == '0' --> this is a HINT instruction 2081 int imm = fieldFromInstruction_4(Insn, 0, 8); 2082 // HINT are defined only for immediate in [0..4] 2083 if(imm > 4) return MCDisassembler_Fail; 2084 MCInst_setOpcode(Inst, ARM_t2HINT); 2085 MCOperand_CreateImm0(Inst, imm); 2086 } 2087 2088 return S; 2089 } 2090 2091 static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn, 2092 uint64_t Address, const void *Decoder) 2093 { 2094 DecodeStatus S = MCDisassembler_Success; 2095 2096 unsigned Rd = fieldFromInstruction_4(Insn, 8, 4); 2097 unsigned imm = 0; 2098 2099 imm |= (fieldFromInstruction_4(Insn, 0, 8) << 0); 2100 imm |= (fieldFromInstruction_4(Insn, 12, 3) << 8); 2101 imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12); 2102 imm |= (fieldFromInstruction_4(Insn, 26, 1) << 11); 2103 2104 if (MCInst_getOpcode(Inst) == ARM_t2MOVTi16) 2105 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2106 return MCDisassembler_Fail; 2107 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2108 return MCDisassembler_Fail; 2109 2110 MCOperand_CreateImm0(Inst, imm); 2111 2112 return S; 2113 } 2114 2115 static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn, 2116 uint64_t Address, const void *Decoder) 2117 { 2118 DecodeStatus S = MCDisassembler_Success; 2119 2120 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); 2121 unsigned pred = fieldFromInstruction_4(Insn, 28, 4); 2122 unsigned imm = 0; 2123 2124 imm |= (fieldFromInstruction_4(Insn, 0, 12) << 0); 2125 imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12); 2126 2127 if (MCInst_getOpcode(Inst) == ARM_MOVTi16) 2128 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2129 return MCDisassembler_Fail; 2130 2131 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2132 return MCDisassembler_Fail; 2133 2134 MCOperand_CreateImm0(Inst, imm); 2135 2136 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2137 return MCDisassembler_Fail; 2138 2139 return S; 2140 } 2141 2142 static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn, 2143 uint64_t Address, const void *Decoder) 2144 { 2145 DecodeStatus S = MCDisassembler_Success; 2146 2147 unsigned Rd = fieldFromInstruction_4(Insn, 16, 4); 2148 unsigned Rn = fieldFromInstruction_4(Insn, 0, 4); 2149 unsigned Rm = fieldFromInstruction_4(Insn, 8, 4); 2150 unsigned Ra = fieldFromInstruction_4(Insn, 12, 4); 2151 unsigned pred = fieldFromInstruction_4(Insn, 28, 4); 2152 2153 if (pred == 0xF) 2154 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2155 2156 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2157 return MCDisassembler_Fail; 2158 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2159 return MCDisassembler_Fail; 2160 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2161 return MCDisassembler_Fail; 2162 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2163 return MCDisassembler_Fail; 2164 2165 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2166 return MCDisassembler_Fail; 2167 2168 return S; 2169 } 2170 2171 static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val, 2172 uint64_t Address, const void *Decoder) 2173 { 2174 DecodeStatus S = MCDisassembler_Success; 2175 2176 unsigned add = fieldFromInstruction_4(Val, 12, 1); 2177 unsigned imm = fieldFromInstruction_4(Val, 0, 12); 2178 unsigned Rn = fieldFromInstruction_4(Val, 13, 4); 2179 2180 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2181 return MCDisassembler_Fail; 2182 2183 if (!add) imm *= (unsigned int)-1; 2184 if (imm == 0 && !add) imm = (unsigned int)INT32_MIN; 2185 MCOperand_CreateImm0(Inst, imm); 2186 //if (Rn == 15) 2187 // tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2188 2189 return S; 2190 } 2191 2192 static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val, 2193 uint64_t Address, const void *Decoder) 2194 { 2195 DecodeStatus S = MCDisassembler_Success; 2196 2197 unsigned Rn = fieldFromInstruction_4(Val, 9, 4); 2198 unsigned U = fieldFromInstruction_4(Val, 8, 1); 2199 unsigned imm = fieldFromInstruction_4(Val, 0, 8); 2200 2201 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2202 return MCDisassembler_Fail; 2203 2204 if (U) 2205 MCOperand_CreateImm0(Inst, ARM_AM_getAM5Opc(ARM_AM_add, (unsigned char)imm)); 2206 else 2207 MCOperand_CreateImm0(Inst, ARM_AM_getAM5Opc(ARM_AM_sub, (unsigned char)imm)); 2208 2209 return S; 2210 } 2211 2212 static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val, 2213 uint64_t Address, const void *Decoder) 2214 { 2215 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2216 } 2217 2218 static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn, 2219 uint64_t Address, const void *Decoder) 2220 { 2221 DecodeStatus Status = MCDisassembler_Success; 2222 2223 // Note the J1 and J2 values are from the encoded instruction. So here 2224 // change them to I1 and I2 values via as documented: 2225 // I1 = NOT(J1 EOR S); 2226 // I2 = NOT(J2 EOR S); 2227 // and build the imm32 with one trailing zero as documented: 2228 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2229 unsigned S = fieldFromInstruction_4(Insn, 26, 1); 2230 unsigned J1 = fieldFromInstruction_4(Insn, 13, 1); 2231 unsigned J2 = fieldFromInstruction_4(Insn, 11, 1); 2232 unsigned I1 = !(J1 ^ S); 2233 unsigned I2 = !(J2 ^ S); 2234 unsigned imm10 = fieldFromInstruction_4(Insn, 16, 10); 2235 unsigned imm11 = fieldFromInstruction_4(Insn, 0, 11); 2236 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2237 int imm32 = SignExtend32(tmp << 1, 25); 2238 MCOperand_CreateImm0(Inst, imm32); 2239 2240 return Status; 2241 } 2242 2243 static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst, unsigned Insn, 2244 uint64_t Address, const void *Decoder) 2245 { 2246 DecodeStatus S = MCDisassembler_Success; 2247 2248 unsigned pred = fieldFromInstruction_4(Insn, 28, 4); 2249 unsigned imm = fieldFromInstruction_4(Insn, 0, 24) << 2; 2250 2251 if (pred == 0xF) { 2252 MCInst_setOpcode(Inst, ARM_BLXi); 2253 imm |= fieldFromInstruction_4(Insn, 24, 1) << 1; 2254 MCOperand_CreateImm0(Inst, SignExtend32(imm, 26)); 2255 return S; 2256 } 2257 2258 MCOperand_CreateImm0(Inst, SignExtend32(imm, 26)); 2259 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2260 return MCDisassembler_Fail; 2261 2262 return S; 2263 } 2264 2265 2266 static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val, 2267 uint64_t Address, const void *Decoder) 2268 { 2269 DecodeStatus S = MCDisassembler_Success; 2270 2271 unsigned Rm = fieldFromInstruction_4(Val, 0, 4); 2272 unsigned align = fieldFromInstruction_4(Val, 4, 2); 2273 2274 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2275 return MCDisassembler_Fail; 2276 if (!align) 2277 MCOperand_CreateImm0(Inst, 0); 2278 else 2279 MCOperand_CreateImm0(Inst, 4 << align); 2280 2281 return S; 2282 } 2283 2284 static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Insn, 2285 uint64_t Address, const void *Decoder) 2286 { 2287 DecodeStatus S = MCDisassembler_Success; 2288 unsigned wb, Rn, Rm; 2289 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); 2290 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; 2291 wb = fieldFromInstruction_4(Insn, 16, 4); 2292 Rn = fieldFromInstruction_4(Insn, 16, 4); 2293 Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4; 2294 Rm = fieldFromInstruction_4(Insn, 0, 4); 2295 2296 // First output register 2297 switch (MCInst_getOpcode(Inst)) { 2298 case ARM_VLD1q16: case ARM_VLD1q32: case ARM_VLD1q64: case ARM_VLD1q8: 2299 case ARM_VLD1q16wb_fixed: case ARM_VLD1q16wb_register: 2300 case ARM_VLD1q32wb_fixed: case ARM_VLD1q32wb_register: 2301 case ARM_VLD1q64wb_fixed: case ARM_VLD1q64wb_register: 2302 case ARM_VLD1q8wb_fixed: case ARM_VLD1q8wb_register: 2303 case ARM_VLD2d16: case ARM_VLD2d32: case ARM_VLD2d8: 2304 case ARM_VLD2d16wb_fixed: case ARM_VLD2d16wb_register: 2305 case ARM_VLD2d32wb_fixed: case ARM_VLD2d32wb_register: 2306 case ARM_VLD2d8wb_fixed: case ARM_VLD2d8wb_register: 2307 if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2308 return MCDisassembler_Fail; 2309 break; 2310 case ARM_VLD2b16: 2311 case ARM_VLD2b32: 2312 case ARM_VLD2b8: 2313 case ARM_VLD2b16wb_fixed: 2314 case ARM_VLD2b16wb_register: 2315 case ARM_VLD2b32wb_fixed: 2316 case ARM_VLD2b32wb_register: 2317 case ARM_VLD2b8wb_fixed: 2318 case ARM_VLD2b8wb_register: 2319 if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2320 return MCDisassembler_Fail; 2321 break; 2322 default: 2323 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2324 return MCDisassembler_Fail; 2325 } 2326 2327 // Second output register 2328 switch (MCInst_getOpcode(Inst)) { 2329 case ARM_VLD3d8: 2330 case ARM_VLD3d16: 2331 case ARM_VLD3d32: 2332 case ARM_VLD3d8_UPD: 2333 case ARM_VLD3d16_UPD: 2334 case ARM_VLD3d32_UPD: 2335 case ARM_VLD4d8: 2336 case ARM_VLD4d16: 2337 case ARM_VLD4d32: 2338 case ARM_VLD4d8_UPD: 2339 case ARM_VLD4d16_UPD: 2340 case ARM_VLD4d32_UPD: 2341 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2342 return MCDisassembler_Fail; 2343 break; 2344 case ARM_VLD3q8: 2345 case ARM_VLD3q16: 2346 case ARM_VLD3q32: 2347 case ARM_VLD3q8_UPD: 2348 case ARM_VLD3q16_UPD: 2349 case ARM_VLD3q32_UPD: 2350 case ARM_VLD4q8: 2351 case ARM_VLD4q16: 2352 case ARM_VLD4q32: 2353 case ARM_VLD4q8_UPD: 2354 case ARM_VLD4q16_UPD: 2355 case ARM_VLD4q32_UPD: 2356 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2357 return MCDisassembler_Fail; 2358 default: 2359 break; 2360 } 2361 2362 // Third output register 2363 switch(MCInst_getOpcode(Inst)) { 2364 case ARM_VLD3d8: 2365 case ARM_VLD3d16: 2366 case ARM_VLD3d32: 2367 case ARM_VLD3d8_UPD: 2368 case ARM_VLD3d16_UPD: 2369 case ARM_VLD3d32_UPD: 2370 case ARM_VLD4d8: 2371 case ARM_VLD4d16: 2372 case ARM_VLD4d32: 2373 case ARM_VLD4d8_UPD: 2374 case ARM_VLD4d16_UPD: 2375 case ARM_VLD4d32_UPD: 2376 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2377 return MCDisassembler_Fail; 2378 break; 2379 case ARM_VLD3q8: 2380 case ARM_VLD3q16: 2381 case ARM_VLD3q32: 2382 case ARM_VLD3q8_UPD: 2383 case ARM_VLD3q16_UPD: 2384 case ARM_VLD3q32_UPD: 2385 case ARM_VLD4q8: 2386 case ARM_VLD4q16: 2387 case ARM_VLD4q32: 2388 case ARM_VLD4q8_UPD: 2389 case ARM_VLD4q16_UPD: 2390 case ARM_VLD4q32_UPD: 2391 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2392 return MCDisassembler_Fail; 2393 break; 2394 default: 2395 break; 2396 } 2397 2398 // Fourth output register 2399 switch (MCInst_getOpcode(Inst)) { 2400 case ARM_VLD4d8: 2401 case ARM_VLD4d16: 2402 case ARM_VLD4d32: 2403 case ARM_VLD4d8_UPD: 2404 case ARM_VLD4d16_UPD: 2405 case ARM_VLD4d32_UPD: 2406 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2407 return MCDisassembler_Fail; 2408 break; 2409 case ARM_VLD4q8: 2410 case ARM_VLD4q16: 2411 case ARM_VLD4q32: 2412 case ARM_VLD4q8_UPD: 2413 case ARM_VLD4q16_UPD: 2414 case ARM_VLD4q32_UPD: 2415 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2416 return MCDisassembler_Fail; 2417 break; 2418 default: 2419 break; 2420 } 2421 2422 // Writeback operand 2423 switch (MCInst_getOpcode(Inst)) { 2424 case ARM_VLD1d8wb_fixed: 2425 case ARM_VLD1d16wb_fixed: 2426 case ARM_VLD1d32wb_fixed: 2427 case ARM_VLD1d64wb_fixed: 2428 case ARM_VLD1d8wb_register: 2429 case ARM_VLD1d16wb_register: 2430 case ARM_VLD1d32wb_register: 2431 case ARM_VLD1d64wb_register: 2432 case ARM_VLD1q8wb_fixed: 2433 case ARM_VLD1q16wb_fixed: 2434 case ARM_VLD1q32wb_fixed: 2435 case ARM_VLD1q64wb_fixed: 2436 case ARM_VLD1q8wb_register: 2437 case ARM_VLD1q16wb_register: 2438 case ARM_VLD1q32wb_register: 2439 case ARM_VLD1q64wb_register: 2440 case ARM_VLD1d8Twb_fixed: 2441 case ARM_VLD1d8Twb_register: 2442 case ARM_VLD1d16Twb_fixed: 2443 case ARM_VLD1d16Twb_register: 2444 case ARM_VLD1d32Twb_fixed: 2445 case ARM_VLD1d32Twb_register: 2446 case ARM_VLD1d64Twb_fixed: 2447 case ARM_VLD1d64Twb_register: 2448 case ARM_VLD1d8Qwb_fixed: 2449 case ARM_VLD1d8Qwb_register: 2450 case ARM_VLD1d16Qwb_fixed: 2451 case ARM_VLD1d16Qwb_register: 2452 case ARM_VLD1d32Qwb_fixed: 2453 case ARM_VLD1d32Qwb_register: 2454 case ARM_VLD1d64Qwb_fixed: 2455 case ARM_VLD1d64Qwb_register: 2456 case ARM_VLD2d8wb_fixed: 2457 case ARM_VLD2d16wb_fixed: 2458 case ARM_VLD2d32wb_fixed: 2459 case ARM_VLD2q8wb_fixed: 2460 case ARM_VLD2q16wb_fixed: 2461 case ARM_VLD2q32wb_fixed: 2462 case ARM_VLD2d8wb_register: 2463 case ARM_VLD2d16wb_register: 2464 case ARM_VLD2d32wb_register: 2465 case ARM_VLD2q8wb_register: 2466 case ARM_VLD2q16wb_register: 2467 case ARM_VLD2q32wb_register: 2468 case ARM_VLD2b8wb_fixed: 2469 case ARM_VLD2b16wb_fixed: 2470 case ARM_VLD2b32wb_fixed: 2471 case ARM_VLD2b8wb_register: 2472 case ARM_VLD2b16wb_register: 2473 case ARM_VLD2b32wb_register: 2474 MCOperand_CreateImm0(Inst, 0); 2475 break; 2476 case ARM_VLD3d8_UPD: 2477 case ARM_VLD3d16_UPD: 2478 case ARM_VLD3d32_UPD: 2479 case ARM_VLD3q8_UPD: 2480 case ARM_VLD3q16_UPD: 2481 case ARM_VLD3q32_UPD: 2482 case ARM_VLD4d8_UPD: 2483 case ARM_VLD4d16_UPD: 2484 case ARM_VLD4d32_UPD: 2485 case ARM_VLD4q8_UPD: 2486 case ARM_VLD4q16_UPD: 2487 case ARM_VLD4q32_UPD: 2488 if (!Check(&S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2489 return MCDisassembler_Fail; 2490 break; 2491 default: 2492 break; 2493 } 2494 2495 // AddrMode6 Base (register+alignment) 2496 if (!Check(&S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2497 return MCDisassembler_Fail; 2498 2499 // AddrMode6 Offset (register) 2500 switch (MCInst_getOpcode(Inst)) { 2501 default: 2502 // The below have been updated to have explicit am6offset split 2503 // between fixed and register offset. For those instructions not 2504 // yet updated, we need to add an additional reg0 operand for the 2505 // fixed variant. 2506 // 2507 // The fixed offset encodes as Rm == 0xd, so we check for that. 2508 if (Rm == 0xd) { 2509 MCOperand_CreateReg0(Inst, 0); 2510 break; 2511 } 2512 // Fall through to handle the register offset variant. 2513 case ARM_VLD1d8wb_fixed: 2514 case ARM_VLD1d16wb_fixed: 2515 case ARM_VLD1d32wb_fixed: 2516 case ARM_VLD1d64wb_fixed: 2517 case ARM_VLD1d8Twb_fixed: 2518 case ARM_VLD1d16Twb_fixed: 2519 case ARM_VLD1d32Twb_fixed: 2520 case ARM_VLD1d64Twb_fixed: 2521 case ARM_VLD1d8Qwb_fixed: 2522 case ARM_VLD1d16Qwb_fixed: 2523 case ARM_VLD1d32Qwb_fixed: 2524 case ARM_VLD1d64Qwb_fixed: 2525 case ARM_VLD1d8wb_register: 2526 case ARM_VLD1d16wb_register: 2527 case ARM_VLD1d32wb_register: 2528 case ARM_VLD1d64wb_register: 2529 case ARM_VLD1q8wb_fixed: 2530 case ARM_VLD1q16wb_fixed: 2531 case ARM_VLD1q32wb_fixed: 2532 case ARM_VLD1q64wb_fixed: 2533 case ARM_VLD1q8wb_register: 2534 case ARM_VLD1q16wb_register: 2535 case ARM_VLD1q32wb_register: 2536 case ARM_VLD1q64wb_register: 2537 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2538 // variant encodes Rm == 0xf. Anything else is a register offset post- 2539 // increment and we need to add the register operand to the instruction. 2540 if (Rm != 0xD && Rm != 0xF && 2541 !Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2542 return MCDisassembler_Fail; 2543 break; 2544 case ARM_VLD2d8wb_fixed: 2545 case ARM_VLD2d16wb_fixed: 2546 case ARM_VLD2d32wb_fixed: 2547 case ARM_VLD2b8wb_fixed: 2548 case ARM_VLD2b16wb_fixed: 2549 case ARM_VLD2b32wb_fixed: 2550 case ARM_VLD2q8wb_fixed: 2551 case ARM_VLD2q16wb_fixed: 2552 case ARM_VLD2q32wb_fixed: 2553 break; 2554 } 2555 2556 return S; 2557 } 2558 2559 static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Insn, 2560 uint64_t Address, const void *Decoder) 2561 { 2562 unsigned load; 2563 unsigned type = fieldFromInstruction_4(Insn, 8, 4); 2564 unsigned align = fieldFromInstruction_4(Insn, 4, 2); 2565 if (type == 6 && (align & 2)) return MCDisassembler_Fail; 2566 if (type == 7 && (align & 2)) return MCDisassembler_Fail; 2567 if (type == 10 && align == 3) return MCDisassembler_Fail; 2568 2569 load = fieldFromInstruction_4(Insn, 21, 1); 2570 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2571 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2572 } 2573 2574 static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Insn, 2575 uint64_t Address, const void *Decoder) 2576 { 2577 unsigned type, align, load; 2578 unsigned size = fieldFromInstruction_4(Insn, 6, 2); 2579 if (size == 3) return MCDisassembler_Fail; 2580 2581 type = fieldFromInstruction_4(Insn, 8, 4); 2582 align = fieldFromInstruction_4(Insn, 4, 2); 2583 if (type == 8 && align == 3) return MCDisassembler_Fail; 2584 if (type == 9 && align == 3) return MCDisassembler_Fail; 2585 2586 load = fieldFromInstruction_4(Insn, 21, 1); 2587 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2588 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2589 } 2590 2591 static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Insn, 2592 uint64_t Address, const void *Decoder) 2593 { 2594 unsigned align, load; 2595 unsigned size = fieldFromInstruction_4(Insn, 6, 2); 2596 if (size == 3) return MCDisassembler_Fail; 2597 2598 align = fieldFromInstruction_4(Insn, 4, 2); 2599 if (align & 2) return MCDisassembler_Fail; 2600 2601 load = fieldFromInstruction_4(Insn, 21, 1); 2602 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2603 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2604 } 2605 2606 static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Insn, 2607 uint64_t Address, const void *Decoder) 2608 { 2609 unsigned load; 2610 unsigned size = fieldFromInstruction_4(Insn, 6, 2); 2611 if (size == 3) return MCDisassembler_Fail; 2612 2613 load = fieldFromInstruction_4(Insn, 21, 1); 2614 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2615 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2616 } 2617 2618 static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Insn, 2619 uint64_t Address, const void *Decoder) 2620 { 2621 DecodeStatus S = MCDisassembler_Success; 2622 unsigned wb, Rn, Rm; 2623 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); 2624 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; 2625 wb = fieldFromInstruction_4(Insn, 16, 4); 2626 Rn = fieldFromInstruction_4(Insn, 16, 4); 2627 Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4; 2628 Rm = fieldFromInstruction_4(Insn, 0, 4); 2629 2630 // Writeback Operand 2631 switch (MCInst_getOpcode(Inst)) { 2632 case ARM_VST1d8wb_fixed: 2633 case ARM_VST1d16wb_fixed: 2634 case ARM_VST1d32wb_fixed: 2635 case ARM_VST1d64wb_fixed: 2636 case ARM_VST1d8wb_register: 2637 case ARM_VST1d16wb_register: 2638 case ARM_VST1d32wb_register: 2639 case ARM_VST1d64wb_register: 2640 case ARM_VST1q8wb_fixed: 2641 case ARM_VST1q16wb_fixed: 2642 case ARM_VST1q32wb_fixed: 2643 case ARM_VST1q64wb_fixed: 2644 case ARM_VST1q8wb_register: 2645 case ARM_VST1q16wb_register: 2646 case ARM_VST1q32wb_register: 2647 case ARM_VST1q64wb_register: 2648 case ARM_VST1d8Twb_fixed: 2649 case ARM_VST1d16Twb_fixed: 2650 case ARM_VST1d32Twb_fixed: 2651 case ARM_VST1d64Twb_fixed: 2652 case ARM_VST1d8Twb_register: 2653 case ARM_VST1d16Twb_register: 2654 case ARM_VST1d32Twb_register: 2655 case ARM_VST1d64Twb_register: 2656 case ARM_VST1d8Qwb_fixed: 2657 case ARM_VST1d16Qwb_fixed: 2658 case ARM_VST1d32Qwb_fixed: 2659 case ARM_VST1d64Qwb_fixed: 2660 case ARM_VST1d8Qwb_register: 2661 case ARM_VST1d16Qwb_register: 2662 case ARM_VST1d32Qwb_register: 2663 case ARM_VST1d64Qwb_register: 2664 case ARM_VST2d8wb_fixed: 2665 case ARM_VST2d16wb_fixed: 2666 case ARM_VST2d32wb_fixed: 2667 case ARM_VST2d8wb_register: 2668 case ARM_VST2d16wb_register: 2669 case ARM_VST2d32wb_register: 2670 case ARM_VST2q8wb_fixed: 2671 case ARM_VST2q16wb_fixed: 2672 case ARM_VST2q32wb_fixed: 2673 case ARM_VST2q8wb_register: 2674 case ARM_VST2q16wb_register: 2675 case ARM_VST2q32wb_register: 2676 case ARM_VST2b8wb_fixed: 2677 case ARM_VST2b16wb_fixed: 2678 case ARM_VST2b32wb_fixed: 2679 case ARM_VST2b8wb_register: 2680 case ARM_VST2b16wb_register: 2681 case ARM_VST2b32wb_register: 2682 if (Rm == 0xF) 2683 return MCDisassembler_Fail; 2684 MCOperand_CreateImm0(Inst, 0); 2685 break; 2686 case ARM_VST3d8_UPD: 2687 case ARM_VST3d16_UPD: 2688 case ARM_VST3d32_UPD: 2689 case ARM_VST3q8_UPD: 2690 case ARM_VST3q16_UPD: 2691 case ARM_VST3q32_UPD: 2692 case ARM_VST4d8_UPD: 2693 case ARM_VST4d16_UPD: 2694 case ARM_VST4d32_UPD: 2695 case ARM_VST4q8_UPD: 2696 case ARM_VST4q16_UPD: 2697 case ARM_VST4q32_UPD: 2698 if (!Check(&S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2699 return MCDisassembler_Fail; 2700 break; 2701 default: 2702 break; 2703 } 2704 2705 // AddrMode6 Base (register+alignment) 2706 if (!Check(&S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2707 return MCDisassembler_Fail; 2708 2709 // AddrMode6 Offset (register) 2710 switch (MCInst_getOpcode(Inst)) { 2711 default: 2712 if (Rm == 0xD) 2713 MCOperand_CreateReg0(Inst, 0); 2714 else if (Rm != 0xF) { 2715 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2716 return MCDisassembler_Fail; 2717 } 2718 break; 2719 case ARM_VST1d8wb_fixed: 2720 case ARM_VST1d16wb_fixed: 2721 case ARM_VST1d32wb_fixed: 2722 case ARM_VST1d64wb_fixed: 2723 case ARM_VST1q8wb_fixed: 2724 case ARM_VST1q16wb_fixed: 2725 case ARM_VST1q32wb_fixed: 2726 case ARM_VST1q64wb_fixed: 2727 case ARM_VST1d8Twb_fixed: 2728 case ARM_VST1d16Twb_fixed: 2729 case ARM_VST1d32Twb_fixed: 2730 case ARM_VST1d64Twb_fixed: 2731 case ARM_VST1d8Qwb_fixed: 2732 case ARM_VST1d16Qwb_fixed: 2733 case ARM_VST1d32Qwb_fixed: 2734 case ARM_VST1d64Qwb_fixed: 2735 case ARM_VST2d8wb_fixed: 2736 case ARM_VST2d16wb_fixed: 2737 case ARM_VST2d32wb_fixed: 2738 case ARM_VST2q8wb_fixed: 2739 case ARM_VST2q16wb_fixed: 2740 case ARM_VST2q32wb_fixed: 2741 case ARM_VST2b8wb_fixed: 2742 case ARM_VST2b16wb_fixed: 2743 case ARM_VST2b32wb_fixed: 2744 break; 2745 } 2746 2747 2748 // First input register 2749 switch (MCInst_getOpcode(Inst)) { 2750 case ARM_VST1q16: 2751 case ARM_VST1q32: 2752 case ARM_VST1q64: 2753 case ARM_VST1q8: 2754 case ARM_VST1q16wb_fixed: 2755 case ARM_VST1q16wb_register: 2756 case ARM_VST1q32wb_fixed: 2757 case ARM_VST1q32wb_register: 2758 case ARM_VST1q64wb_fixed: 2759 case ARM_VST1q64wb_register: 2760 case ARM_VST1q8wb_fixed: 2761 case ARM_VST1q8wb_register: 2762 case ARM_VST2d16: 2763 case ARM_VST2d32: 2764 case ARM_VST2d8: 2765 case ARM_VST2d16wb_fixed: 2766 case ARM_VST2d16wb_register: 2767 case ARM_VST2d32wb_fixed: 2768 case ARM_VST2d32wb_register: 2769 case ARM_VST2d8wb_fixed: 2770 case ARM_VST2d8wb_register: 2771 if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2772 return MCDisassembler_Fail; 2773 break; 2774 case ARM_VST2b16: 2775 case ARM_VST2b32: 2776 case ARM_VST2b8: 2777 case ARM_VST2b16wb_fixed: 2778 case ARM_VST2b16wb_register: 2779 case ARM_VST2b32wb_fixed: 2780 case ARM_VST2b32wb_register: 2781 case ARM_VST2b8wb_fixed: 2782 case ARM_VST2b8wb_register: 2783 if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2784 return MCDisassembler_Fail; 2785 break; 2786 default: 2787 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2788 return MCDisassembler_Fail; 2789 } 2790 2791 // Second input register 2792 switch (MCInst_getOpcode(Inst)) { 2793 case ARM_VST3d8: 2794 case ARM_VST3d16: 2795 case ARM_VST3d32: 2796 case ARM_VST3d8_UPD: 2797 case ARM_VST3d16_UPD: 2798 case ARM_VST3d32_UPD: 2799 case ARM_VST4d8: 2800 case ARM_VST4d16: 2801 case ARM_VST4d32: 2802 case ARM_VST4d8_UPD: 2803 case ARM_VST4d16_UPD: 2804 case ARM_VST4d32_UPD: 2805 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2806 return MCDisassembler_Fail; 2807 break; 2808 case ARM_VST3q8: 2809 case ARM_VST3q16: 2810 case ARM_VST3q32: 2811 case ARM_VST3q8_UPD: 2812 case ARM_VST3q16_UPD: 2813 case ARM_VST3q32_UPD: 2814 case ARM_VST4q8: 2815 case ARM_VST4q16: 2816 case ARM_VST4q32: 2817 case ARM_VST4q8_UPD: 2818 case ARM_VST4q16_UPD: 2819 case ARM_VST4q32_UPD: 2820 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2821 return MCDisassembler_Fail; 2822 break; 2823 default: 2824 break; 2825 } 2826 2827 // Third input register 2828 switch (MCInst_getOpcode(Inst)) { 2829 case ARM_VST3d8: 2830 case ARM_VST3d16: 2831 case ARM_VST3d32: 2832 case ARM_VST3d8_UPD: 2833 case ARM_VST3d16_UPD: 2834 case ARM_VST3d32_UPD: 2835 case ARM_VST4d8: 2836 case ARM_VST4d16: 2837 case ARM_VST4d32: 2838 case ARM_VST4d8_UPD: 2839 case ARM_VST4d16_UPD: 2840 case ARM_VST4d32_UPD: 2841 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2842 return MCDisassembler_Fail; 2843 break; 2844 case ARM_VST3q8: 2845 case ARM_VST3q16: 2846 case ARM_VST3q32: 2847 case ARM_VST3q8_UPD: 2848 case ARM_VST3q16_UPD: 2849 case ARM_VST3q32_UPD: 2850 case ARM_VST4q8: 2851 case ARM_VST4q16: 2852 case ARM_VST4q32: 2853 case ARM_VST4q8_UPD: 2854 case ARM_VST4q16_UPD: 2855 case ARM_VST4q32_UPD: 2856 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2857 return MCDisassembler_Fail; 2858 break; 2859 default: 2860 break; 2861 } 2862 2863 // Fourth input register 2864 switch (MCInst_getOpcode(Inst)) { 2865 case ARM_VST4d8: 2866 case ARM_VST4d16: 2867 case ARM_VST4d32: 2868 case ARM_VST4d8_UPD: 2869 case ARM_VST4d16_UPD: 2870 case ARM_VST4d32_UPD: 2871 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2872 return MCDisassembler_Fail; 2873 break; 2874 case ARM_VST4q8: 2875 case ARM_VST4q16: 2876 case ARM_VST4q32: 2877 case ARM_VST4q8_UPD: 2878 case ARM_VST4q16_UPD: 2879 case ARM_VST4q32_UPD: 2880 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2881 return MCDisassembler_Fail; 2882 break; 2883 default: 2884 break; 2885 } 2886 2887 return S; 2888 } 2889 2890 static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Insn, 2891 uint64_t Address, const void *Decoder) 2892 { 2893 DecodeStatus S = MCDisassembler_Success; 2894 unsigned Rn, Rm, align, size; 2895 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); 2896 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; 2897 Rn = fieldFromInstruction_4(Insn, 16, 4); 2898 Rm = fieldFromInstruction_4(Insn, 0, 4); 2899 align = fieldFromInstruction_4(Insn, 4, 1); 2900 size = fieldFromInstruction_4(Insn, 6, 2); 2901 2902 if (size == 0 && align == 1) 2903 return MCDisassembler_Fail; 2904 align *= (1 << size); 2905 2906 switch (MCInst_getOpcode(Inst)) { 2907 case ARM_VLD1DUPq16: case ARM_VLD1DUPq32: case ARM_VLD1DUPq8: 2908 case ARM_VLD1DUPq16wb_fixed: case ARM_VLD1DUPq16wb_register: 2909 case ARM_VLD1DUPq32wb_fixed: case ARM_VLD1DUPq32wb_register: 2910 case ARM_VLD1DUPq8wb_fixed: case ARM_VLD1DUPq8wb_register: 2911 if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2912 return MCDisassembler_Fail; 2913 break; 2914 default: 2915 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2916 return MCDisassembler_Fail; 2917 break; 2918 } 2919 if (Rm != 0xF) { 2920 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2921 return MCDisassembler_Fail; 2922 } 2923 2924 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2925 return MCDisassembler_Fail; 2926 MCOperand_CreateImm0(Inst, align); 2927 2928 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2929 // variant encodes Rm == 0xf. Anything else is a register offset post- 2930 // increment and we need to add the register operand to the instruction. 2931 if (Rm != 0xD && Rm != 0xF && 2932 !Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2933 return MCDisassembler_Fail; 2934 2935 return S; 2936 } 2937 2938 static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Insn, 2939 uint64_t Address, const void *Decoder) 2940 { 2941 DecodeStatus S = MCDisassembler_Success; 2942 unsigned Rn, Rm, align, size; 2943 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); 2944 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; 2945 Rn = fieldFromInstruction_4(Insn, 16, 4); 2946 Rm = fieldFromInstruction_4(Insn, 0, 4); 2947 align = fieldFromInstruction_4(Insn, 4, 1); 2948 size = 1 << fieldFromInstruction_4(Insn, 6, 2); 2949 align *= 2*size; 2950 2951 switch (MCInst_getOpcode(Inst)) { 2952 case ARM_VLD2DUPd16: case ARM_VLD2DUPd32: case ARM_VLD2DUPd8: 2953 case ARM_VLD2DUPd16wb_fixed: case ARM_VLD2DUPd16wb_register: 2954 case ARM_VLD2DUPd32wb_fixed: case ARM_VLD2DUPd32wb_register: 2955 case ARM_VLD2DUPd8wb_fixed: case ARM_VLD2DUPd8wb_register: 2956 if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2957 return MCDisassembler_Fail; 2958 break; 2959 case ARM_VLD2DUPd16x2: case ARM_VLD2DUPd32x2: case ARM_VLD2DUPd8x2: 2960 case ARM_VLD2DUPd16x2wb_fixed: case ARM_VLD2DUPd16x2wb_register: 2961 case ARM_VLD2DUPd32x2wb_fixed: case ARM_VLD2DUPd32x2wb_register: 2962 case ARM_VLD2DUPd8x2wb_fixed: case ARM_VLD2DUPd8x2wb_register: 2963 if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2964 return MCDisassembler_Fail; 2965 break; 2966 default: 2967 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2968 return MCDisassembler_Fail; 2969 break; 2970 } 2971 2972 if (Rm != 0xF) 2973 MCOperand_CreateImm0(Inst, 0); 2974 2975 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2976 return MCDisassembler_Fail; 2977 MCOperand_CreateImm0(Inst, align); 2978 2979 if (Rm != 0xD && Rm != 0xF) { 2980 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2981 return MCDisassembler_Fail; 2982 } 2983 2984 return S; 2985 } 2986 2987 static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Insn, 2988 uint64_t Address, const void *Decoder) 2989 { 2990 DecodeStatus S = MCDisassembler_Success; 2991 unsigned Rn, Rm, inc; 2992 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); 2993 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; 2994 Rn = fieldFromInstruction_4(Insn, 16, 4); 2995 Rm = fieldFromInstruction_4(Insn, 0, 4); 2996 inc = fieldFromInstruction_4(Insn, 5, 1) + 1; 2997 2998 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2999 return MCDisassembler_Fail; 3000 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3001 return MCDisassembler_Fail; 3002 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3003 return MCDisassembler_Fail; 3004 if (Rm != 0xF) { 3005 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3006 return MCDisassembler_Fail; 3007 } 3008 3009 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3010 return MCDisassembler_Fail; 3011 MCOperand_CreateImm0(Inst, 0); 3012 3013 if (Rm == 0xD) 3014 MCOperand_CreateReg0(Inst, 0); 3015 else if (Rm != 0xF) { 3016 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3017 return MCDisassembler_Fail; 3018 } 3019 3020 return S; 3021 } 3022 3023 static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Insn, 3024 uint64_t Address, const void *Decoder) 3025 { 3026 DecodeStatus S = MCDisassembler_Success; 3027 unsigned Rn, Rm, size, inc, align; 3028 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); 3029 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; 3030 Rn = fieldFromInstruction_4(Insn, 16, 4); 3031 Rm = fieldFromInstruction_4(Insn, 0, 4); 3032 size = fieldFromInstruction_4(Insn, 6, 2); 3033 inc = fieldFromInstruction_4(Insn, 5, 1) + 1; 3034 align = fieldFromInstruction_4(Insn, 4, 1); 3035 3036 if (size == 0x3) { 3037 if (align == 0) 3038 return MCDisassembler_Fail; 3039 align = 16; 3040 } else { 3041 if (size == 2) { 3042 align *= 8; 3043 } else { 3044 size = 1 << size; 3045 align *= 4 * size; 3046 } 3047 } 3048 3049 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3050 return MCDisassembler_Fail; 3051 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3052 return MCDisassembler_Fail; 3053 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3054 return MCDisassembler_Fail; 3055 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3056 return MCDisassembler_Fail; 3057 if (Rm != 0xF) { 3058 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3059 return MCDisassembler_Fail; 3060 } 3061 3062 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3063 return MCDisassembler_Fail; 3064 MCOperand_CreateImm0(Inst, align); 3065 3066 if (Rm == 0xD) 3067 MCOperand_CreateReg0(Inst, 0); 3068 else if (Rm != 0xF) { 3069 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3070 return MCDisassembler_Fail; 3071 } 3072 3073 return S; 3074 } 3075 3076 static DecodeStatus DecodeNEONModImmInstruction(MCInst *Inst, unsigned Insn, 3077 uint64_t Address, const void *Decoder) 3078 { 3079 DecodeStatus S = MCDisassembler_Success; 3080 unsigned imm, Q; 3081 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); 3082 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; 3083 imm = fieldFromInstruction_4(Insn, 0, 4); 3084 imm |= fieldFromInstruction_4(Insn, 16, 3) << 4; 3085 imm |= fieldFromInstruction_4(Insn, 24, 1) << 7; 3086 imm |= fieldFromInstruction_4(Insn, 8, 4) << 8; 3087 imm |= fieldFromInstruction_4(Insn, 5, 1) << 12; 3088 Q = fieldFromInstruction_4(Insn, 6, 1); 3089 3090 if (Q) { 3091 if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3092 return MCDisassembler_Fail; 3093 } else { 3094 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3095 return MCDisassembler_Fail; 3096 } 3097 3098 MCOperand_CreateImm0(Inst, imm); 3099 3100 switch (MCInst_getOpcode(Inst)) { 3101 case ARM_VORRiv4i16: 3102 case ARM_VORRiv2i32: 3103 case ARM_VBICiv4i16: 3104 case ARM_VBICiv2i32: 3105 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3106 return MCDisassembler_Fail; 3107 break; 3108 case ARM_VORRiv8i16: 3109 case ARM_VORRiv4i32: 3110 case ARM_VBICiv8i16: 3111 case ARM_VBICiv4i32: 3112 if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3113 return MCDisassembler_Fail; 3114 break; 3115 default: 3116 break; 3117 } 3118 3119 return S; 3120 } 3121 3122 static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Insn, 3123 uint64_t Address, const void *Decoder) 3124 { 3125 DecodeStatus S = MCDisassembler_Success; 3126 unsigned Rm, size; 3127 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); 3128 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; 3129 Rm = fieldFromInstruction_4(Insn, 0, 4); 3130 Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4; 3131 size = fieldFromInstruction_4(Insn, 18, 2); 3132 3133 if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3134 return MCDisassembler_Fail; 3135 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3136 return MCDisassembler_Fail; 3137 MCOperand_CreateImm0(Inst, 8 << size); 3138 3139 return S; 3140 } 3141 3142 static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val, 3143 uint64_t Address, const void *Decoder) 3144 { 3145 MCOperand_CreateImm0(Inst, 8 - Val); 3146 return MCDisassembler_Success; 3147 } 3148 3149 static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val, 3150 uint64_t Address, const void *Decoder) 3151 { 3152 MCOperand_CreateImm0(Inst, 16 - Val); 3153 return MCDisassembler_Success; 3154 } 3155 3156 static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val, 3157 uint64_t Address, const void *Decoder) 3158 { 3159 MCOperand_CreateImm0(Inst, 32 - Val); 3160 return MCDisassembler_Success; 3161 } 3162 3163 static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val, 3164 uint64_t Address, const void *Decoder) 3165 { 3166 MCOperand_CreateImm0(Inst, 64 - Val); 3167 return MCDisassembler_Success; 3168 } 3169 3170 static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn, 3171 uint64_t Address, const void *Decoder) 3172 { 3173 DecodeStatus S = MCDisassembler_Success; 3174 unsigned Rn, Rm, op; 3175 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); 3176 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; 3177 Rn = fieldFromInstruction_4(Insn, 16, 4); 3178 Rn |= fieldFromInstruction_4(Insn, 7, 1) << 4; 3179 Rm = fieldFromInstruction_4(Insn, 0, 4); 3180 Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4; 3181 op = fieldFromInstruction_4(Insn, 6, 1); 3182 3183 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3184 return MCDisassembler_Fail; 3185 if (op) { 3186 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3187 return MCDisassembler_Fail; // Writeback 3188 } 3189 3190 switch (MCInst_getOpcode(Inst)) { 3191 case ARM_VTBL2: 3192 case ARM_VTBX2: 3193 if (!Check(&S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3194 return MCDisassembler_Fail; 3195 break; 3196 default: 3197 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3198 return MCDisassembler_Fail; 3199 } 3200 3201 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3202 return MCDisassembler_Fail; 3203 3204 return S; 3205 } 3206 3207 static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn, 3208 uint64_t Address, const void *Decoder) 3209 { 3210 DecodeStatus S = MCDisassembler_Success; 3211 3212 unsigned dst = fieldFromInstruction_2(Insn, 8, 3); 3213 unsigned imm = fieldFromInstruction_2(Insn, 0, 8); 3214 3215 if (!Check(&S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3216 return MCDisassembler_Fail; 3217 3218 switch(MCInst_getOpcode(Inst)) { 3219 default: 3220 return MCDisassembler_Fail; 3221 case ARM_tADR: 3222 break; // tADR does not explicitly represent the PC as an operand. 3223 case ARM_tADDrSPi: 3224 MCOperand_CreateReg0(Inst, ARM_SP); 3225 break; 3226 } 3227 3228 MCOperand_CreateImm0(Inst, imm); 3229 return S; 3230 } 3231 3232 static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val, 3233 uint64_t Address, const void *Decoder) 3234 { 3235 MCOperand_CreateImm0(Inst, SignExtend32(Val << 1, 12)); 3236 return MCDisassembler_Success; 3237 } 3238 3239 static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val, 3240 uint64_t Address, const void *Decoder) 3241 { 3242 MCOperand_CreateImm0(Inst, SignExtend32(Val, 21)); 3243 return MCDisassembler_Success; 3244 } 3245 3246 static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val, 3247 uint64_t Address, const void *Decoder) 3248 { 3249 MCOperand_CreateImm0(Inst, Val << 1); 3250 return MCDisassembler_Success; 3251 } 3252 3253 static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val, 3254 uint64_t Address, const void *Decoder) 3255 { 3256 DecodeStatus S = MCDisassembler_Success; 3257 3258 unsigned Rn = fieldFromInstruction_4(Val, 0, 3); 3259 unsigned Rm = fieldFromInstruction_4(Val, 3, 3); 3260 3261 if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3262 return MCDisassembler_Fail; 3263 if (!Check(&S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3264 return MCDisassembler_Fail; 3265 3266 return S; 3267 } 3268 3269 static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val, 3270 uint64_t Address, const void *Decoder) 3271 { 3272 DecodeStatus S = MCDisassembler_Success; 3273 3274 unsigned Rn = fieldFromInstruction_4(Val, 0, 3); 3275 unsigned imm = fieldFromInstruction_4(Val, 3, 5); 3276 3277 if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3278 return MCDisassembler_Fail; 3279 MCOperand_CreateImm0(Inst, imm); 3280 3281 return S; 3282 } 3283 3284 static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val, 3285 uint64_t Address, const void *Decoder) 3286 { 3287 unsigned imm = Val << 2; 3288 3289 MCOperand_CreateImm0(Inst, imm); 3290 //tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3291 3292 return MCDisassembler_Success; 3293 } 3294 3295 static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val, 3296 uint64_t Address, const void *Decoder) 3297 { 3298 MCOperand_CreateReg0(Inst, ARM_SP); 3299 MCOperand_CreateImm0(Inst, Val); 3300 3301 return MCDisassembler_Success; 3302 } 3303 3304 static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val, 3305 uint64_t Address, const void *Decoder) 3306 { 3307 DecodeStatus S = MCDisassembler_Success; 3308 3309 unsigned Rn = fieldFromInstruction_4(Val, 6, 4); 3310 unsigned Rm = fieldFromInstruction_4(Val, 2, 4); 3311 unsigned imm = fieldFromInstruction_4(Val, 0, 2); 3312 3313 // Thumb stores cannot use PC as dest register. 3314 switch (MCInst_getOpcode(Inst)) { 3315 case ARM_t2STRHs: 3316 case ARM_t2STRBs: 3317 case ARM_t2STRs: 3318 if (Rn == 15) 3319 return MCDisassembler_Fail; 3320 default: 3321 break; 3322 } 3323 3324 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3325 return MCDisassembler_Fail; 3326 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3327 return MCDisassembler_Fail; 3328 MCOperand_CreateImm0(Inst, imm); 3329 3330 return S; 3331 } 3332 3333 static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Insn, 3334 uint64_t Address, const void *Decoder) 3335 { 3336 DecodeStatus S = MCDisassembler_Success; 3337 unsigned addrmode; 3338 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); 3339 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 3340 3341 if (Rn == 15) { 3342 switch (MCInst_getOpcode(Inst)) { 3343 case ARM_t2LDRBs: 3344 MCInst_setOpcode(Inst, ARM_t2LDRBpci); 3345 break; 3346 case ARM_t2LDRHs: 3347 MCInst_setOpcode(Inst, ARM_t2LDRHpci); 3348 break; 3349 case ARM_t2LDRSHs: 3350 MCInst_setOpcode(Inst, ARM_t2LDRSHpci); 3351 break; 3352 case ARM_t2LDRSBs: 3353 MCInst_setOpcode(Inst, ARM_t2LDRSBpci); 3354 break; 3355 case ARM_t2LDRs: 3356 MCInst_setOpcode(Inst, ARM_t2LDRpci); 3357 break; 3358 case ARM_t2PLDs: 3359 MCInst_setOpcode(Inst, ARM_t2PLDpci); 3360 break; 3361 case ARM_t2PLIs: 3362 MCInst_setOpcode(Inst, ARM_t2PLIpci); 3363 break; 3364 default: 3365 return MCDisassembler_Fail; 3366 } 3367 3368 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3369 } 3370 3371 if (Rt == 15) { 3372 switch (MCInst_getOpcode(Inst)) { 3373 case ARM_t2LDRSHs: 3374 return MCDisassembler_Fail; 3375 case ARM_t2LDRHs: 3376 // FIXME: this instruction is only available with MP extensions, 3377 // this should be checked first but we don't have access to the 3378 // feature bits here. 3379 MCInst_setOpcode(Inst, ARM_t2PLDWs); 3380 break; 3381 default: 3382 break; 3383 } 3384 } 3385 3386 switch (MCInst_getOpcode(Inst)) { 3387 case ARM_t2PLDs: 3388 case ARM_t2PLDWs: 3389 case ARM_t2PLIs: 3390 break; 3391 default: 3392 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3393 return MCDisassembler_Fail; 3394 } 3395 3396 addrmode = fieldFromInstruction_4(Insn, 4, 2); 3397 addrmode |= fieldFromInstruction_4(Insn, 0, 4) << 2; 3398 addrmode |= fieldFromInstruction_4(Insn, 16, 4) << 6; 3399 if (!Check(&S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3400 return MCDisassembler_Fail; 3401 3402 return S; 3403 } 3404 3405 static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn, 3406 uint64_t Address, const void* Decoder) 3407 { 3408 DecodeStatus S = MCDisassembler_Success; 3409 3410 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 3411 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); 3412 unsigned U = fieldFromInstruction_4(Insn, 9, 1); 3413 unsigned imm = fieldFromInstruction_4(Insn, 0, 8); 3414 imm |= (U << 8); 3415 imm |= (Rn << 9); 3416 3417 if (Rn == 15) { 3418 switch (MCInst_getOpcode(Inst)) { 3419 case ARM_t2LDRi8: 3420 MCInst_setOpcode(Inst, ARM_t2LDRpci); 3421 break; 3422 case ARM_t2LDRBi8: 3423 MCInst_setOpcode(Inst, ARM_t2LDRBpci); 3424 break; 3425 case ARM_t2LDRSBi8: 3426 MCInst_setOpcode(Inst, ARM_t2LDRSBpci); 3427 break; 3428 case ARM_t2LDRHi8: 3429 MCInst_setOpcode(Inst, ARM_t2LDRHpci); 3430 break; 3431 case ARM_t2LDRSHi8: 3432 MCInst_setOpcode(Inst, ARM_t2LDRSHpci); 3433 break; 3434 case ARM_t2PLDi8: 3435 MCInst_setOpcode(Inst, ARM_t2PLDpci); 3436 break; 3437 case ARM_t2PLIi8: 3438 MCInst_setOpcode(Inst, ARM_t2PLIpci); 3439 break; 3440 default: 3441 return MCDisassembler_Fail; 3442 } 3443 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3444 } 3445 3446 if (Rt == 15) { 3447 switch (MCInst_getOpcode(Inst)) { 3448 case ARM_t2LDRSHi8: 3449 return MCDisassembler_Fail; 3450 default: 3451 break; 3452 } 3453 } 3454 3455 switch (MCInst_getOpcode(Inst)) { 3456 case ARM_t2PLDi8: 3457 case ARM_t2PLIi8: 3458 case ARM_t2PLDWi8: 3459 break; 3460 default: 3461 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3462 return MCDisassembler_Fail; 3463 } 3464 3465 if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3466 return MCDisassembler_Fail; 3467 return S; 3468 } 3469 3470 static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn, 3471 uint64_t Address, const void* Decoder) 3472 { 3473 DecodeStatus S = MCDisassembler_Success; 3474 3475 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 3476 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); 3477 unsigned imm = fieldFromInstruction_4(Insn, 0, 12); 3478 imm |= (Rn << 13); 3479 3480 if (Rn == 15) { 3481 switch (MCInst_getOpcode(Inst)) { 3482 case ARM_t2LDRi12: 3483 MCInst_setOpcode(Inst, ARM_t2LDRpci); 3484 break; 3485 case ARM_t2LDRHi12: 3486 MCInst_setOpcode(Inst, ARM_t2LDRHpci); 3487 break; 3488 case ARM_t2LDRSHi12: 3489 MCInst_setOpcode(Inst, ARM_t2LDRSHpci); 3490 break; 3491 case ARM_t2LDRBi12: 3492 MCInst_setOpcode(Inst, ARM_t2LDRBpci); 3493 break; 3494 case ARM_t2LDRSBi12: 3495 MCInst_setOpcode(Inst, ARM_t2LDRSBpci); 3496 break; 3497 case ARM_t2PLDi12: 3498 MCInst_setOpcode(Inst, ARM_t2PLDpci); 3499 break; 3500 case ARM_t2PLIi12: 3501 MCInst_setOpcode(Inst, ARM_t2PLIpci); 3502 break; 3503 default: 3504 return MCDisassembler_Fail; 3505 } 3506 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3507 } 3508 3509 if (Rt == 15) { 3510 switch (MCInst_getOpcode(Inst)) { 3511 case ARM_t2LDRSHi12: 3512 return MCDisassembler_Fail; 3513 case ARM_t2LDRHi12: 3514 MCInst_setOpcode(Inst, ARM_t2PLDi12); 3515 break; 3516 default: 3517 break; 3518 } 3519 } 3520 3521 switch (MCInst_getOpcode(Inst)) { 3522 case ARM_t2PLDi12: 3523 case ARM_t2PLDWi12: 3524 case ARM_t2PLIi12: 3525 break; 3526 default: 3527 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3528 return MCDisassembler_Fail; 3529 } 3530 3531 if (!Check(&S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3532 return MCDisassembler_Fail; 3533 return S; 3534 } 3535 3536 static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn, 3537 uint64_t Address, const void* Decoder) 3538 { 3539 DecodeStatus S = MCDisassembler_Success; 3540 3541 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 3542 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); 3543 unsigned imm = fieldFromInstruction_4(Insn, 0, 8); 3544 imm |= (Rn << 9); 3545 3546 if (Rn == 15) { 3547 switch (MCInst_getOpcode(Inst)) { 3548 case ARM_t2LDRT: 3549 MCInst_setOpcode(Inst, ARM_t2LDRpci); 3550 break; 3551 case ARM_t2LDRBT: 3552 MCInst_setOpcode(Inst, ARM_t2LDRBpci); 3553 break; 3554 case ARM_t2LDRHT: 3555 MCInst_setOpcode(Inst, ARM_t2LDRHpci); 3556 break; 3557 case ARM_t2LDRSBT: 3558 MCInst_setOpcode(Inst, ARM_t2LDRSBpci); 3559 break; 3560 case ARM_t2LDRSHT: 3561 MCInst_setOpcode(Inst, ARM_t2LDRSHpci); 3562 break; 3563 default: 3564 return MCDisassembler_Fail; 3565 } 3566 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3567 } 3568 3569 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3570 return MCDisassembler_Fail; 3571 if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3572 return MCDisassembler_Fail; 3573 return S; 3574 } 3575 3576 static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn, 3577 uint64_t Address, const void* Decoder) 3578 { 3579 DecodeStatus S = MCDisassembler_Success; 3580 3581 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); 3582 unsigned U = fieldFromInstruction_4(Insn, 23, 1); 3583 int imm = fieldFromInstruction_4(Insn, 0, 12); 3584 3585 if (Rt == 15) { 3586 switch (MCInst_getOpcode(Inst)) { 3587 case ARM_t2LDRBpci: 3588 case ARM_t2LDRHpci: 3589 MCInst_setOpcode(Inst, ARM_t2PLDpci); 3590 break; 3591 case ARM_t2LDRSBpci: 3592 MCInst_setOpcode(Inst, ARM_t2PLIpci); 3593 break; 3594 case ARM_t2LDRSHpci: 3595 return MCDisassembler_Fail; 3596 default: 3597 break; 3598 } 3599 } 3600 3601 switch(MCInst_getOpcode(Inst)) { 3602 case ARM_t2PLDpci: 3603 case ARM_t2PLIpci: 3604 break; 3605 default: 3606 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3607 return MCDisassembler_Fail; 3608 } 3609 3610 if (!U) { 3611 // Special case for #-0. 3612 if (imm == 0) 3613 imm = INT32_MIN; 3614 else 3615 imm = -imm; 3616 } 3617 MCOperand_CreateImm0(Inst, imm); 3618 3619 return S; 3620 } 3621 3622 static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val, 3623 uint64_t Address, const void *Decoder) 3624 { 3625 if (Val == 0) 3626 MCOperand_CreateImm0(Inst, INT32_MIN); 3627 else { 3628 int imm = Val & 0xFF; 3629 3630 if (!(Val & 0x100)) imm *= -1; 3631 MCOperand_CreateImm0(Inst, imm * 4); 3632 } 3633 3634 return MCDisassembler_Success; 3635 } 3636 3637 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val, 3638 uint64_t Address, const void *Decoder) 3639 { 3640 DecodeStatus S = MCDisassembler_Success; 3641 3642 unsigned Rn = fieldFromInstruction_4(Val, 9, 4); 3643 unsigned imm = fieldFromInstruction_4(Val, 0, 9); 3644 3645 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3646 return MCDisassembler_Fail; 3647 if (!Check(&S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3648 return MCDisassembler_Fail; 3649 3650 return S; 3651 } 3652 3653 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst,unsigned Val, 3654 uint64_t Address, const void *Decoder) 3655 { 3656 DecodeStatus S = MCDisassembler_Success; 3657 3658 unsigned Rn = fieldFromInstruction_4(Val, 8, 4); 3659 unsigned imm = fieldFromInstruction_4(Val, 0, 8); 3660 3661 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3662 return MCDisassembler_Fail; 3663 3664 MCOperand_CreateImm0(Inst, imm); 3665 3666 return S; 3667 } 3668 3669 static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val, 3670 uint64_t Address, const void *Decoder) 3671 { 3672 int imm = Val & 0xFF; 3673 if (Val == 0) 3674 imm = INT32_MIN; 3675 else if (!(Val & 0x100)) 3676 imm *= -1; 3677 MCOperand_CreateImm0(Inst, imm); 3678 3679 return MCDisassembler_Success; 3680 } 3681 3682 static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val, 3683 uint64_t Address, const void *Decoder) 3684 { 3685 DecodeStatus S = MCDisassembler_Success; 3686 3687 unsigned Rn = fieldFromInstruction_4(Val, 9, 4); 3688 unsigned imm = fieldFromInstruction_4(Val, 0, 9); 3689 3690 // Thumb stores cannot use PC as dest register. 3691 switch (MCInst_getOpcode(Inst)) { 3692 case ARM_t2STRT: 3693 case ARM_t2STRBT: 3694 case ARM_t2STRHT: 3695 case ARM_t2STRi8: 3696 case ARM_t2STRHi8: 3697 case ARM_t2STRBi8: 3698 if (Rn == 15) 3699 return MCDisassembler_Fail; 3700 break; 3701 default: 3702 break; 3703 } 3704 3705 // Some instructions always use an additive offset. 3706 switch (MCInst_getOpcode(Inst)) { 3707 case ARM_t2LDRT: 3708 case ARM_t2LDRBT: 3709 case ARM_t2LDRHT: 3710 case ARM_t2LDRSBT: 3711 case ARM_t2LDRSHT: 3712 case ARM_t2STRT: 3713 case ARM_t2STRBT: 3714 case ARM_t2STRHT: 3715 imm |= 0x100; 3716 break; 3717 default: 3718 break; 3719 } 3720 3721 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3722 return MCDisassembler_Fail; 3723 if (!Check(&S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3724 return MCDisassembler_Fail; 3725 3726 return S; 3727 } 3728 3729 static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Insn, 3730 uint64_t Address, const void *Decoder) 3731 { 3732 DecodeStatus S = MCDisassembler_Success; 3733 unsigned load; 3734 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); 3735 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 3736 unsigned addr = fieldFromInstruction_4(Insn, 0, 8); 3737 addr |= fieldFromInstruction_4(Insn, 9, 1) << 8; 3738 addr |= Rn << 9; 3739 load = fieldFromInstruction_4(Insn, 20, 1); 3740 3741 if (Rn == 15) { 3742 switch (MCInst_getOpcode(Inst)) { 3743 case ARM_t2LDR_PRE: 3744 case ARM_t2LDR_POST: 3745 MCInst_setOpcode(Inst, ARM_t2LDRpci); 3746 break; 3747 case ARM_t2LDRB_PRE: 3748 case ARM_t2LDRB_POST: 3749 MCInst_setOpcode(Inst, ARM_t2LDRBpci); 3750 break; 3751 case ARM_t2LDRH_PRE: 3752 case ARM_t2LDRH_POST: 3753 MCInst_setOpcode(Inst, ARM_t2LDRHpci); 3754 break; 3755 case ARM_t2LDRSB_PRE: 3756 case ARM_t2LDRSB_POST: 3757 if (Rt == 15) 3758 MCInst_setOpcode(Inst, ARM_t2PLIpci); 3759 else 3760 MCInst_setOpcode(Inst, ARM_t2LDRSBpci); 3761 break; 3762 case ARM_t2LDRSH_PRE: 3763 case ARM_t2LDRSH_POST: 3764 MCInst_setOpcode(Inst, ARM_t2LDRSHpci); 3765 break; 3766 default: 3767 return MCDisassembler_Fail; 3768 } 3769 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3770 } 3771 3772 if (!load) { 3773 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3774 return MCDisassembler_Fail; 3775 } 3776 3777 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3778 return MCDisassembler_Fail; 3779 3780 if (load) { 3781 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3782 return MCDisassembler_Fail; 3783 } 3784 3785 if (!Check(&S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3786 return MCDisassembler_Fail; 3787 3788 return S; 3789 } 3790 3791 static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val, 3792 uint64_t Address, const void *Decoder) 3793 { 3794 DecodeStatus S = MCDisassembler_Success; 3795 3796 unsigned Rn = fieldFromInstruction_4(Val, 13, 4); 3797 unsigned imm = fieldFromInstruction_4(Val, 0, 12); 3798 3799 // Thumb stores cannot use PC as dest register. 3800 switch (MCInst_getOpcode(Inst)) { 3801 case ARM_t2STRi12: 3802 case ARM_t2STRBi12: 3803 case ARM_t2STRHi12: 3804 if (Rn == 15) 3805 return MCDisassembler_Fail; 3806 default: 3807 break; 3808 } 3809 3810 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3811 return MCDisassembler_Fail; 3812 MCOperand_CreateImm0(Inst, imm); 3813 3814 return S; 3815 } 3816 3817 static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Insn, 3818 uint64_t Address, const void *Decoder) 3819 { 3820 unsigned imm = fieldFromInstruction_2(Insn, 0, 7); 3821 3822 MCOperand_CreateReg0(Inst, ARM_SP); 3823 MCOperand_CreateReg0(Inst, ARM_SP); 3824 MCOperand_CreateImm0(Inst, imm); 3825 3826 return MCDisassembler_Success; 3827 } 3828 3829 static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn, 3830 uint64_t Address, const void *Decoder) 3831 { 3832 DecodeStatus S = MCDisassembler_Success; 3833 3834 if (MCInst_getOpcode(Inst) == ARM_tADDrSP) { 3835 unsigned Rdm = fieldFromInstruction_2(Insn, 0, 3); 3836 Rdm |= fieldFromInstruction_2(Insn, 7, 1) << 3; 3837 3838 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3839 return MCDisassembler_Fail; 3840 MCOperand_CreateReg0(Inst, ARM_SP); 3841 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3842 return MCDisassembler_Fail; 3843 } else if (MCInst_getOpcode(Inst) == ARM_tADDspr) { 3844 unsigned Rm = fieldFromInstruction_2(Insn, 3, 4); 3845 3846 MCOperand_CreateReg0(Inst, ARM_SP); 3847 MCOperand_CreateReg0(Inst, ARM_SP); 3848 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3849 return MCDisassembler_Fail; 3850 } 3851 3852 return S; 3853 } 3854 3855 static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn, 3856 uint64_t Address, const void *Decoder) 3857 { 3858 unsigned imod = fieldFromInstruction_2(Insn, 4, 1) | 0x2; 3859 unsigned flags = fieldFromInstruction_2(Insn, 0, 3); 3860 3861 MCOperand_CreateImm0(Inst, imod); 3862 MCOperand_CreateImm0(Inst, flags); 3863 3864 return MCDisassembler_Success; 3865 } 3866 3867 static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn, 3868 uint64_t Address, const void *Decoder) 3869 { 3870 DecodeStatus S = MCDisassembler_Success; 3871 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); 3872 unsigned add = fieldFromInstruction_4(Insn, 4, 1); 3873 3874 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3875 return MCDisassembler_Fail; 3876 MCOperand_CreateImm0(Inst, add); 3877 3878 return S; 3879 } 3880 3881 static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Val, 3882 uint64_t Address, const void *Decoder) 3883 { 3884 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3885 // Note only one trailing zero not two. Also the J1 and J2 values are from 3886 // the encoded instruction. So here change to I1 and I2 values via: 3887 // I1 = NOT(J1 EOR S); 3888 // I2 = NOT(J2 EOR S); 3889 // and build the imm32 with two trailing zeros as documented: 3890 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3891 unsigned S = (Val >> 23) & 1; 3892 unsigned J1 = (Val >> 22) & 1; 3893 unsigned J2 = (Val >> 21) & 1; 3894 unsigned I1 = !(J1 ^ S); 3895 unsigned I2 = !(J2 ^ S); 3896 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3897 int imm32 = SignExtend32(tmp << 1, 25); 3898 3899 MCOperand_CreateImm0(Inst, imm32); 3900 return MCDisassembler_Success; 3901 } 3902 3903 static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Val, 3904 uint64_t Address, const void *Decoder) 3905 { 3906 if (Val == 0xA || Val == 0xB) 3907 return MCDisassembler_Fail; 3908 3909 MCOperand_CreateImm0(Inst, Val); 3910 return MCDisassembler_Success; 3911 } 3912 3913 static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Insn, 3914 uint64_t Address, const void *Decoder) 3915 { 3916 DecodeStatus S = MCDisassembler_Success; 3917 3918 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 3919 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); 3920 3921 if (Rn == ARM_SP) S = MCDisassembler_SoftFail; 3922 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3923 return MCDisassembler_Fail; 3924 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3925 return MCDisassembler_Fail; 3926 return S; 3927 } 3928 3929 static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Insn, 3930 uint64_t Address, const void *Decoder) 3931 { 3932 DecodeStatus S = MCDisassembler_Success; 3933 unsigned brtarget; 3934 unsigned pred = fieldFromInstruction_4(Insn, 22, 4); 3935 if (pred == 0xE || pred == 0xF) { 3936 unsigned imm; 3937 unsigned opc = fieldFromInstruction_4(Insn, 4, 28); 3938 switch (opc) { 3939 default: 3940 return MCDisassembler_Fail; 3941 case 0xf3bf8f4: 3942 MCInst_setOpcode(Inst, ARM_t2DSB); 3943 break; 3944 case 0xf3bf8f5: 3945 MCInst_setOpcode(Inst, ARM_t2DMB); 3946 break; 3947 case 0xf3bf8f6: 3948 MCInst_setOpcode(Inst, ARM_t2ISB); 3949 break; 3950 } 3951 3952 imm = fieldFromInstruction_4(Insn, 0, 4); 3953 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3954 } 3955 3956 brtarget = fieldFromInstruction_4(Insn, 0, 11) << 1; 3957 brtarget |= fieldFromInstruction_4(Insn, 11, 1) << 19; 3958 brtarget |= fieldFromInstruction_4(Insn, 13, 1) << 18; 3959 brtarget |= fieldFromInstruction_4(Insn, 16, 6) << 12; 3960 brtarget |= fieldFromInstruction_4(Insn, 26, 1) << 20; 3961 3962 if (!Check(&S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3963 return MCDisassembler_Fail; 3964 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3965 return MCDisassembler_Fail; 3966 3967 return S; 3968 } 3969 3970 // Decode a shifted immediate operand. These basically consist 3971 // of an 8-bit value, and a 4-bit directive that specifies either 3972 // a splat operation or a rotation. 3973 static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val, 3974 uint64_t Address, const void *Decoder) 3975 { 3976 unsigned ctrl = fieldFromInstruction_4(Val, 10, 2); 3977 if (ctrl == 0) { 3978 unsigned byte = fieldFromInstruction_4(Val, 8, 2); 3979 unsigned imm = fieldFromInstruction_4(Val, 0, 8); 3980 switch (byte) { 3981 case 0: 3982 MCOperand_CreateImm0(Inst, imm); 3983 break; 3984 case 1: 3985 MCOperand_CreateImm0(Inst, (imm << 16) | imm); 3986 break; 3987 case 2: 3988 MCOperand_CreateImm0(Inst, (imm << 24) | (imm << 8)); 3989 break; 3990 case 3: 3991 MCOperand_CreateImm0(Inst, (imm << 24) | (imm << 16) | (imm << 8) | imm); 3992 break; 3993 } 3994 } else { 3995 unsigned unrot = fieldFromInstruction_4(Val, 0, 7) | 0x80; 3996 unsigned rot = fieldFromInstruction_4(Val, 7, 5); 3997 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3998 MCOperand_CreateImm0(Inst, imm); 3999 } 4000 4001 return MCDisassembler_Success; 4002 } 4003 4004 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst, unsigned Val, 4005 uint64_t Address, const void *Decoder) 4006 { 4007 MCOperand_CreateImm0(Inst, SignExtend32(Val << 1, 9)); 4008 return MCDisassembler_Success; 4009 } 4010 4011 static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val, 4012 uint64_t Address, const void *Decoder) 4013 { 4014 // Val is passed in as S:J1:J2:imm10:imm11 4015 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4016 // the encoded instruction. So here change to I1 and I2 values via: 4017 // I1 = NOT(J1 EOR S); 4018 // I2 = NOT(J2 EOR S); 4019 // and build the imm32 with one trailing zero as documented: 4020 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4021 unsigned S = (Val >> 23) & 1; 4022 unsigned J1 = (Val >> 22) & 1; 4023 unsigned J2 = (Val >> 21) & 1; 4024 unsigned I1 = !(J1 ^ S); 4025 unsigned I2 = !(J2 ^ S); 4026 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4027 int imm32 = SignExtend32(tmp << 1, 25); 4028 4029 MCOperand_CreateImm0(Inst, imm32); 4030 return MCDisassembler_Success; 4031 } 4032 4033 static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Val, 4034 uint64_t Address, const void *Decoder) 4035 { 4036 if (Val & ~0xf) 4037 return MCDisassembler_Fail; 4038 4039 MCOperand_CreateImm0(Inst, Val); 4040 return MCDisassembler_Success; 4041 } 4042 4043 static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Val, 4044 uint64_t Address, const void *Decoder) 4045 { 4046 if (Val & ~0xf) 4047 return MCDisassembler_Fail; 4048 4049 MCOperand_CreateImm0(Inst, Val); 4050 return MCDisassembler_Success; 4051 } 4052 4053 static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Val, 4054 uint64_t Address, const void *Decoder) 4055 { 4056 uint64_t FeatureBits = ARM_getFeatureBits(Inst->csh->mode); 4057 if (FeatureBits & ARM_FeatureMClass) { 4058 unsigned ValLow = Val & 0xff; 4059 4060 // Validate the SYSm value first. 4061 switch (ValLow) { 4062 case 0: // apsr 4063 case 1: // iapsr 4064 case 2: // eapsr 4065 case 3: // xpsr 4066 case 5: // ipsr 4067 case 6: // epsr 4068 case 7: // iepsr 4069 case 8: // msp 4070 case 9: // psp 4071 case 16: // primask 4072 case 20: // control 4073 break; 4074 case 17: // basepri 4075 case 18: // basepri_max 4076 case 19: // faultmask 4077 if (!(FeatureBits & ARM_HasV7Ops)) 4078 // Values basepri, basepri_max and faultmask are only valid for v7m. 4079 return MCDisassembler_Fail; 4080 break; 4081 default: 4082 return MCDisassembler_Fail; 4083 } 4084 4085 // The ARMv7-M architecture has an additional 2-bit mask value in the MSR 4086 // instruction (bits {11,10}). The mask is used only with apsr, iapsr, 4087 // eapsr and xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates 4088 // if the NZCVQ bits should be moved by the instruction. Bit mask{0} 4089 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4090 // only if the processor includes the DSP extension. 4091 if ((FeatureBits & ARM_HasV7Ops) && MCInst_getOpcode(Inst) == ARM_t2MSR_M) { 4092 unsigned Mask = (Val >> 10) & 3; 4093 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4094 (!(FeatureBits & ARM_FeatureDSPThumb2) && Mask == 1)) 4095 return MCDisassembler_Fail; 4096 } 4097 } else { 4098 // A/R class 4099 if (Val == 0) 4100 return MCDisassembler_Fail; 4101 } 4102 4103 MCOperand_CreateImm0(Inst, Val); 4104 return MCDisassembler_Success; 4105 } 4106 4107 static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn, 4108 uint64_t Address, const void *Decoder) 4109 { 4110 DecodeStatus S = MCDisassembler_Success; 4111 4112 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); 4113 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 4114 unsigned pred = fieldFromInstruction_4(Insn, 28, 4); 4115 4116 if (Rn == 0xF) 4117 S = MCDisassembler_SoftFail; 4118 4119 if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4120 return MCDisassembler_Fail; 4121 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4122 return MCDisassembler_Fail; 4123 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4124 return MCDisassembler_Fail; 4125 4126 return S; 4127 } 4128 4129 static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn, 4130 uint64_t Address, const void *Decoder) 4131 { 4132 DecodeStatus S = MCDisassembler_Success; 4133 4134 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); 4135 unsigned Rt = fieldFromInstruction_4(Insn, 0, 4); 4136 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 4137 unsigned pred = fieldFromInstruction_4(Insn, 28, 4); 4138 4139 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4140 return MCDisassembler_Fail; 4141 4142 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4143 S = MCDisassembler_SoftFail; 4144 4145 if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4146 return MCDisassembler_Fail; 4147 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4148 return MCDisassembler_Fail; 4149 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4150 return MCDisassembler_Fail; 4151 4152 return S; 4153 } 4154 4155 static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn, 4156 uint64_t Address, const void *Decoder) 4157 { 4158 DecodeStatus S = MCDisassembler_Success; 4159 unsigned pred; 4160 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 4161 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); 4162 unsigned imm = fieldFromInstruction_4(Insn, 0, 12); 4163 imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; 4164 imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; 4165 pred = fieldFromInstruction_4(Insn, 28, 4); 4166 4167 if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; 4168 4169 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4170 return MCDisassembler_Fail; 4171 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4172 return MCDisassembler_Fail; 4173 if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4174 return MCDisassembler_Fail; 4175 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4176 return MCDisassembler_Fail; 4177 4178 return S; 4179 } 4180 4181 static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn, 4182 uint64_t Address, const void *Decoder) 4183 { 4184 DecodeStatus S = MCDisassembler_Success; 4185 unsigned pred, Rm; 4186 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 4187 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); 4188 unsigned imm = fieldFromInstruction_4(Insn, 0, 12); 4189 imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; 4190 imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; 4191 pred = fieldFromInstruction_4(Insn, 28, 4); 4192 Rm = fieldFromInstruction_4(Insn, 0, 4); 4193 4194 if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; 4195 if (Rm == 0xF) S = MCDisassembler_SoftFail; 4196 4197 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4198 return MCDisassembler_Fail; 4199 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4200 return MCDisassembler_Fail; 4201 if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4202 return MCDisassembler_Fail; 4203 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4204 return MCDisassembler_Fail; 4205 4206 return S; 4207 } 4208 4209 static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn, 4210 uint64_t Address, const void *Decoder) 4211 { 4212 DecodeStatus S = MCDisassembler_Success; 4213 unsigned pred; 4214 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 4215 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); 4216 unsigned imm = fieldFromInstruction_4(Insn, 0, 12); 4217 imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; 4218 imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; 4219 pred = fieldFromInstruction_4(Insn, 28, 4); 4220 4221 if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; 4222 4223 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4224 return MCDisassembler_Fail; 4225 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4226 return MCDisassembler_Fail; 4227 if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4228 return MCDisassembler_Fail; 4229 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4230 return MCDisassembler_Fail; 4231 4232 return S; 4233 } 4234 4235 static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn, 4236 uint64_t Address, const void *Decoder) 4237 { 4238 DecodeStatus S = MCDisassembler_Success; 4239 unsigned pred; 4240 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 4241 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); 4242 unsigned imm = fieldFromInstruction_4(Insn, 0, 12); 4243 imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; 4244 imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; 4245 pred = fieldFromInstruction_4(Insn, 28, 4); 4246 4247 if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; 4248 4249 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4250 return MCDisassembler_Fail; 4251 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4252 return MCDisassembler_Fail; 4253 if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4254 return MCDisassembler_Fail; 4255 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4256 return MCDisassembler_Fail; 4257 4258 return S; 4259 } 4260 4261 static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn, 4262 uint64_t Address, const void *Decoder) 4263 { 4264 DecodeStatus S = MCDisassembler_Success; 4265 unsigned size, align = 0, index = 0; 4266 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 4267 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); 4268 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); 4269 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; 4270 size = fieldFromInstruction_4(Insn, 10, 2); 4271 4272 switch (size) { 4273 default: 4274 return MCDisassembler_Fail; 4275 case 0: 4276 if (fieldFromInstruction_4(Insn, 4, 1)) 4277 return MCDisassembler_Fail; // UNDEFINED 4278 index = fieldFromInstruction_4(Insn, 5, 3); 4279 break; 4280 case 1: 4281 if (fieldFromInstruction_4(Insn, 5, 1)) 4282 return MCDisassembler_Fail; // UNDEFINED 4283 index = fieldFromInstruction_4(Insn, 6, 2); 4284 if (fieldFromInstruction_4(Insn, 4, 1)) 4285 align = 2; 4286 break; 4287 case 2: 4288 if (fieldFromInstruction_4(Insn, 6, 1)) 4289 return MCDisassembler_Fail; // UNDEFINED 4290 index = fieldFromInstruction_4(Insn, 7, 1); 4291 4292 switch (fieldFromInstruction_4(Insn, 4, 2)) { 4293 case 0 : 4294 align = 0; break; 4295 case 3: 4296 align = 4; break; 4297 default: 4298 return MCDisassembler_Fail; 4299 } 4300 break; 4301 } 4302 4303 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4304 return MCDisassembler_Fail; 4305 if (Rm != 0xF) { // Writeback 4306 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4307 return MCDisassembler_Fail; 4308 } 4309 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4310 return MCDisassembler_Fail; 4311 MCOperand_CreateImm0(Inst, align); 4312 if (Rm != 0xF) { 4313 if (Rm != 0xD) { 4314 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4315 return MCDisassembler_Fail; 4316 } else 4317 MCOperand_CreateReg0(Inst, 0); 4318 } 4319 4320 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4321 return MCDisassembler_Fail; 4322 MCOperand_CreateImm0(Inst, index); 4323 4324 return S; 4325 } 4326 4327 static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn, 4328 uint64_t Address, const void *Decoder) 4329 { 4330 DecodeStatus S = MCDisassembler_Success; 4331 unsigned size, align = 0, index = 0; 4332 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 4333 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); 4334 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); 4335 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; 4336 size = fieldFromInstruction_4(Insn, 10, 2); 4337 4338 switch (size) { 4339 default: 4340 return MCDisassembler_Fail; 4341 case 0: 4342 if (fieldFromInstruction_4(Insn, 4, 1)) 4343 return MCDisassembler_Fail; // UNDEFINED 4344 index = fieldFromInstruction_4(Insn, 5, 3); 4345 break; 4346 case 1: 4347 if (fieldFromInstruction_4(Insn, 5, 1)) 4348 return MCDisassembler_Fail; // UNDEFINED 4349 index = fieldFromInstruction_4(Insn, 6, 2); 4350 if (fieldFromInstruction_4(Insn, 4, 1)) 4351 align = 2; 4352 break; 4353 case 2: 4354 if (fieldFromInstruction_4(Insn, 6, 1)) 4355 return MCDisassembler_Fail; // UNDEFINED 4356 index = fieldFromInstruction_4(Insn, 7, 1); 4357 4358 switch (fieldFromInstruction_4(Insn, 4, 2)) { 4359 case 0: 4360 align = 0; break; 4361 case 3: 4362 align = 4; break; 4363 default: 4364 return MCDisassembler_Fail; 4365 } 4366 break; 4367 } 4368 4369 if (Rm != 0xF) { // Writeback 4370 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4371 return MCDisassembler_Fail; 4372 } 4373 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4374 return MCDisassembler_Fail; 4375 MCOperand_CreateImm0(Inst, align); 4376 if (Rm != 0xF) { 4377 if (Rm != 0xD) { 4378 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4379 return MCDisassembler_Fail; 4380 } else 4381 MCOperand_CreateReg0(Inst, 0); 4382 } 4383 4384 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4385 return MCDisassembler_Fail; 4386 MCOperand_CreateImm0(Inst, index); 4387 4388 return S; 4389 } 4390 4391 static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn, 4392 uint64_t Address, const void *Decoder) 4393 { 4394 DecodeStatus S = MCDisassembler_Success; 4395 unsigned size, align = 0, index = 0, inc = 1; 4396 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 4397 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); 4398 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); 4399 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; 4400 size = fieldFromInstruction_4(Insn, 10, 2); 4401 4402 switch (size) { 4403 default: 4404 return MCDisassembler_Fail; 4405 case 0: 4406 index = fieldFromInstruction_4(Insn, 5, 3); 4407 if (fieldFromInstruction_4(Insn, 4, 1)) 4408 align = 2; 4409 break; 4410 case 1: 4411 index = fieldFromInstruction_4(Insn, 6, 2); 4412 if (fieldFromInstruction_4(Insn, 4, 1)) 4413 align = 4; 4414 if (fieldFromInstruction_4(Insn, 5, 1)) 4415 inc = 2; 4416 break; 4417 case 2: 4418 if (fieldFromInstruction_4(Insn, 5, 1)) 4419 return MCDisassembler_Fail; // UNDEFINED 4420 index = fieldFromInstruction_4(Insn, 7, 1); 4421 if (fieldFromInstruction_4(Insn, 4, 1) != 0) 4422 align = 8; 4423 if (fieldFromInstruction_4(Insn, 6, 1)) 4424 inc = 2; 4425 break; 4426 } 4427 4428 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4429 return MCDisassembler_Fail; 4430 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4431 return MCDisassembler_Fail; 4432 if (Rm != 0xF) { // Writeback 4433 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4434 return MCDisassembler_Fail; 4435 } 4436 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4437 return MCDisassembler_Fail; 4438 MCOperand_CreateImm0(Inst, align); 4439 if (Rm != 0xF) { 4440 if (Rm != 0xD) { 4441 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4442 return MCDisassembler_Fail; 4443 } else 4444 MCOperand_CreateReg0(Inst, 0); 4445 } 4446 4447 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4448 return MCDisassembler_Fail; 4449 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4450 return MCDisassembler_Fail; 4451 MCOperand_CreateImm0(Inst, index); 4452 4453 return S; 4454 } 4455 4456 static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn, 4457 uint64_t Address, const void *Decoder) 4458 { 4459 DecodeStatus S = MCDisassembler_Success; 4460 unsigned size, align = 0, index = 0, inc = 1; 4461 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 4462 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); 4463 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); 4464 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; 4465 size = fieldFromInstruction_4(Insn, 10, 2); 4466 4467 switch (size) { 4468 default: 4469 return MCDisassembler_Fail; 4470 case 0: 4471 index = fieldFromInstruction_4(Insn, 5, 3); 4472 if (fieldFromInstruction_4(Insn, 4, 1)) 4473 align = 2; 4474 break; 4475 case 1: 4476 index = fieldFromInstruction_4(Insn, 6, 2); 4477 if (fieldFromInstruction_4(Insn, 4, 1)) 4478 align = 4; 4479 if (fieldFromInstruction_4(Insn, 5, 1)) 4480 inc = 2; 4481 break; 4482 case 2: 4483 if (fieldFromInstruction_4(Insn, 5, 1)) 4484 return MCDisassembler_Fail; // UNDEFINED 4485 index = fieldFromInstruction_4(Insn, 7, 1); 4486 if (fieldFromInstruction_4(Insn, 4, 1) != 0) 4487 align = 8; 4488 if (fieldFromInstruction_4(Insn, 6, 1)) 4489 inc = 2; 4490 break; 4491 } 4492 4493 if (Rm != 0xF) { // Writeback 4494 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4495 return MCDisassembler_Fail; 4496 } 4497 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4498 return MCDisassembler_Fail; 4499 MCOperand_CreateImm0(Inst, align); 4500 if (Rm != 0xF) { 4501 if (Rm != 0xD) { 4502 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4503 return MCDisassembler_Fail; 4504 } else 4505 MCOperand_CreateReg0(Inst, 0); 4506 } 4507 4508 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4509 return MCDisassembler_Fail; 4510 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4511 return MCDisassembler_Fail; 4512 MCOperand_CreateImm0(Inst, index); 4513 4514 return S; 4515 } 4516 4517 static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn, 4518 uint64_t Address, const void *Decoder) 4519 { 4520 DecodeStatus S = MCDisassembler_Success; 4521 unsigned size, align = 0, index = 0, inc = 1; 4522 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 4523 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); 4524 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); 4525 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; 4526 size = fieldFromInstruction_4(Insn, 10, 2); 4527 4528 switch (size) { 4529 default: 4530 return MCDisassembler_Fail; 4531 case 0: 4532 if (fieldFromInstruction_4(Insn, 4, 1)) 4533 return MCDisassembler_Fail; // UNDEFINED 4534 index = fieldFromInstruction_4(Insn, 5, 3); 4535 break; 4536 case 1: 4537 if (fieldFromInstruction_4(Insn, 4, 1)) 4538 return MCDisassembler_Fail; // UNDEFINED 4539 index = fieldFromInstruction_4(Insn, 6, 2); 4540 if (fieldFromInstruction_4(Insn, 5, 1)) 4541 inc = 2; 4542 break; 4543 case 2: 4544 if (fieldFromInstruction_4(Insn, 4, 2)) 4545 return MCDisassembler_Fail; // UNDEFINED 4546 index = fieldFromInstruction_4(Insn, 7, 1); 4547 if (fieldFromInstruction_4(Insn, 6, 1)) 4548 inc = 2; 4549 break; 4550 } 4551 4552 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4553 return MCDisassembler_Fail; 4554 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4555 return MCDisassembler_Fail; 4556 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4557 return MCDisassembler_Fail; 4558 4559 if (Rm != 0xF) { // Writeback 4560 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4561 return MCDisassembler_Fail; 4562 } 4563 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4564 return MCDisassembler_Fail; 4565 MCOperand_CreateImm0(Inst, align); 4566 if (Rm != 0xF) { 4567 if (Rm != 0xD) { 4568 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4569 return MCDisassembler_Fail; 4570 } else 4571 MCOperand_CreateReg0(Inst, 0); 4572 } 4573 4574 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4575 return MCDisassembler_Fail; 4576 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4577 return MCDisassembler_Fail; 4578 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4579 return MCDisassembler_Fail; 4580 MCOperand_CreateImm0(Inst, index); 4581 4582 return S; 4583 } 4584 4585 static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn, 4586 uint64_t Address, const void *Decoder) 4587 { 4588 DecodeStatus S = MCDisassembler_Success; 4589 unsigned size, align = 0, index = 0, inc = 1; 4590 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 4591 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); 4592 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); 4593 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; 4594 size = fieldFromInstruction_4(Insn, 10, 2); 4595 4596 switch (size) { 4597 default: 4598 return MCDisassembler_Fail; 4599 case 0: 4600 if (fieldFromInstruction_4(Insn, 4, 1)) 4601 return MCDisassembler_Fail; // UNDEFINED 4602 index = fieldFromInstruction_4(Insn, 5, 3); 4603 break; 4604 case 1: 4605 if (fieldFromInstruction_4(Insn, 4, 1)) 4606 return MCDisassembler_Fail; // UNDEFINED 4607 index = fieldFromInstruction_4(Insn, 6, 2); 4608 if (fieldFromInstruction_4(Insn, 5, 1)) 4609 inc = 2; 4610 break; 4611 case 2: 4612 if (fieldFromInstruction_4(Insn, 4, 2)) 4613 return MCDisassembler_Fail; // UNDEFINED 4614 index = fieldFromInstruction_4(Insn, 7, 1); 4615 if (fieldFromInstruction_4(Insn, 6, 1)) 4616 inc = 2; 4617 break; 4618 } 4619 4620 if (Rm != 0xF) { // Writeback 4621 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4622 return MCDisassembler_Fail; 4623 } 4624 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4625 return MCDisassembler_Fail; 4626 MCOperand_CreateImm0(Inst, align); 4627 if (Rm != 0xF) { 4628 if (Rm != 0xD) { 4629 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4630 return MCDisassembler_Fail; 4631 } else 4632 MCOperand_CreateReg0(Inst, 0); 4633 } 4634 4635 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4636 return MCDisassembler_Fail; 4637 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4638 return MCDisassembler_Fail; 4639 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4640 return MCDisassembler_Fail; 4641 MCOperand_CreateImm0(Inst, index); 4642 4643 return S; 4644 } 4645 4646 static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn, 4647 uint64_t Address, const void *Decoder) 4648 { 4649 DecodeStatus S = MCDisassembler_Success; 4650 unsigned size, align = 0, index = 0, inc = 1; 4651 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 4652 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); 4653 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); 4654 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; 4655 size = fieldFromInstruction_4(Insn, 10, 2); 4656 4657 switch (size) { 4658 default: 4659 return MCDisassembler_Fail; 4660 case 0: 4661 if (fieldFromInstruction_4(Insn, 4, 1)) 4662 align = 4; 4663 index = fieldFromInstruction_4(Insn, 5, 3); 4664 break; 4665 case 1: 4666 if (fieldFromInstruction_4(Insn, 4, 1)) 4667 align = 8; 4668 index = fieldFromInstruction_4(Insn, 6, 2); 4669 if (fieldFromInstruction_4(Insn, 5, 1)) 4670 inc = 2; 4671 break; 4672 case 2: 4673 switch (fieldFromInstruction_4(Insn, 4, 2)) { 4674 case 0: 4675 align = 0; break; 4676 case 3: 4677 return MCDisassembler_Fail; 4678 default: 4679 align = 4 << fieldFromInstruction_4(Insn, 4, 2); break; 4680 } 4681 4682 index = fieldFromInstruction_4(Insn, 7, 1); 4683 if (fieldFromInstruction_4(Insn, 6, 1)) 4684 inc = 2; 4685 break; 4686 } 4687 4688 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4689 return MCDisassembler_Fail; 4690 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4691 return MCDisassembler_Fail; 4692 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4693 return MCDisassembler_Fail; 4694 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4695 return MCDisassembler_Fail; 4696 4697 if (Rm != 0xF) { // Writeback 4698 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4699 return MCDisassembler_Fail; 4700 } 4701 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4702 return MCDisassembler_Fail; 4703 MCOperand_CreateImm0(Inst, align); 4704 if (Rm != 0xF) { 4705 if (Rm != 0xD) { 4706 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4707 return MCDisassembler_Fail; 4708 } else 4709 MCOperand_CreateReg0(Inst, 0); 4710 } 4711 4712 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4713 return MCDisassembler_Fail; 4714 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4715 return MCDisassembler_Fail; 4716 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4717 return MCDisassembler_Fail; 4718 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4719 return MCDisassembler_Fail; 4720 MCOperand_CreateImm0(Inst, index); 4721 4722 return S; 4723 } 4724 4725 static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn, 4726 uint64_t Address, const void *Decoder) 4727 { 4728 DecodeStatus S = MCDisassembler_Success; 4729 unsigned size, align = 0, index = 0, inc = 1; 4730 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 4731 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); 4732 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); 4733 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; 4734 size = fieldFromInstruction_4(Insn, 10, 2); 4735 4736 switch (size) { 4737 default: 4738 return MCDisassembler_Fail; 4739 case 0: 4740 if (fieldFromInstruction_4(Insn, 4, 1)) 4741 align = 4; 4742 index = fieldFromInstruction_4(Insn, 5, 3); 4743 break; 4744 case 1: 4745 if (fieldFromInstruction_4(Insn, 4, 1)) 4746 align = 8; 4747 index = fieldFromInstruction_4(Insn, 6, 2); 4748 if (fieldFromInstruction_4(Insn, 5, 1)) 4749 inc = 2; 4750 break; 4751 case 2: 4752 switch (fieldFromInstruction_4(Insn, 4, 2)) { 4753 case 0: 4754 align = 0; break; 4755 case 3: 4756 return MCDisassembler_Fail; 4757 default: 4758 align = 4 << fieldFromInstruction_4(Insn, 4, 2); break; 4759 } 4760 4761 index = fieldFromInstruction_4(Insn, 7, 1); 4762 if (fieldFromInstruction_4(Insn, 6, 1)) 4763 inc = 2; 4764 break; 4765 } 4766 4767 if (Rm != 0xF) { // Writeback 4768 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4769 return MCDisassembler_Fail; 4770 } 4771 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4772 return MCDisassembler_Fail; 4773 MCOperand_CreateImm0(Inst, align); 4774 if (Rm != 0xF) { 4775 if (Rm != 0xD) { 4776 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4777 return MCDisassembler_Fail; 4778 } else 4779 MCOperand_CreateReg0(Inst, 0); 4780 } 4781 4782 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4783 return MCDisassembler_Fail; 4784 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4785 return MCDisassembler_Fail; 4786 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4787 return MCDisassembler_Fail; 4788 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4789 return MCDisassembler_Fail; 4790 MCOperand_CreateImm0(Inst, index); 4791 4792 return S; 4793 } 4794 4795 static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn, 4796 uint64_t Address, const void *Decoder) 4797 { 4798 DecodeStatus S = MCDisassembler_Success; 4799 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); 4800 unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); 4801 unsigned Rm = fieldFromInstruction_4(Insn, 5, 1); 4802 unsigned pred = fieldFromInstruction_4(Insn, 28, 4); 4803 Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1; 4804 4805 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4806 S = MCDisassembler_SoftFail; 4807 4808 if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4809 return MCDisassembler_Fail; 4810 if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4811 return MCDisassembler_Fail; 4812 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4813 return MCDisassembler_Fail; 4814 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4815 return MCDisassembler_Fail; 4816 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4817 return MCDisassembler_Fail; 4818 4819 return S; 4820 } 4821 4822 static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn, 4823 uint64_t Address, const void *Decoder) 4824 { 4825 DecodeStatus S = MCDisassembler_Success; 4826 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); 4827 unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); 4828 unsigned Rm = fieldFromInstruction_4(Insn, 5, 1); 4829 unsigned pred = fieldFromInstruction_4(Insn, 28, 4); 4830 Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1; 4831 4832 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4833 S = MCDisassembler_SoftFail; 4834 4835 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4836 return MCDisassembler_Fail; 4837 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4838 return MCDisassembler_Fail; 4839 if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4840 return MCDisassembler_Fail; 4841 if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4842 return MCDisassembler_Fail; 4843 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4844 return MCDisassembler_Fail; 4845 4846 return S; 4847 } 4848 4849 static DecodeStatus DecodeIT(MCInst *Inst, unsigned Insn, 4850 uint64_t Address, const void *Decoder) 4851 { 4852 DecodeStatus S = MCDisassembler_Success; 4853 unsigned pred = fieldFromInstruction_4(Insn, 4, 4); 4854 unsigned mask = fieldFromInstruction_4(Insn, 0, 4); 4855 4856 if (pred == 0xF) { 4857 pred = 0xE; 4858 S = MCDisassembler_SoftFail; 4859 } 4860 4861 if (mask == 0x0) 4862 return MCDisassembler_Fail; 4863 4864 MCOperand_CreateImm0(Inst, pred); 4865 MCOperand_CreateImm0(Inst, mask); 4866 return S; 4867 } 4868 4869 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst, unsigned Insn, 4870 uint64_t Address, const void *Decoder) 4871 { 4872 DecodeStatus S = MCDisassembler_Success; 4873 4874 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); 4875 unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4); 4876 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 4877 unsigned addr = fieldFromInstruction_4(Insn, 0, 8); 4878 unsigned W = fieldFromInstruction_4(Insn, 21, 1); 4879 unsigned U = fieldFromInstruction_4(Insn, 23, 1); 4880 unsigned P = fieldFromInstruction_4(Insn, 24, 1); 4881 bool writeback = (W == 1) | (P == 0); 4882 4883 addr |= (U << 8) | (Rn << 9); 4884 4885 if (writeback && (Rn == Rt || Rn == Rt2)) 4886 Check(&S, MCDisassembler_SoftFail); 4887 if (Rt == Rt2) 4888 Check(&S, MCDisassembler_SoftFail); 4889 4890 // Rt 4891 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4892 return MCDisassembler_Fail; 4893 // Rt2 4894 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4895 return MCDisassembler_Fail; 4896 // Writeback operand 4897 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4898 return MCDisassembler_Fail; 4899 // addr 4900 if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4901 return MCDisassembler_Fail; 4902 4903 return S; 4904 } 4905 4906 static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst, unsigned Insn, 4907 uint64_t Address, const void *Decoder) 4908 { 4909 DecodeStatus S = MCDisassembler_Success; 4910 4911 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); 4912 unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4); 4913 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 4914 unsigned addr = fieldFromInstruction_4(Insn, 0, 8); 4915 unsigned W = fieldFromInstruction_4(Insn, 21, 1); 4916 unsigned U = fieldFromInstruction_4(Insn, 23, 1); 4917 unsigned P = fieldFromInstruction_4(Insn, 24, 1); 4918 bool writeback = (W == 1) | (P == 0); 4919 4920 addr |= (U << 8) | (Rn << 9); 4921 4922 if (writeback && (Rn == Rt || Rn == Rt2)) 4923 Check(&S, MCDisassembler_SoftFail); 4924 4925 // Writeback operand 4926 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4927 return MCDisassembler_Fail; 4928 // Rt 4929 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4930 return MCDisassembler_Fail; 4931 // Rt2 4932 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4933 return MCDisassembler_Fail; 4934 // addr 4935 if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4936 return MCDisassembler_Fail; 4937 4938 return S; 4939 } 4940 4941 static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Insn, 4942 uint64_t Address, const void *Decoder) 4943 { 4944 unsigned Val; 4945 unsigned sign1 = fieldFromInstruction_4(Insn, 21, 1); 4946 unsigned sign2 = fieldFromInstruction_4(Insn, 23, 1); 4947 if (sign1 != sign2) return MCDisassembler_Fail; 4948 4949 Val = fieldFromInstruction_4(Insn, 0, 8); 4950 Val |= fieldFromInstruction_4(Insn, 12, 3) << 8; 4951 Val |= fieldFromInstruction_4(Insn, 26, 1) << 11; 4952 Val |= sign1 << 12; 4953 MCOperand_CreateImm0(Inst, SignExtend32(Val, 13)); 4954 4955 return MCDisassembler_Success; 4956 } 4957 4958 static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val, 4959 uint64_t Address, const void *Decoder) 4960 { 4961 DecodeStatus S = MCDisassembler_Success; 4962 4963 // Shift of "asr #32" is not allowed in Thumb2 mode. 4964 if (Val == 0x20) S = MCDisassembler_SoftFail; 4965 MCOperand_CreateImm0(Inst, Val); 4966 return S; 4967 } 4968 4969 static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn, 4970 uint64_t Address, const void *Decoder) 4971 { 4972 DecodeStatus S; 4973 4974 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); 4975 unsigned Rt2 = fieldFromInstruction_4(Insn, 0, 4); 4976 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); 4977 unsigned pred = fieldFromInstruction_4(Insn, 28, 4); 4978 4979 if (pred == 0xF) 4980 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4981 4982 S = MCDisassembler_Success; 4983 4984 if (Rt == Rn || Rn == Rt2) 4985 S = MCDisassembler_SoftFail; 4986 4987 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4988 return MCDisassembler_Fail; 4989 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4990 return MCDisassembler_Fail; 4991 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4992 return MCDisassembler_Fail; 4993 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4994 return MCDisassembler_Fail; 4995 4996 return S; 4997 } 4998 4999 static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn, 5000 uint64_t Address, const void *Decoder) 5001 { 5002 DecodeStatus S = MCDisassembler_Success; 5003 unsigned Vm, imm, cmode, op; 5004 unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); 5005 Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); 5006 Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); 5007 Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); 5008 imm = fieldFromInstruction_4(Insn, 16, 6); 5009 cmode = fieldFromInstruction_4(Insn, 8, 4); 5010 op = fieldFromInstruction_4(Insn, 5, 1); 5011 5012 // VMOVv2f32 is ambiguous with these decodings. 5013 if (!(imm & 0x38) && cmode == 0xF) { 5014 if (op == 1) return MCDisassembler_Fail; 5015 MCInst_setOpcode(Inst, ARM_VMOVv2f32); 5016 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5017 } 5018 5019 if (!(imm & 0x20)) return MCDisassembler_Fail; 5020 5021 if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5022 return MCDisassembler_Fail; 5023 if (!Check(&S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5024 return MCDisassembler_Fail; 5025 MCOperand_CreateImm0(Inst, 64 - imm); 5026 5027 return S; 5028 } 5029 5030 static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn, 5031 uint64_t Address, const void *Decoder) 5032 { 5033 DecodeStatus S = MCDisassembler_Success; 5034 unsigned Vm, imm, cmode, op; 5035 unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); 5036 Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); 5037 Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); 5038 Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); 5039 imm = fieldFromInstruction_4(Insn, 16, 6); 5040 cmode = fieldFromInstruction_4(Insn, 8, 4); 5041 op = fieldFromInstruction_4(Insn, 5, 1); 5042 5043 // VMOVv4f32 is ambiguous with these decodings. 5044 if (!(imm & 0x38) && cmode == 0xF) { 5045 if (op == 1) return MCDisassembler_Fail; 5046 MCInst_setOpcode(Inst, ARM_VMOVv4f32); 5047 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5048 } 5049 5050 if (!(imm & 0x20)) return MCDisassembler_Fail; 5051 5052 if (!Check(&S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5053 return MCDisassembler_Fail; 5054 if (!Check(&S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5055 return MCDisassembler_Fail; 5056 MCOperand_CreateImm0(Inst, 64 - imm); 5057 5058 return S; 5059 } 5060 5061 static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val, 5062 uint64_t Address, const void *Decoder) 5063 { 5064 DecodeStatus S = MCDisassembler_Success; 5065 unsigned Cond; 5066 unsigned Rn = fieldFromInstruction_4(Val, 16, 4); 5067 unsigned Rt = fieldFromInstruction_4(Val, 12, 4); 5068 unsigned Rm = fieldFromInstruction_4(Val, 0, 4); 5069 Rm |= (fieldFromInstruction_4(Val, 23, 1) << 4); 5070 Cond = fieldFromInstruction_4(Val, 28, 4); 5071 5072 if (fieldFromInstruction_4(Val, 8, 4) != 0 || Rn == Rt) 5073 S = MCDisassembler_SoftFail; 5074 5075 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5076 return MCDisassembler_Fail; 5077 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5078 return MCDisassembler_Fail; 5079 if (!Check(&S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5080 return MCDisassembler_Fail; 5081 if (!Check(&S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5082 return MCDisassembler_Fail; 5083 if (!Check(&S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5084 return MCDisassembler_Fail; 5085 5086 return S; 5087 } 5088 5089 static DecodeStatus DecodeMRRC2(MCInst *Inst, unsigned Val, 5090 uint64_t Address, const void *Decoder) 5091 { 5092 5093 DecodeStatus S = MCDisassembler_Success; 5094 5095 unsigned CRm = fieldFromInstruction_4(Val, 0, 4); 5096 unsigned opc1 = fieldFromInstruction_4(Val, 4, 4); 5097 unsigned cop = fieldFromInstruction_4(Val, 8, 4); 5098 unsigned Rt = fieldFromInstruction_4(Val, 12, 4); 5099 unsigned Rt2 = fieldFromInstruction_4(Val, 16, 4); 5100 5101 if ((cop & ~0x1) == 0xa) 5102 return MCDisassembler_Fail; 5103 5104 if (Rt == Rt2) 5105 S = MCDisassembler_SoftFail; 5106 5107 MCOperand_CreateImm0(Inst, cop); 5108 MCOperand_CreateImm0(Inst, opc1); 5109 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5110 return MCDisassembler_Fail; 5111 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5112 return MCDisassembler_Fail; 5113 MCOperand_CreateImm0(Inst, CRm); 5114 5115 return S; 5116 } 5117 5118 #endif 5119
