| /external/libffi/src/tile/ |
| tile.S | 48 #define LW ld
52 #define LW lw
139 LW TMP, INCOMING_STACK_ARGS
159 LW r0, r0
165 LW REG, PTR ; \
186 LW lr, r52
192 LW RETURN_REG_ADDR, TMP
201 LW r52, TMP
311 LW lr, r1
[all...] |
| /external/python/cpython2/Modules/_ctypes/libffi/src/tile/ |
| tile.S | 48 #define LW ld
52 #define LW lw
139 LW TMP, INCOMING_STACK_ARGS
159 LW r0, r0
165 LW REG, PTR ; \
186 LW lr, r52
192 LW RETURN_REG_ADDR, TMP
201 LW r52, TMP
311 LW lr, r1
[all...] |
| /external/python/cpython3/Modules/_ctypes/libffi/src/tile/ |
| tile.S | 48 #define LW ld
52 #define LW lw
139 LW TMP, INCOMING_STACK_ARGS
159 LW r0, r0
165 LW REG, PTR ; \
186 LW lr, r52
192 LW RETURN_REG_ADDR, TMP
201 LW r52, TMP
311 LW lr, r1
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsEmitGPRestore.cpp | 64 // Insert lw.
67 BuildMI(MBB, I, dl, TII->get(Mips::LW), Mips::GP).addFrameIndex(FI)
79 // emit lw $gp, ($gp save slot on stack) after jalr
80 BuildMI(MBB, ++I, dl, TII->get(Mips::LW), Mips::GP).addFrameIndex(FI)
|
| MipsInstrInfo.cpp | 53 if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) ||
201 Opc = IsN64 ? Mips::LW_P8 : Mips::LW;
|
| /external/libyuv/files/include/libyuv/ |
| macros_msa.h | 19 #define LW(psrc) \
23 asm volatile("lw %[val_m], %[psrc_lw_m] \n" \
45 val0_m = LW(psrc_ld_m); \
46 val1_m = LW(psrc_ld_m + 4); \
84 #define LW(psrc) \
110 val0_m = LW(psrc_ld_m); \
111 val1_m = LW(psrc_ld_m + 4); \
|
| /bionic/libc/arch-mips/string/ |
| strcmp.S | 49 # define LW ld
56 # define LW lw
162 LW $v0, OFFSET($a0); \
163 LW $v1, OFFSET($a1); \
191 LW $v1, OFFSET($a1); \
197 LW $a3, (OFFSET + NSIZE)($a2); \
208 LW $v0, 0($a2)
|
| strncmp.S | 49 # define LW ld
57 # define LW lw
175 LW $v0, (OFFSET)($a0); \
176 LW $v1, (OFFSET)($a1); \
219 LW $v1, (OFFSET)($a1); \
|
| /external/libpng/mips/ |
| filter_msa_intrinsics.c | 44 #define LW(psrc) \
50 "lw %[val_m], %[psrc_lw_m] \n\t" \
115 #define LW(psrc) \
121 "lw %[val_m], %[psrc_lw_m] \n\t" \
183 #define LW(psrc) \
471 inp0 = LW(src);
512 inp0 = LW(src);
553 inp0 = LW(pp);
555 inp1 = LW(src);
608 inp0 = LW(pp)
[all...] |
| /external/clang/utils/ABITest/ |
| Enumeration.py | 150 LW,RW = W//2, W - (W//2)
151 L,R = getNthPairBounded(N, H**LW, H**RW)
152 return (getNthNTuple(L,LW,H=H,useLeftToRight=useLeftToRight) +
|
| /external/libvpx/libvpx/vpx_dsp/mips/ |
| intrapred_msa.c | 24 src_data = LW(src);
34 src_data1 = LW(src);
35 src_data2 = LW(src + 4);
162 val0 = LW(src_top);
163 val1 = LW(src_left);
182 val0 = LW(src);
394 val = LW(src_top_ptr);
|
| macros_msa.h | 39 #define LW(psrc) \
58 val0_ld_m = LW(psrc_ld_m); \
59 val1_ld_m = LW(psrc_ld_m + 4); \
86 #define LW(psrc) \
119 val0_ld_m = LW(psrc_ld_m); \
120 val1_ld_m = LW(psrc_ld_m + 4); \
175 out0 = LW((psrc)); \
176 out1 = LW((psrc) + stride); \
177 out2 = LW((psrc) + 2 * stride); \
178 out3 = LW((psrc) + 3 * stride);
[all...] |
| vpx_convolve_copy_msa.c | 216 tmp = LW(src);
|
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.cpp | 177 mMips->LW(R_s0, R_sp, 0);
178 mMips->LW(R_s1, R_sp, 4);
179 mMips->LW(R_s2, R_sp, 8);
180 mMips->LW(R_s3, R_sp, 12);
181 mMips->LW(R_s4, R_sp, 16);
774 Rn = R_sp; // convert LDR via Arm SP to LW via Mips SP
776 mMips->LW(Rd, Rn, amode.value);
785 mMips->LW(Rd, Rn, 0);
791 mMips->LW(Rd, R_at, 0);
[all...] |
| MIPS64Assembler.cpp | 762 Rn = R_sp; // convert LDR via Arm SP to LW via Mips SP
764 mMips->LW(Rd, Rn, amode.value);
773 mMips->LW(Rd, Rn, 0);
779 mMips->LW(Rd, R_at, 0);
[all...] |
| /external/libyuv/files/source/ |
| scale_msa.cc | 109 data0 = LW(src_argb);
110 data1 = LW(src_argb + stepx);
111 data2 = LW(src_argb + stepx * 2);
112 data3 = LW(src_argb + stepx * 3);
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsNaClELFStreamer.cpp | 216 case Mips::LW:
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 45 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
266 Opc = Mips::LW;
292 Opc = Mips::LW;
296 Opc = Mips::LW;
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| MBlazeISelDAGToDAG.cpp | 239 SDValue Load = SDValue(CurDAG->getMachineNode(MBlaze::LW, dl,
|
| /external/libvpx/libvpx/vp8/common/mips/msa/ |
| vp8_macros_msa.h | 43 #define LW(psrc) \
48 asm volatile("lw %[val_m], %[psrc_m] \n\t" \
76 val0_m = LW(psrc_m); \
77 val1_m = LW(psrc_m + 4); \
120 #define LW(psrc) \
153 val0_m = LW(psrc_m1); \
154 val1_m = LW(psrc_m1 + 4); \
208 out0 = LW((psrc)); \
209 out1 = LW((psrc) + stride); \
210 out2 = LW((psrc) + 2 * stride);
[all...] |
| /external/webp/src/dsp/ |
| msa_macro.h | 100 MSA_LOAD_FUNC(uint32_t, lw, msa_lw);
101 #define LW(psrc) MSA_LOAD(psrc, msa_lw)
120 #define LW(psrc) MSA_LOAD(psrc, msa_ulw)
152 out0 = LW(ptmp); \
154 out1 = LW(ptmp); \
156 out2 = LW(ptmp); \
158 out3 = LW(ptmp); \
[all...] |
| dec_msa.c | 709 const uint32_t val0 = LW(ptop + 0);
710 const uint32_t val1 = LW(ptop + 4);
726 uint32_t val0 = LW(ptop + 0);
727 uint32_t val1 = LW(ptop + 4);
754 uint32_t val0 = LW(ptop + 0);
755 uint32_t val1 = LW(ptop + 4);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/ |
| MBlazeDisassembler.cpp | 56 MBlaze::LBU, MBlaze::LHU, MBlaze::LW, UNSUPPORTED, //30,31,32,33
374 case 0x0: return MBlaze::LW;
475 case MBlaze::LW: return decodeLW(insn);
|
| /external/v8/src/mips/ |
| assembler-mips.cc | 270 // lw(r, MemOperand(sp, 0))
272 LW | (Register::kCode_sp << kRsShift) | (0 & kImm16Mask); // NOLINT
275 LW | (Register::kCode_fp << kRsShift) | (0 & kImm16Mask); // NOLINT
280 const Instr kLwRegFpNegOffsetPattern = LW | (Register::kCode_fp << kRsShift) |
285 // A mask for the Rt register for push, pop, lw, sw instructions.
656 return (static_cast<uint32_t>(instr & kOpcodeMask) == LW);
669 // We actually create a new lw instruction based on the original one.
670 Instr temp_instr = LW | (instr & kRsFieldMask) | (instr & kRtFieldMask)
1877 void Assembler::lw(Register rd, const MemOperand& rs) { function in class:v8::Assembler
[all...] |
| constants-mips.h | 375 LW = ((4U << 3) + 3) << kOpcodeShift,
848 // lw(r, MemOperand(sp, 0))
854 // A mask for the Rt register for push, pop, lw, sw instructions.
915 OpcodeToBitNumber(LW) | OpcodeToBitNumber(LBU) | OpcodeToBitNumber(LHU) |
[all...] |
