1 //===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsSEInstrInfo.h" 15 #include "InstPrinter/MipsInstPrinter.h" 16 #include "MipsAnalyzeImmediate.h" 17 #include "MipsMachineFunction.h" 18 #include "MipsTargetMachine.h" 19 #include "llvm/ADT/STLExtras.h" 20 #include "llvm/CodeGen/MachineInstrBuilder.h" 21 #include "llvm/CodeGen/MachineRegisterInfo.h" 22 #include "llvm/Support/ErrorHandling.h" 23 #include "llvm/Support/MathExtras.h" 24 #include "llvm/Support/TargetRegistry.h" 25 26 using namespace llvm; 27 28 MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI) 29 : MipsInstrInfo(STI, STI.isPositionIndependent() ? Mips::B : Mips::J), 30 RI() {} 31 32 const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const { 33 return RI; 34 } 35 36 /// isLoadFromStackSlot - If the specified machine instruction is a direct 37 /// load from a stack slot, return the virtual or physical register number of 38 /// the destination along with the FrameIndex of the loaded stack slot. If 39 /// not, return 0. This predicate must return 0 if the instruction has 40 /// any side effects other than loading from the stack slot. 41 unsigned MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, 42 int &FrameIndex) const { 43 unsigned Opc = MI.getOpcode(); 44 45 if ((Opc == Mips::LW) || (Opc == Mips::LD) || 46 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { 47 if ((MI.getOperand(1).isFI()) && // is a stack slot 48 (MI.getOperand(2).isImm()) && // the imm is zero 49 (isZeroImm(MI.getOperand(2)))) { 50 FrameIndex = MI.getOperand(1).getIndex(); 51 return MI.getOperand(0).getReg(); 52 } 53 } 54 55 return 0; 56 } 57 58 /// isStoreToStackSlot - If the specified machine instruction is a direct 59 /// store to a stack slot, return the virtual or physical register number of 60 /// the source reg along with the FrameIndex of the loaded stack slot. If 61 /// not, return 0. This predicate must return 0 if the instruction has 62 /// any side effects other than storing to the stack slot. 63 unsigned MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr &MI, 64 int &FrameIndex) const { 65 unsigned Opc = MI.getOpcode(); 66 67 if ((Opc == Mips::SW) || (Opc == Mips::SD) || 68 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { 69 if ((MI.getOperand(1).isFI()) && // is a stack slot 70 (MI.getOperand(2).isImm()) && // the imm is zero 71 (isZeroImm(MI.getOperand(2)))) { 72 FrameIndex = MI.getOperand(1).getIndex(); 73 return MI.getOperand(0).getReg(); 74 } 75 } 76 return 0; 77 } 78 79 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 80 MachineBasicBlock::iterator I, 81 const DebugLoc &DL, unsigned DestReg, 82 unsigned SrcReg, bool KillSrc) const { 83 unsigned Opc = 0, ZeroReg = 0; 84 bool isMicroMips = Subtarget.inMicroMipsMode(); 85 86 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. 87 if (Mips::GPR32RegClass.contains(SrcReg)) { 88 if (isMicroMips) 89 Opc = Mips::MOVE16_MM; 90 else 91 Opc = Mips::OR, ZeroReg = Mips::ZERO; 92 } else if (Mips::CCRRegClass.contains(SrcReg)) 93 Opc = Mips::CFC1; 94 else if (Mips::FGR32RegClass.contains(SrcReg)) 95 Opc = Mips::MFC1; 96 else if (Mips::HI32RegClass.contains(SrcReg)) { 97 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; 98 SrcReg = 0; 99 } else if (Mips::LO32RegClass.contains(SrcReg)) { 100 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; 101 SrcReg = 0; 102 } else if (Mips::HI32DSPRegClass.contains(SrcReg)) 103 Opc = Mips::MFHI_DSP; 104 else if (Mips::LO32DSPRegClass.contains(SrcReg)) 105 Opc = Mips::MFLO_DSP; 106 else if (Mips::DSPCCRegClass.contains(SrcReg)) { 107 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4) 108 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); 109 return; 110 } 111 else if (Mips::MSACtrlRegClass.contains(SrcReg)) 112 Opc = Mips::CFCMSA; 113 } 114 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg. 115 if (Mips::CCRRegClass.contains(DestReg)) 116 Opc = Mips::CTC1; 117 else if (Mips::FGR32RegClass.contains(DestReg)) 118 Opc = Mips::MTC1; 119 else if (Mips::HI32RegClass.contains(DestReg)) 120 Opc = Mips::MTHI, DestReg = 0; 121 else if (Mips::LO32RegClass.contains(DestReg)) 122 Opc = Mips::MTLO, DestReg = 0; 123 else if (Mips::HI32DSPRegClass.contains(DestReg)) 124 Opc = Mips::MTHI_DSP; 125 else if (Mips::LO32DSPRegClass.contains(DestReg)) 126 Opc = Mips::MTLO_DSP; 127 else if (Mips::DSPCCRegClass.contains(DestReg)) { 128 BuildMI(MBB, I, DL, get(Mips::WRDSP)) 129 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4) 130 .addReg(DestReg, RegState::ImplicitDefine); 131 return; 132 } else if (Mips::MSACtrlRegClass.contains(DestReg)) { 133 BuildMI(MBB, I, DL, get(Mips::CTCMSA)) 134 .addReg(DestReg) 135 .addReg(SrcReg, getKillRegState(KillSrc)); 136 return; 137 } 138 } 139 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) 140 Opc = Mips::FMOV_S; 141 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) 142 Opc = Mips::FMOV_D32; 143 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg)) 144 Opc = Mips::FMOV_D64; 145 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg. 146 if (Mips::GPR64RegClass.contains(SrcReg)) 147 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; 148 else if (Mips::HI64RegClass.contains(SrcReg)) 149 Opc = Mips::MFHI64, SrcReg = 0; 150 else if (Mips::LO64RegClass.contains(SrcReg)) 151 Opc = Mips::MFLO64, SrcReg = 0; 152 else if (Mips::FGR64RegClass.contains(SrcReg)) 153 Opc = Mips::DMFC1; 154 } 155 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg. 156 if (Mips::HI64RegClass.contains(DestReg)) 157 Opc = Mips::MTHI64, DestReg = 0; 158 else if (Mips::LO64RegClass.contains(DestReg)) 159 Opc = Mips::MTLO64, DestReg = 0; 160 else if (Mips::FGR64RegClass.contains(DestReg)) 161 Opc = Mips::DMTC1; 162 } 163 else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg 164 if (Mips::MSA128BRegClass.contains(SrcReg)) 165 Opc = Mips::MOVE_V; 166 } 167 168 assert(Opc && "Cannot copy registers"); 169 170 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); 171 172 if (DestReg) 173 MIB.addReg(DestReg, RegState::Define); 174 175 if (SrcReg) 176 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 177 178 if (ZeroReg) 179 MIB.addReg(ZeroReg); 180 } 181 182 void MipsSEInstrInfo:: 183 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 184 unsigned SrcReg, bool isKill, int FI, 185 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, 186 int64_t Offset) const { 187 DebugLoc DL; 188 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore); 189 190 unsigned Opc = 0; 191 192 if (Mips::GPR32RegClass.hasSubClassEq(RC)) 193 Opc = Mips::SW; 194 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) 195 Opc = Mips::SD; 196 else if (Mips::ACC64RegClass.hasSubClassEq(RC)) 197 Opc = Mips::STORE_ACC64; 198 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC)) 199 Opc = Mips::STORE_ACC64DSP; 200 else if (Mips::ACC128RegClass.hasSubClassEq(RC)) 201 Opc = Mips::STORE_ACC128; 202 else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) 203 Opc = Mips::STORE_CCOND_DSP; 204 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) 205 Opc = Mips::SWC1; 206 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) 207 Opc = Mips::SDC1; 208 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) 209 Opc = Mips::SDC164; 210 else if (RC->hasType(MVT::v16i8)) 211 Opc = Mips::ST_B; 212 else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16)) 213 Opc = Mips::ST_H; 214 else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32)) 215 Opc = Mips::ST_W; 216 else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64)) 217 Opc = Mips::ST_D; 218 else if (Mips::LO32RegClass.hasSubClassEq(RC)) 219 Opc = Mips::SW; 220 else if (Mips::LO64RegClass.hasSubClassEq(RC)) 221 Opc = Mips::SD; 222 else if (Mips::HI32RegClass.hasSubClassEq(RC)) 223 Opc = Mips::SW; 224 else if (Mips::HI64RegClass.hasSubClassEq(RC)) 225 Opc = Mips::SD; 226 227 // Hi, Lo are normally caller save but they are callee save 228 // for interrupt handling. 229 const Function *Func = MBB.getParent()->getFunction(); 230 if (Func->hasFnAttribute("interrupt")) { 231 if (Mips::HI32RegClass.hasSubClassEq(RC)) { 232 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0); 233 SrcReg = Mips::K0; 234 } else if (Mips::HI64RegClass.hasSubClassEq(RC)) { 235 BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64); 236 SrcReg = Mips::K0_64; 237 } else if (Mips::LO32RegClass.hasSubClassEq(RC)) { 238 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0); 239 SrcReg = Mips::K0; 240 } else if (Mips::LO64RegClass.hasSubClassEq(RC)) { 241 BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64); 242 SrcReg = Mips::K0_64; 243 } 244 } 245 246 assert(Opc && "Register class not handled!"); 247 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) 248 .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO); 249 } 250 251 void MipsSEInstrInfo:: 252 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 253 unsigned DestReg, int FI, const TargetRegisterClass *RC, 254 const TargetRegisterInfo *TRI, int64_t Offset) const { 255 DebugLoc DL; 256 if (I != MBB.end()) DL = I->getDebugLoc(); 257 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad); 258 unsigned Opc = 0; 259 260 const Function *Func = MBB.getParent()->getFunction(); 261 bool ReqIndirectLoad = Func->hasFnAttribute("interrupt") && 262 (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 || 263 DestReg == Mips::HI0 || DestReg == Mips::HI0_64); 264 265 if (Mips::GPR32RegClass.hasSubClassEq(RC)) 266 Opc = Mips::LW; 267 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) 268 Opc = Mips::LD; 269 else if (Mips::ACC64RegClass.hasSubClassEq(RC)) 270 Opc = Mips::LOAD_ACC64; 271 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC)) 272 Opc = Mips::LOAD_ACC64DSP; 273 else if (Mips::ACC128RegClass.hasSubClassEq(RC)) 274 Opc = Mips::LOAD_ACC128; 275 else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) 276 Opc = Mips::LOAD_CCOND_DSP; 277 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) 278 Opc = Mips::LWC1; 279 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) 280 Opc = Mips::LDC1; 281 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) 282 Opc = Mips::LDC164; 283 else if (RC->hasType(MVT::v16i8)) 284 Opc = Mips::LD_B; 285 else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16)) 286 Opc = Mips::LD_H; 287 else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32)) 288 Opc = Mips::LD_W; 289 else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64)) 290 Opc = Mips::LD_D; 291 else if (Mips::HI32RegClass.hasSubClassEq(RC)) 292 Opc = Mips::LW; 293 else if (Mips::HI64RegClass.hasSubClassEq(RC)) 294 Opc = Mips::LD; 295 else if (Mips::LO32RegClass.hasSubClassEq(RC)) 296 Opc = Mips::LW; 297 else if (Mips::LO64RegClass.hasSubClassEq(RC)) 298 Opc = Mips::LD; 299 300 assert(Opc && "Register class not handled!"); 301 302 if (!ReqIndirectLoad) 303 BuildMI(MBB, I, DL, get(Opc), DestReg) 304 .addFrameIndex(FI) 305 .addImm(Offset) 306 .addMemOperand(MMO); 307 else { 308 // Load HI/LO through K0. Notably the DestReg is encoded into the 309 // instruction itself. 310 unsigned Reg = Mips::K0; 311 unsigned LdOp = Mips::MTLO; 312 if (DestReg == Mips::HI0) 313 LdOp = Mips::MTHI; 314 315 if (Subtarget.getABI().ArePtrs64bit()) { 316 Reg = Mips::K0_64; 317 if (DestReg == Mips::HI0_64) 318 LdOp = Mips::MTHI64; 319 else 320 LdOp = Mips::MTLO64; 321 } 322 323 BuildMI(MBB, I, DL, get(Opc), Reg) 324 .addFrameIndex(FI) 325 .addImm(Offset) 326 .addMemOperand(MMO); 327 BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg); 328 } 329 } 330 331 bool MipsSEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { 332 MachineBasicBlock &MBB = *MI.getParent(); 333 bool isMicroMips = Subtarget.inMicroMipsMode(); 334 unsigned Opc; 335 336 switch (MI.getDesc().getOpcode()) { 337 default: 338 return false; 339 case Mips::RetRA: 340 expandRetRA(MBB, MI); 341 break; 342 case Mips::ERet: 343 expandERet(MBB, MI); 344 break; 345 case Mips::PseudoMFHI: 346 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; 347 expandPseudoMFHiLo(MBB, MI, Opc); 348 break; 349 case Mips::PseudoMFLO: 350 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; 351 expandPseudoMFHiLo(MBB, MI, Opc); 352 break; 353 case Mips::PseudoMFHI64: 354 expandPseudoMFHiLo(MBB, MI, Mips::MFHI64); 355 break; 356 case Mips::PseudoMFLO64: 357 expandPseudoMFHiLo(MBB, MI, Mips::MFLO64); 358 break; 359 case Mips::PseudoMTLOHI: 360 expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false); 361 break; 362 case Mips::PseudoMTLOHI64: 363 expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false); 364 break; 365 case Mips::PseudoMTLOHI_DSP: 366 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true); 367 break; 368 case Mips::PseudoCVT_S_W: 369 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false); 370 break; 371 case Mips::PseudoCVT_D32_W: 372 expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false); 373 break; 374 case Mips::PseudoCVT_S_L: 375 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true); 376 break; 377 case Mips::PseudoCVT_D64_W: 378 expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true); 379 break; 380 case Mips::PseudoCVT_D64_L: 381 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true); 382 break; 383 case Mips::BuildPairF64: 384 expandBuildPairF64(MBB, MI, false); 385 break; 386 case Mips::BuildPairF64_64: 387 expandBuildPairF64(MBB, MI, true); 388 break; 389 case Mips::ExtractElementF64: 390 expandExtractElementF64(MBB, MI, false); 391 break; 392 case Mips::ExtractElementF64_64: 393 expandExtractElementF64(MBB, MI, true); 394 break; 395 case Mips::MIPSeh_return32: 396 case Mips::MIPSeh_return64: 397 expandEhReturn(MBB, MI); 398 break; 399 } 400 401 MBB.erase(MI); 402 return true; 403 } 404 405 /// getOppositeBranchOpc - Return the inverse of the specified 406 /// opcode, e.g. turning BEQ to BNE. 407 unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const { 408 switch (Opc) { 409 default: llvm_unreachable("Illegal opcode!"); 410 case Mips::BEQ: return Mips::BNE; 411 case Mips::BNE: return Mips::BEQ; 412 case Mips::BGTZ: return Mips::BLEZ; 413 case Mips::BGEZ: return Mips::BLTZ; 414 case Mips::BLTZ: return Mips::BGEZ; 415 case Mips::BLEZ: return Mips::BGTZ; 416 case Mips::BEQ64: return Mips::BNE64; 417 case Mips::BNE64: return Mips::BEQ64; 418 case Mips::BGTZ64: return Mips::BLEZ64; 419 case Mips::BGEZ64: return Mips::BLTZ64; 420 case Mips::BLTZ64: return Mips::BGEZ64; 421 case Mips::BLEZ64: return Mips::BGTZ64; 422 case Mips::BC1T: return Mips::BC1F; 423 case Mips::BC1F: return Mips::BC1T; 424 case Mips::BEQZC_MM: return Mips::BNEZC_MM; 425 case Mips::BNEZC_MM: return Mips::BEQZC_MM; 426 case Mips::BEQZC: return Mips::BNEZC; 427 case Mips::BNEZC: return Mips::BEQZC; 428 case Mips::BEQC: return Mips::BNEC; 429 case Mips::BNEC: return Mips::BEQC; 430 case Mips::BGTZC: return Mips::BLEZC; 431 case Mips::BGEZC: return Mips::BLTZC; 432 case Mips::BLTZC: return Mips::BGEZC; 433 case Mips::BLEZC: return Mips::BGTZC; 434 } 435 } 436 437 /// Adjust SP by Amount bytes. 438 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount, 439 MachineBasicBlock &MBB, 440 MachineBasicBlock::iterator I) const { 441 MipsABIInfo ABI = Subtarget.getABI(); 442 DebugLoc DL; 443 unsigned ADDiu = ABI.GetPtrAddiuOp(); 444 445 if (Amount == 0) 446 return; 447 448 if (isInt<16>(Amount)) { 449 // addi sp, sp, amount 450 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount); 451 } else { 452 // For numbers which are not 16bit integers we synthesize Amount inline 453 // then add or subtract it from sp. 454 unsigned Opc = ABI.GetPtrAdduOp(); 455 if (Amount < 0) { 456 Opc = ABI.GetPtrSubuOp(); 457 Amount = -Amount; 458 } 459 unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr); 460 BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill); 461 } 462 } 463 464 /// This function generates the sequence of instructions needed to get the 465 /// result of adding register REG and immediate IMM. 466 unsigned MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB, 467 MachineBasicBlock::iterator II, 468 const DebugLoc &DL, 469 unsigned *NewImm) const { 470 MipsAnalyzeImmediate AnalyzeImm; 471 const MipsSubtarget &STI = Subtarget; 472 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); 473 unsigned Size = STI.isABI_N64() ? 64 : 32; 474 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi; 475 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 476 const TargetRegisterClass *RC = STI.isABI_N64() ? 477 &Mips::GPR64RegClass : &Mips::GPR32RegClass; 478 bool LastInstrIsADDiu = NewImm; 479 480 const MipsAnalyzeImmediate::InstSeq &Seq = 481 AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu); 482 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin(); 483 484 assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1))); 485 486 // The first instruction can be a LUi, which is different from other 487 // instructions (ADDiu, ORI and SLL) in that it does not have a register 488 // operand. 489 unsigned Reg = RegInfo.createVirtualRegister(RC); 490 491 if (Inst->Opc == LUi) 492 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd)); 493 else 494 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg) 495 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 496 497 // Build the remaining instructions in Seq. 498 for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst) 499 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill) 500 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 501 502 if (LastInstrIsADDiu) 503 *NewImm = Inst->ImmOpnd; 504 505 return Reg; 506 } 507 508 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const { 509 return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ || 510 Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ || 511 Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || 512 Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || 513 Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B || 514 Opc == Mips::J || Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM || 515 Opc == Mips::BEQC || Opc == Mips::BNEC || Opc == Mips::BLTC || 516 Opc == Mips::BGEC || Opc == Mips::BLTUC || Opc == Mips::BGEUC || 517 Opc == Mips::BGTZC || Opc == Mips::BLEZC || Opc == Mips::BGEZC || 518 Opc == Mips::BLTZC || Opc == Mips::BEQZC || Opc == Mips::BNEZC || 519 Opc == Mips::BC) ? Opc : 0; 520 } 521 522 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB, 523 MachineBasicBlock::iterator I) const { 524 if (Subtarget.isGP64bit()) 525 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64)) 526 .addReg(Mips::RA_64); 527 else 528 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn)).addReg(Mips::RA); 529 } 530 531 void MipsSEInstrInfo::expandERet(MachineBasicBlock &MBB, 532 MachineBasicBlock::iterator I) const { 533 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET)); 534 } 535 536 std::pair<bool, bool> 537 MipsSEInstrInfo::compareOpndSize(unsigned Opc, 538 const MachineFunction &MF) const { 539 const MCInstrDesc &Desc = get(Opc); 540 assert(Desc.NumOperands == 2 && "Unary instruction expected."); 541 const MipsRegisterInfo *RI = &getRegisterInfo(); 542 unsigned DstRegSize = getRegClass(Desc, 0, RI, MF)->getSize(); 543 unsigned SrcRegSize = getRegClass(Desc, 1, RI, MF)->getSize(); 544 545 return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize); 546 } 547 548 void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB, 549 MachineBasicBlock::iterator I, 550 unsigned NewOpc) const { 551 BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg()); 552 } 553 554 void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB, 555 MachineBasicBlock::iterator I, 556 unsigned LoOpc, 557 unsigned HiOpc, 558 bool HasExplicitDef) const { 559 // Expand 560 // lo_hi pseudomtlohi $gpr0, $gpr1 561 // to these two instructions: 562 // mtlo $gpr0 563 // mthi $gpr1 564 565 DebugLoc DL = I->getDebugLoc(); 566 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); 567 MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc)); 568 MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc)); 569 570 // Add lo/hi registers if the mtlo/hi instructions created have explicit 571 // def registers. 572 if (HasExplicitDef) { 573 unsigned DstReg = I->getOperand(0).getReg(); 574 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 575 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); 576 LoInst.addReg(DstLo, RegState::Define); 577 HiInst.addReg(DstHi, RegState::Define); 578 } 579 580 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill())); 581 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill())); 582 } 583 584 void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB, 585 MachineBasicBlock::iterator I, 586 unsigned CvtOpc, unsigned MovOpc, 587 bool IsI64) const { 588 const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc); 589 const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1); 590 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg; 591 unsigned KillSrc = getKillRegState(Src.isKill()); 592 DebugLoc DL = I->getDebugLoc(); 593 bool DstIsLarger, SrcIsLarger; 594 595 std::tie(DstIsLarger, SrcIsLarger) = 596 compareOpndSize(CvtOpc, *MBB.getParent()); 597 598 if (DstIsLarger) 599 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 600 601 if (SrcIsLarger) 602 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 603 604 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc); 605 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill); 606 } 607 608 void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB, 609 MachineBasicBlock::iterator I, 610 bool FP64) const { 611 unsigned DstReg = I->getOperand(0).getReg(); 612 unsigned SrcReg = I->getOperand(1).getReg(); 613 unsigned N = I->getOperand(2).getImm(); 614 DebugLoc dl = I->getDebugLoc(); 615 616 assert(N < 2 && "Invalid immediate"); 617 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo; 618 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx); 619 620 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload 621 // in MipsSEFrameLowering.cpp. 622 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2())); 623 624 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload 625 // in MipsSEFrameLowering.cpp. 626 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg())); 627 628 if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) { 629 // FIXME: Strictly speaking MFHC1 only reads the top 32-bits however, we 630 // claim to read the whole 64-bits as part of a white lie used to 631 // temporarily work around a widespread bug in the -mfp64 support. 632 // The problem is that none of the 32-bit fpu ops mention the fact 633 // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that 634 // requires a major overhaul of the FPU implementation which can't 635 // be done right now due to time constraints. 636 // MFHC1 is one of two instructions that are affected since they are 637 // the only instructions that don't read the lower 32-bits. 638 // We therefore pretend that it reads the bottom 32-bits to 639 // artificially create a dependency and prevent the scheduler 640 // changing the behaviour of the code. 641 BuildMI(MBB, I, dl, get(FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32), DstReg) 642 .addReg(SrcReg); 643 } else 644 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg); 645 } 646 647 void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB, 648 MachineBasicBlock::iterator I, 649 bool FP64) const { 650 unsigned DstReg = I->getOperand(0).getReg(); 651 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); 652 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1); 653 DebugLoc dl = I->getDebugLoc(); 654 const TargetRegisterInfo &TRI = getRegisterInfo(); 655 656 // When mthc1 is available, use: 657 // mtc1 Lo, $fp 658 // mthc1 Hi, $fp 659 // 660 // Otherwise, for O32 FPXX ABI: 661 // spill + reload via ldc1 662 // This case is handled by the frame lowering code. 663 // 664 // Otherwise, for FP32: 665 // mtc1 Lo, $fp 666 // mtc1 Hi, $fp + 1 667 // 668 // The case where dmtc1 is available doesn't need to be handled here 669 // because it never creates a BuildPairF64 node. 670 671 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload 672 // in MipsSEFrameLowering.cpp. 673 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2())); 674 675 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload 676 // in MipsSEFrameLowering.cpp. 677 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg())); 678 679 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo)) 680 .addReg(LoReg); 681 682 if (Subtarget.hasMTHC1()) { 683 // FIXME: The .addReg(DstReg) is a white lie used to temporarily work 684 // around a widespread bug in the -mfp64 support. 685 // The problem is that none of the 32-bit fpu ops mention the fact 686 // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that 687 // requires a major overhaul of the FPU implementation which can't 688 // be done right now due to time constraints. 689 // MTHC1 is one of two instructions that are affected since they are 690 // the only instructions that don't read the lower 32-bits. 691 // We therefore pretend that it reads the bottom 32-bits to 692 // artificially create a dependency and prevent the scheduler 693 // changing the behaviour of the code. 694 BuildMI(MBB, I, dl, get(FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32), DstReg) 695 .addReg(DstReg) 696 .addReg(HiReg); 697 } else if (Subtarget.isABI_FPXX()) 698 llvm_unreachable("BuildPairF64 not expanded in frame lowering code!"); 699 else 700 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi)) 701 .addReg(HiReg); 702 } 703 704 void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB, 705 MachineBasicBlock::iterator I) const { 706 // This pseudo instruction is generated as part of the lowering of 707 // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and 708 // indirect jump to TargetReg 709 MipsABIInfo ABI = Subtarget.getABI(); 710 unsigned ADDU = ABI.GetPtrAdduOp(); 711 unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP; 712 unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA; 713 unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9; 714 unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; 715 unsigned OffsetReg = I->getOperand(0).getReg(); 716 unsigned TargetReg = I->getOperand(1).getReg(); 717 718 // addu $ra, $v0, $zero 719 // addu $sp, $sp, $v1 720 // jr $ra (via RetRA) 721 const TargetMachine &TM = MBB.getParent()->getTarget(); 722 if (TM.isPositionIndependent()) 723 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), T9) 724 .addReg(TargetReg) 725 .addReg(ZERO); 726 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA) 727 .addReg(TargetReg) 728 .addReg(ZERO); 729 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg); 730 expandRetRA(MBB, I); 731 } 732 733 const MipsInstrInfo *llvm::createMipsSEInstrInfo(const MipsSubtarget &STI) { 734 return new MipsSEInstrInfo(STI); 735 } 736
