| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyFrameLowering.cpp | 159 unsigned OffsetReg = MRI.createVirtualRegister(PtrRC);
160 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg)
165 .addReg(OffsetReg);
200 unsigned OffsetReg = MRI.createVirtualRegister(PtrRC);
202 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg)
209 .addReg(OffsetReg);
|
| /external/llvm/lib/Target/AMDGPU/ |
| R600InstrInfo.h | 41 unsigned OffsetReg,
47 unsigned OffsetReg,
246 unsigned OffsetReg) const;
254 unsigned OffsetReg) const;
|
| R600InstrInfo.cpp | [all...] |
| SIRegisterInfo.cpp | 293 unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
295 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg)
299 .addReg(OffsetReg, RegState::Kill)
346 unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
351 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg)
355 .addReg(OffsetReg, RegState::Kill)
[all...] |
| /external/llvm/lib/Target/Lanai/AsmParser/ |
| LanaiAsmParser.cpp | 115 unsigned OffsetReg;
161 return Mem.OffsetReg;
600 Op->Mem.OffsetReg = 0;
608 unsigned OffsetReg = Op->getReg();
612 Op->Mem.OffsetReg = OffsetReg;
624 Op->Mem.OffsetReg = 0;
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 528 unsigned OffsetReg = 0;
532 OffsetReg = MI->getOperand(2).getReg();
567 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!");
570 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) |
[all...] |
| Thumb2InstrInfo.cpp | 540 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
541 if (OffsetReg != 0) {
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 422 unsigned OffsetReg = 0;
425 OffsetReg = MI->getOperand(2).getReg();
453 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!");
456 MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
|
| Thumb2InstrInfo.cpp | 472 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
473 if (OffsetReg != 0) {
|
| /external/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 212 unsigned OffsetReg;
271 return Mem.OffsetReg;
437 unsigned offsetReg = Op->getReg();
440 Op->Mem.OffsetReg = offsetReg;
449 Op->Mem.OffsetReg = Sparc::G0; // always 0
461 Op->Mem.OffsetReg = 0;
[all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceTargetLoweringARM32.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonOptAddrMode.cpp | 147 unsigned OffsetReg = MI->getOperand(2).getReg();
152 if (OffsetReg == RR.Reg) {
|
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 707 // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
715 unsigned OffsetReg = I->getOperand(0).getReg();
729 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg);
|
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 59 unsigned OffsetReg;
66 OffsetReg(0), Shift(0), Offset(0), GV(nullptr) { Base.Reg = 0; }
82 OffsetReg = Reg;
85 return OffsetReg;
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
