| /art/compiler/utils/mips/ |
| assembler_mips.h | 542 // Mtc1(), Mthc1(), MoveToFpuHigh(), Lwc1(). Even if you need two Mtc1()'s or two
543 // Lwc1()'s to load a pair of 32-bit FPRs and these loads do not interfere with one
556 void Lwc1(FRegister ft, Register rs, uint16_t imm16);
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| assembler_mips_test.cc | 832 TEST_F(AssemblerMIPSTest, Lwc1) {
833 DriverStr(RepeatFRIb(&mips::MipsAssembler::Lwc1, -16, "lwc1 ${reg1}, {imm}(${reg2})"), "Lwc1");
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| assembler_mips.cc | [all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64.h | 660 void Lwc1(FpuRegister ft, GpuRegister rs, uint16_t imm16);
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| assembler_mips64_test.cc | 751 TEST_F(AssemblerMIPS64Test, Lwc1) {
752 DriverStr(RepeatFRIb(&mips64::Mips64Assembler::Lwc1, -16, "lwc1 ${reg1}, {imm}(${reg2})"),
753 "lwc1");
[all...] |
| assembler_mips64.cc | [all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceInstMIPS32.h | 231 Lwc1,
629 "lwc1"
[all...] |
