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    Searched refs:MI_LOAD_REGISTER_IMM (Results 1 - 14 of 14) sorted by null

  /external/mesa3d/src/mesa/drivers/dri/i965/
gen7_l3_state.c 123 OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
151 OUT_BATCH(MI_LOAD_REGISTER_IMM | (7 - 2));
183 OUT_BATCH(MI_LOAD_REGISTER_IMM | (5 - 2));
brw_compute.c 58 OUT_BATCH(MI_LOAD_REGISTER_IMM | (7 - 2));
hsw_sol.c 176 OUT_BATCH(MI_LOAD_REGISTER_IMM | (1 + 2 * BRW_MAX_XFB_STREAMS - 2));
brw_draw.c 211 OUT_BATCH(MI_LOAD_REGISTER_IMM | (9 - 2));
251 OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
intel_batchbuffer.c 616 OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
631 OUT_BATCH(MI_LOAD_REGISTER_IMM | (5 - 2));
gen8_depth_state.c 351 OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
brw_state_upload.c 403 OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
intel_screen.c     [all...]
intel_blit.c 129 OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
    [all...]
brw_defines.h     [all...]
  /external/mesa3d/src/gallium/drivers/ilo/core/
ilo_builder_mi.h 89 dw[0] = GEN6_MI_CMD(MI_LOAD_REGISTER_IMM) | (cmd_len - 2);
  /external/mesa3d/src/mesa/drivers/dri/i915/
intel_reg.h 40 #define MI_LOAD_REGISTER_IMM (CMD_MI | (0x22 << 23))
  /external/mesa3d/src/intel/vulkan/
genX_gpu_memcpy.c 185 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), load) {
genX_cmd_buffer.c 47 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
    [all...]

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