1 /* 2 * Copyright 2003 VMware, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sublicense, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #include <errno.h> 27 #include <time.h> 28 #include <unistd.h> 29 #include "main/context.h" 30 #include "main/framebuffer.h" 31 #include "main/renderbuffer.h" 32 #include "main/texobj.h" 33 #include "main/hash.h" 34 #include "main/fbobject.h" 35 #include "main/version.h" 36 #include "swrast/s_renderbuffer.h" 37 #include "util/ralloc.h" 38 #include "brw_shader.h" 39 #include "compiler/nir/nir.h" 40 41 #include "utils.h" 42 #include "xmlpool.h" 43 44 static const __DRIconfigOptionsExtension brw_config_options = { 45 .base = { __DRI_CONFIG_OPTIONS, 1 }, 46 .xml = 47 DRI_CONF_BEGIN 48 DRI_CONF_SECTION_PERFORMANCE 49 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_ALWAYS_SYNC) 50 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED, 51 * DRI_CONF_BO_REUSE_ALL 52 */ 53 DRI_CONF_OPT_BEGIN_V(bo_reuse, enum, 1, "0:1") 54 DRI_CONF_DESC_BEGIN(en, "Buffer object reuse") 55 DRI_CONF_ENUM(0, "Disable buffer object reuse") 56 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects") 57 DRI_CONF_DESC_END 58 DRI_CONF_OPT_END 59 60 DRI_CONF_OPT_BEGIN_B(hiz, "true") 61 DRI_CONF_DESC(en, "Enable Hierarchical Z on gen6+") 62 DRI_CONF_OPT_END 63 DRI_CONF_SECTION_END 64 65 DRI_CONF_SECTION_QUALITY 66 DRI_CONF_FORCE_S3TC_ENABLE("false") 67 68 DRI_CONF_PRECISE_TRIG("false") 69 70 DRI_CONF_OPT_BEGIN(clamp_max_samples, int, -1) 71 DRI_CONF_DESC(en, "Clamp the value of GL_MAX_SAMPLES to the " 72 "given integer. If negative, then do not clamp.") 73 DRI_CONF_OPT_END 74 DRI_CONF_SECTION_END 75 76 DRI_CONF_SECTION_DEBUG 77 DRI_CONF_NO_RAST("false") 78 DRI_CONF_ALWAYS_FLUSH_BATCH("false") 79 DRI_CONF_ALWAYS_FLUSH_CACHE("false") 80 DRI_CONF_DISABLE_THROTTLING("false") 81 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false") 82 DRI_CONF_FORCE_GLSL_VERSION(0) 83 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false") 84 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false") 85 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false") 86 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false") 87 88 DRI_CONF_OPT_BEGIN_B(shader_precompile, "true") 89 DRI_CONF_DESC(en, "Perform code generation at shader link time.") 90 DRI_CONF_OPT_END 91 DRI_CONF_SECTION_END 92 93 DRI_CONF_SECTION_MISCELLANEOUS 94 DRI_CONF_GLSL_ZERO_INIT("false") 95 DRI_CONF_SECTION_END 96 DRI_CONF_END 97 }; 98 99 #include "intel_batchbuffer.h" 100 #include "intel_buffers.h" 101 #include "intel_bufmgr.h" 102 #include "intel_fbo.h" 103 #include "intel_mipmap_tree.h" 104 #include "intel_screen.h" 105 #include "intel_tex.h" 106 #include "intel_image.h" 107 108 #include "brw_context.h" 109 110 #include "i915_drm.h" 111 112 /** 113 * For debugging purposes, this returns a time in seconds. 114 */ 115 double 116 get_time(void) 117 { 118 struct timespec tp; 119 120 clock_gettime(CLOCK_MONOTONIC, &tp); 121 122 return tp.tv_sec + tp.tv_nsec / 1000000000.0; 123 } 124 125 void 126 aub_dump_bmp(struct gl_context *ctx) 127 { 128 struct gl_framebuffer *fb = ctx->DrawBuffer; 129 130 for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) { 131 struct intel_renderbuffer *irb = 132 intel_renderbuffer(fb->_ColorDrawBuffers[i]); 133 134 if (irb && irb->mt) { 135 enum aub_dump_bmp_format format; 136 137 switch (irb->Base.Base.Format) { 138 case MESA_FORMAT_B8G8R8A8_UNORM: 139 case MESA_FORMAT_B8G8R8X8_UNORM: 140 format = AUB_DUMP_BMP_FORMAT_ARGB_8888; 141 break; 142 default: 143 continue; 144 } 145 146 drm_intel_gem_bo_aub_dump_bmp(irb->mt->bo, 147 irb->draw_x, 148 irb->draw_y, 149 irb->Base.Base.Width, 150 irb->Base.Base.Height, 151 format, 152 irb->mt->pitch, 153 0); 154 } 155 } 156 } 157 158 static const __DRItexBufferExtension intelTexBufferExtension = { 159 .base = { __DRI_TEX_BUFFER, 3 }, 160 161 .setTexBuffer = intelSetTexBuffer, 162 .setTexBuffer2 = intelSetTexBuffer2, 163 .releaseTexBuffer = NULL, 164 }; 165 166 static void 167 intel_dri2_flush_with_flags(__DRIcontext *cPriv, 168 __DRIdrawable *dPriv, 169 unsigned flags, 170 enum __DRI2throttleReason reason) 171 { 172 struct brw_context *brw = cPriv->driverPrivate; 173 174 if (!brw) 175 return; 176 177 struct gl_context *ctx = &brw->ctx; 178 179 FLUSH_VERTICES(ctx, 0); 180 181 if (flags & __DRI2_FLUSH_DRAWABLE) 182 intel_resolve_for_dri2_flush(brw, dPriv); 183 184 if (reason == __DRI2_THROTTLE_SWAPBUFFER) 185 brw->need_swap_throttle = true; 186 if (reason == __DRI2_THROTTLE_FLUSHFRONT) 187 brw->need_flush_throttle = true; 188 189 intel_batchbuffer_flush(brw); 190 191 if (INTEL_DEBUG & DEBUG_AUB) { 192 aub_dump_bmp(ctx); 193 } 194 } 195 196 /** 197 * Provides compatibility with loaders that only support the older (version 198 * 1-3) flush interface. 199 * 200 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13. 201 */ 202 static void 203 intel_dri2_flush(__DRIdrawable *drawable) 204 { 205 intel_dri2_flush_with_flags(drawable->driContextPriv, drawable, 206 __DRI2_FLUSH_DRAWABLE, 207 __DRI2_THROTTLE_SWAPBUFFER); 208 } 209 210 static const struct __DRI2flushExtensionRec intelFlushExtension = { 211 .base = { __DRI2_FLUSH, 4 }, 212 213 .flush = intel_dri2_flush, 214 .invalidate = dri2InvalidateDrawable, 215 .flush_with_flags = intel_dri2_flush_with_flags, 216 }; 217 218 static struct intel_image_format intel_image_formats[] = { 219 { __DRI_IMAGE_FOURCC_ARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, 220 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } }, 221 222 { __DRI_IMAGE_FOURCC_ABGR8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, 223 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } }, 224 225 { __DRI_IMAGE_FOURCC_SARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1, 226 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8, 4 } } }, 227 228 { __DRI_IMAGE_FOURCC_XRGB8888, __DRI_IMAGE_COMPONENTS_RGB, 1, 229 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888, 4 }, } }, 230 231 { __DRI_IMAGE_FOURCC_XBGR8888, __DRI_IMAGE_COMPONENTS_RGB, 1, 232 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888, 4 }, } }, 233 234 { __DRI_IMAGE_FOURCC_ARGB1555, __DRI_IMAGE_COMPONENTS_RGBA, 1, 235 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555, 2 } } }, 236 237 { __DRI_IMAGE_FOURCC_RGB565, __DRI_IMAGE_COMPONENTS_RGB, 1, 238 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565, 2 } } }, 239 240 { __DRI_IMAGE_FOURCC_R8, __DRI_IMAGE_COMPONENTS_R, 1, 241 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } }, 242 243 { __DRI_IMAGE_FOURCC_GR88, __DRI_IMAGE_COMPONENTS_RG, 1, 244 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, } }, 245 246 { __DRI_IMAGE_FOURCC_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, 247 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 248 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 }, 249 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 } } }, 250 251 { __DRI_IMAGE_FOURCC_YUV411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, 252 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 253 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 254 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, 255 256 { __DRI_IMAGE_FOURCC_YUV420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, 257 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 258 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 }, 259 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 } } }, 260 261 { __DRI_IMAGE_FOURCC_YUV422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, 262 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 263 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 264 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, 265 266 { __DRI_IMAGE_FOURCC_YUV444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, 267 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 268 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 269 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, 270 271 { __DRI_IMAGE_FOURCC_YVU410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, 272 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 273 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 }, 274 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 } } }, 275 276 { __DRI_IMAGE_FOURCC_YVU411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, 277 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 278 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 279 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, 280 281 { __DRI_IMAGE_FOURCC_YVU420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, 282 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 283 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 }, 284 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 } } }, 285 286 { __DRI_IMAGE_FOURCC_YVU422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, 287 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 288 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 289 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, 290 291 { __DRI_IMAGE_FOURCC_YVU444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, 292 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 293 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 294 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 } } }, 295 296 { __DRI_IMAGE_FOURCC_NV12, __DRI_IMAGE_COMPONENTS_Y_UV, 2, 297 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 298 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88, 2 } } }, 299 300 { __DRI_IMAGE_FOURCC_NV16, __DRI_IMAGE_COMPONENTS_Y_UV, 2, 301 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, 302 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88, 2 } } }, 303 304 /* For YUYV buffers, we set up two overlapping DRI images and treat 305 * them as planar buffers in the compositors. Plane 0 is GR88 and 306 * samples YU or YV pairs and places Y into the R component, while 307 * plane 1 is ARGB and samples YUYV clusters and places pairs and 308 * places U into the G component and V into A. This lets the 309 * texture sampler interpolate the Y components correctly when 310 * sampling from plane 0, and interpolate U and V correctly when 311 * sampling from plane 1. */ 312 { __DRI_IMAGE_FOURCC_YUYV, __DRI_IMAGE_COMPONENTS_Y_XUXV, 2, 313 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, 314 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } } 315 }; 316 317 static void 318 intel_image_warn_if_unaligned(__DRIimage *image, const char *func) 319 { 320 uint32_t tiling, swizzle; 321 drm_intel_bo_get_tiling(image->bo, &tiling, &swizzle); 322 323 if (tiling != I915_TILING_NONE && (image->offset & 0xfff)) { 324 _mesa_warning(NULL, "%s: offset 0x%08x not on tile boundary", 325 func, image->offset); 326 } 327 } 328 329 static struct intel_image_format * 330 intel_image_format_lookup(int fourcc) 331 { 332 struct intel_image_format *f = NULL; 333 334 for (unsigned i = 0; i < ARRAY_SIZE(intel_image_formats); i++) { 335 if (intel_image_formats[i].fourcc == fourcc) { 336 f = &intel_image_formats[i]; 337 break; 338 } 339 } 340 341 return f; 342 } 343 344 static boolean intel_lookup_fourcc(int dri_format, int *fourcc) 345 { 346 for (unsigned i = 0; i < ARRAY_SIZE(intel_image_formats); i++) { 347 if (intel_image_formats[i].planes[0].dri_format == dri_format) { 348 *fourcc = intel_image_formats[i].fourcc; 349 return true; 350 } 351 } 352 return false; 353 } 354 355 static __DRIimage * 356 intel_allocate_image(int dri_format, void *loaderPrivate) 357 { 358 __DRIimage *image; 359 360 image = calloc(1, sizeof *image); 361 if (image == NULL) 362 return NULL; 363 364 image->dri_format = dri_format; 365 image->offset = 0; 366 367 image->format = driImageFormatToGLFormat(dri_format); 368 if (dri_format != __DRI_IMAGE_FORMAT_NONE && 369 image->format == MESA_FORMAT_NONE) { 370 free(image); 371 return NULL; 372 } 373 374 image->internal_format = _mesa_get_format_base_format(image->format); 375 image->data = loaderPrivate; 376 377 return image; 378 } 379 380 /** 381 * Sets up a DRIImage structure to point to a slice out of a miptree. 382 */ 383 static void 384 intel_setup_image_from_mipmap_tree(struct brw_context *brw, __DRIimage *image, 385 struct intel_mipmap_tree *mt, GLuint level, 386 GLuint zoffset) 387 { 388 intel_miptree_make_shareable(brw, mt); 389 390 intel_miptree_check_level_layer(mt, level, zoffset); 391 392 image->width = minify(mt->physical_width0, level - mt->first_level); 393 image->height = minify(mt->physical_height0, level - mt->first_level); 394 image->pitch = mt->pitch; 395 396 image->offset = intel_miptree_get_tile_offsets(mt, level, zoffset, 397 &image->tile_x, 398 &image->tile_y); 399 400 drm_intel_bo_unreference(image->bo); 401 image->bo = mt->bo; 402 drm_intel_bo_reference(mt->bo); 403 } 404 405 static __DRIimage * 406 intel_create_image_from_name(__DRIscreen *dri_screen, 407 int width, int height, int format, 408 int name, int pitch, void *loaderPrivate) 409 { 410 struct intel_screen *screen = dri_screen->driverPrivate; 411 __DRIimage *image; 412 int cpp; 413 414 image = intel_allocate_image(format, loaderPrivate); 415 if (image == NULL) 416 return NULL; 417 418 if (image->format == MESA_FORMAT_NONE) 419 cpp = 1; 420 else 421 cpp = _mesa_get_format_bytes(image->format); 422 423 image->width = width; 424 image->height = height; 425 image->pitch = pitch * cpp; 426 image->bo = drm_intel_bo_gem_create_from_name(screen->bufmgr, "image", 427 name); 428 if (!image->bo) { 429 free(image); 430 return NULL; 431 } 432 433 return image; 434 } 435 436 static __DRIimage * 437 intel_create_image_from_renderbuffer(__DRIcontext *context, 438 int renderbuffer, void *loaderPrivate) 439 { 440 __DRIimage *image; 441 struct brw_context *brw = context->driverPrivate; 442 struct gl_context *ctx = &brw->ctx; 443 struct gl_renderbuffer *rb; 444 struct intel_renderbuffer *irb; 445 446 rb = _mesa_lookup_renderbuffer(ctx, renderbuffer); 447 if (!rb) { 448 _mesa_error(ctx, GL_INVALID_OPERATION, "glRenderbufferExternalMESA"); 449 return NULL; 450 } 451 452 irb = intel_renderbuffer(rb); 453 intel_miptree_make_shareable(brw, irb->mt); 454 image = calloc(1, sizeof *image); 455 if (image == NULL) 456 return NULL; 457 458 image->internal_format = rb->InternalFormat; 459 image->format = rb->Format; 460 image->offset = 0; 461 image->data = loaderPrivate; 462 drm_intel_bo_unreference(image->bo); 463 image->bo = irb->mt->bo; 464 drm_intel_bo_reference(irb->mt->bo); 465 image->width = rb->Width; 466 image->height = rb->Height; 467 image->pitch = irb->mt->pitch; 468 image->dri_format = driGLFormatToImageFormat(image->format); 469 image->has_depthstencil = irb->mt->stencil_mt? true : false; 470 471 rb->NeedsFinishRenderTexture = true; 472 return image; 473 } 474 475 static __DRIimage * 476 intel_create_image_from_texture(__DRIcontext *context, int target, 477 unsigned texture, int zoffset, 478 int level, 479 unsigned *error, 480 void *loaderPrivate) 481 { 482 __DRIimage *image; 483 struct brw_context *brw = context->driverPrivate; 484 struct gl_texture_object *obj; 485 struct intel_texture_object *iobj; 486 GLuint face = 0; 487 488 obj = _mesa_lookup_texture(&brw->ctx, texture); 489 if (!obj || obj->Target != target) { 490 *error = __DRI_IMAGE_ERROR_BAD_PARAMETER; 491 return NULL; 492 } 493 494 if (target == GL_TEXTURE_CUBE_MAP) 495 face = zoffset; 496 497 _mesa_test_texobj_completeness(&brw->ctx, obj); 498 iobj = intel_texture_object(obj); 499 if (!obj->_BaseComplete || (level > 0 && !obj->_MipmapComplete)) { 500 *error = __DRI_IMAGE_ERROR_BAD_PARAMETER; 501 return NULL; 502 } 503 504 if (level < obj->BaseLevel || level > obj->_MaxLevel) { 505 *error = __DRI_IMAGE_ERROR_BAD_MATCH; 506 return NULL; 507 } 508 509 if (target == GL_TEXTURE_3D && obj->Image[face][level]->Depth < zoffset) { 510 *error = __DRI_IMAGE_ERROR_BAD_MATCH; 511 return NULL; 512 } 513 image = calloc(1, sizeof *image); 514 if (image == NULL) { 515 *error = __DRI_IMAGE_ERROR_BAD_ALLOC; 516 return NULL; 517 } 518 519 image->internal_format = obj->Image[face][level]->InternalFormat; 520 image->format = obj->Image[face][level]->TexFormat; 521 image->data = loaderPrivate; 522 intel_setup_image_from_mipmap_tree(brw, image, iobj->mt, level, zoffset); 523 image->dri_format = driGLFormatToImageFormat(image->format); 524 image->has_depthstencil = iobj->mt->stencil_mt? true : false; 525 if (image->dri_format == MESA_FORMAT_NONE) { 526 *error = __DRI_IMAGE_ERROR_BAD_PARAMETER; 527 free(image); 528 return NULL; 529 } 530 531 *error = __DRI_IMAGE_ERROR_SUCCESS; 532 return image; 533 } 534 535 static void 536 intel_destroy_image(__DRIimage *image) 537 { 538 drm_intel_bo_unreference(image->bo); 539 free(image); 540 } 541 542 static __DRIimage * 543 intel_create_image(__DRIscreen *dri_screen, 544 int width, int height, int format, 545 unsigned int use, 546 void *loaderPrivate) 547 { 548 __DRIimage *image; 549 struct intel_screen *screen = dri_screen->driverPrivate; 550 uint32_t tiling; 551 int cpp; 552 unsigned long pitch; 553 554 tiling = I915_TILING_X; 555 if (use & __DRI_IMAGE_USE_CURSOR) { 556 if (width != 64 || height != 64) 557 return NULL; 558 tiling = I915_TILING_NONE; 559 } 560 561 if (use & __DRI_IMAGE_USE_LINEAR) 562 tiling = I915_TILING_NONE; 563 564 image = intel_allocate_image(format, loaderPrivate); 565 if (image == NULL) 566 return NULL; 567 568 cpp = _mesa_get_format_bytes(image->format); 569 image->bo = drm_intel_bo_alloc_tiled(screen->bufmgr, "image", 570 width, height, cpp, &tiling, 571 &pitch, 0); 572 if (image->bo == NULL) { 573 free(image); 574 return NULL; 575 } 576 image->width = width; 577 image->height = height; 578 image->pitch = pitch; 579 580 return image; 581 } 582 583 static GLboolean 584 intel_query_image(__DRIimage *image, int attrib, int *value) 585 { 586 switch (attrib) { 587 case __DRI_IMAGE_ATTRIB_STRIDE: 588 *value = image->pitch; 589 return true; 590 case __DRI_IMAGE_ATTRIB_HANDLE: 591 *value = image->bo->handle; 592 return true; 593 case __DRI_IMAGE_ATTRIB_NAME: 594 return !drm_intel_bo_flink(image->bo, (uint32_t *) value); 595 case __DRI_IMAGE_ATTRIB_FORMAT: 596 *value = image->dri_format; 597 return true; 598 case __DRI_IMAGE_ATTRIB_WIDTH: 599 *value = image->width; 600 return true; 601 case __DRI_IMAGE_ATTRIB_HEIGHT: 602 *value = image->height; 603 return true; 604 case __DRI_IMAGE_ATTRIB_COMPONENTS: 605 if (image->planar_format == NULL) 606 return false; 607 *value = image->planar_format->components; 608 return true; 609 case __DRI_IMAGE_ATTRIB_FD: 610 return !drm_intel_bo_gem_export_to_prime(image->bo, value); 611 case __DRI_IMAGE_ATTRIB_FOURCC: 612 return intel_lookup_fourcc(image->dri_format, value); 613 case __DRI_IMAGE_ATTRIB_NUM_PLANES: 614 *value = 1; 615 return true; 616 case __DRI_IMAGE_ATTRIB_OFFSET: 617 *value = image->offset; 618 return true; 619 620 default: 621 return false; 622 } 623 } 624 625 static __DRIimage * 626 intel_dup_image(__DRIimage *orig_image, void *loaderPrivate) 627 { 628 __DRIimage *image; 629 630 image = calloc(1, sizeof *image); 631 if (image == NULL) 632 return NULL; 633 634 drm_intel_bo_reference(orig_image->bo); 635 image->bo = orig_image->bo; 636 image->internal_format = orig_image->internal_format; 637 image->planar_format = orig_image->planar_format; 638 image->dri_format = orig_image->dri_format; 639 image->format = orig_image->format; 640 image->offset = orig_image->offset; 641 image->width = orig_image->width; 642 image->height = orig_image->height; 643 image->pitch = orig_image->pitch; 644 image->tile_x = orig_image->tile_x; 645 image->tile_y = orig_image->tile_y; 646 image->has_depthstencil = orig_image->has_depthstencil; 647 image->data = loaderPrivate; 648 649 memcpy(image->strides, orig_image->strides, sizeof(image->strides)); 650 memcpy(image->offsets, orig_image->offsets, sizeof(image->offsets)); 651 652 return image; 653 } 654 655 static GLboolean 656 intel_validate_usage(__DRIimage *image, unsigned int use) 657 { 658 if (use & __DRI_IMAGE_USE_CURSOR) { 659 if (image->width != 64 || image->height != 64) 660 return GL_FALSE; 661 } 662 663 return GL_TRUE; 664 } 665 666 static __DRIimage * 667 intel_create_image_from_names(__DRIscreen *dri_screen, 668 int width, int height, int fourcc, 669 int *names, int num_names, 670 int *strides, int *offsets, 671 void *loaderPrivate) 672 { 673 struct intel_image_format *f = NULL; 674 __DRIimage *image; 675 int i, index; 676 677 if (dri_screen == NULL || names == NULL || num_names != 1) 678 return NULL; 679 680 f = intel_image_format_lookup(fourcc); 681 if (f == NULL) 682 return NULL; 683 684 image = intel_create_image_from_name(dri_screen, width, height, 685 __DRI_IMAGE_FORMAT_NONE, 686 names[0], strides[0], 687 loaderPrivate); 688 689 if (image == NULL) 690 return NULL; 691 692 image->planar_format = f; 693 for (i = 0; i < f->nplanes; i++) { 694 index = f->planes[i].buffer_index; 695 image->offsets[index] = offsets[index]; 696 image->strides[index] = strides[index]; 697 } 698 699 return image; 700 } 701 702 static __DRIimage * 703 intel_create_image_from_fds(__DRIscreen *dri_screen, 704 int width, int height, int fourcc, 705 int *fds, int num_fds, int *strides, int *offsets, 706 void *loaderPrivate) 707 { 708 struct intel_screen *screen = dri_screen->driverPrivate; 709 struct intel_image_format *f; 710 __DRIimage *image; 711 int i, index; 712 713 if (fds == NULL || num_fds < 1) 714 return NULL; 715 716 /* We only support all planes from the same bo */ 717 for (i = 0; i < num_fds; i++) 718 if (fds[0] != fds[i]) 719 return NULL; 720 721 f = intel_image_format_lookup(fourcc); 722 if (f == NULL) 723 return NULL; 724 725 if (f->nplanes == 1) 726 image = intel_allocate_image(f->planes[0].dri_format, loaderPrivate); 727 else 728 image = intel_allocate_image(__DRI_IMAGE_FORMAT_NONE, loaderPrivate); 729 730 if (image == NULL) 731 return NULL; 732 733 image->width = width; 734 image->height = height; 735 image->pitch = strides[0]; 736 737 image->planar_format = f; 738 int size = 0; 739 for (i = 0; i < f->nplanes; i++) { 740 index = f->planes[i].buffer_index; 741 image->offsets[index] = offsets[index]; 742 image->strides[index] = strides[index]; 743 744 const int plane_height = height >> f->planes[i].height_shift; 745 const int end = offsets[index] + plane_height * strides[index]; 746 if (size < end) 747 size = end; 748 } 749 750 image->bo = drm_intel_bo_gem_create_from_prime(screen->bufmgr, 751 fds[0], size); 752 if (image->bo == NULL) { 753 free(image); 754 return NULL; 755 } 756 757 if (f->nplanes == 1) { 758 image->offset = image->offsets[0]; 759 intel_image_warn_if_unaligned(image, __func__); 760 } 761 762 return image; 763 } 764 765 static __DRIimage * 766 intel_create_image_from_dma_bufs(__DRIscreen *dri_screen, 767 int width, int height, int fourcc, 768 int *fds, int num_fds, 769 int *strides, int *offsets, 770 enum __DRIYUVColorSpace yuv_color_space, 771 enum __DRISampleRange sample_range, 772 enum __DRIChromaSiting horizontal_siting, 773 enum __DRIChromaSiting vertical_siting, 774 unsigned *error, 775 void *loaderPrivate) 776 { 777 __DRIimage *image; 778 struct intel_image_format *f = intel_image_format_lookup(fourcc); 779 780 if (!f) { 781 *error = __DRI_IMAGE_ERROR_BAD_MATCH; 782 return NULL; 783 } 784 785 image = intel_create_image_from_fds(dri_screen, width, height, fourcc, fds, 786 num_fds, strides, offsets, 787 loaderPrivate); 788 789 /* 790 * Invalid parameters and any inconsistencies between are assumed to be 791 * checked by the caller. Therefore besides unsupported formats one can fail 792 * only in allocation. 793 */ 794 if (!image) { 795 *error = __DRI_IMAGE_ERROR_BAD_ALLOC; 796 return NULL; 797 } 798 799 image->dma_buf_imported = true; 800 image->yuv_color_space = yuv_color_space; 801 image->sample_range = sample_range; 802 image->horizontal_siting = horizontal_siting; 803 image->vertical_siting = vertical_siting; 804 805 *error = __DRI_IMAGE_ERROR_SUCCESS; 806 return image; 807 } 808 809 static __DRIimage * 810 intel_from_planar(__DRIimage *parent, int plane, void *loaderPrivate) 811 { 812 int width, height, offset, stride, dri_format, index; 813 struct intel_image_format *f; 814 __DRIimage *image; 815 816 if (parent == NULL || parent->planar_format == NULL) 817 return NULL; 818 819 f = parent->planar_format; 820 821 if (plane >= f->nplanes) 822 return NULL; 823 824 width = parent->width >> f->planes[plane].width_shift; 825 height = parent->height >> f->planes[plane].height_shift; 826 dri_format = f->planes[plane].dri_format; 827 index = f->planes[plane].buffer_index; 828 offset = parent->offsets[index]; 829 stride = parent->strides[index]; 830 831 image = intel_allocate_image(dri_format, loaderPrivate); 832 if (image == NULL) 833 return NULL; 834 835 if (offset + height * stride > parent->bo->size) { 836 _mesa_warning(NULL, "intel_create_sub_image: subimage out of bounds"); 837 free(image); 838 return NULL; 839 } 840 841 image->bo = parent->bo; 842 drm_intel_bo_reference(parent->bo); 843 844 image->width = width; 845 image->height = height; 846 image->pitch = stride; 847 image->offset = offset; 848 849 intel_image_warn_if_unaligned(image, __func__); 850 851 return image; 852 } 853 854 static const __DRIimageExtension intelImageExtension = { 855 .base = { __DRI_IMAGE, 13 }, 856 857 .createImageFromName = intel_create_image_from_name, 858 .createImageFromRenderbuffer = intel_create_image_from_renderbuffer, 859 .destroyImage = intel_destroy_image, 860 .createImage = intel_create_image, 861 .queryImage = intel_query_image, 862 .dupImage = intel_dup_image, 863 .validateUsage = intel_validate_usage, 864 .createImageFromNames = intel_create_image_from_names, 865 .fromPlanar = intel_from_planar, 866 .createImageFromTexture = intel_create_image_from_texture, 867 .createImageFromFds = intel_create_image_from_fds, 868 .createImageFromDmaBufs = intel_create_image_from_dma_bufs, 869 .blitImage = NULL, 870 .getCapabilities = NULL, 871 .mapImage = NULL, 872 .unmapImage = NULL, 873 }; 874 875 static int 876 brw_query_renderer_integer(__DRIscreen *dri_screen, 877 int param, unsigned int *value) 878 { 879 const struct intel_screen *const screen = 880 (struct intel_screen *) dri_screen->driverPrivate; 881 882 switch (param) { 883 case __DRI2_RENDERER_VENDOR_ID: 884 value[0] = 0x8086; 885 return 0; 886 case __DRI2_RENDERER_DEVICE_ID: 887 value[0] = screen->deviceID; 888 return 0; 889 case __DRI2_RENDERER_ACCELERATED: 890 value[0] = 1; 891 return 0; 892 case __DRI2_RENDERER_VIDEO_MEMORY: { 893 /* Once a batch uses more than 75% of the maximum mappable size, we 894 * assume that there's some fragmentation, and we start doing extra 895 * flushing, etc. That's the big cliff apps will care about. 896 */ 897 size_t aper_size; 898 size_t mappable_size; 899 900 drm_intel_get_aperture_sizes(dri_screen->fd, &mappable_size, &aper_size); 901 902 const unsigned gpu_mappable_megabytes = 903 (aper_size / (1024 * 1024)) * 3 / 4; 904 905 const long system_memory_pages = sysconf(_SC_PHYS_PAGES); 906 const long system_page_size = sysconf(_SC_PAGE_SIZE); 907 908 if (system_memory_pages <= 0 || system_page_size <= 0) 909 return -1; 910 911 const uint64_t system_memory_bytes = (uint64_t) system_memory_pages 912 * (uint64_t) system_page_size; 913 914 const unsigned system_memory_megabytes = 915 (unsigned) (system_memory_bytes / (1024 * 1024)); 916 917 value[0] = MIN2(system_memory_megabytes, gpu_mappable_megabytes); 918 return 0; 919 } 920 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE: 921 value[0] = 1; 922 return 0; 923 case __DRI2_RENDERER_HAS_TEXTURE_3D: 924 value[0] = 1; 925 return 0; 926 default: 927 return driQueryRendererIntegerCommon(dri_screen, param, value); 928 } 929 930 return -1; 931 } 932 933 static int 934 brw_query_renderer_string(__DRIscreen *dri_screen, 935 int param, const char **value) 936 { 937 const struct intel_screen *screen = 938 (struct intel_screen *) dri_screen->driverPrivate; 939 940 switch (param) { 941 case __DRI2_RENDERER_VENDOR_ID: 942 value[0] = brw_vendor_string; 943 return 0; 944 case __DRI2_RENDERER_DEVICE_ID: 945 value[0] = brw_get_renderer_string(screen); 946 return 0; 947 default: 948 break; 949 } 950 951 return -1; 952 } 953 954 static const __DRI2rendererQueryExtension intelRendererQueryExtension = { 955 .base = { __DRI2_RENDERER_QUERY, 1 }, 956 957 .queryInteger = brw_query_renderer_integer, 958 .queryString = brw_query_renderer_string 959 }; 960 961 static const __DRIrobustnessExtension dri2Robustness = { 962 .base = { __DRI2_ROBUSTNESS, 1 } 963 }; 964 965 static const __DRIextension *screenExtensions[] = { 966 &intelTexBufferExtension.base, 967 &intelFenceExtension.base, 968 &intelFlushExtension.base, 969 &intelImageExtension.base, 970 &intelRendererQueryExtension.base, 971 &dri2ConfigQueryExtension.base, 972 NULL 973 }; 974 975 static const __DRIextension *intelRobustScreenExtensions[] = { 976 &intelTexBufferExtension.base, 977 &intelFenceExtension.base, 978 &intelFlushExtension.base, 979 &intelImageExtension.base, 980 &intelRendererQueryExtension.base, 981 &dri2ConfigQueryExtension.base, 982 &dri2Robustness.base, 983 NULL 984 }; 985 986 static int 987 intel_get_param(struct intel_screen *screen, int param, int *value) 988 { 989 int ret = 0; 990 struct drm_i915_getparam gp; 991 992 memset(&gp, 0, sizeof(gp)); 993 gp.param = param; 994 gp.value = value; 995 996 if (drmIoctl(screen->driScrnPriv->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1) { 997 ret = -errno; 998 if (ret != -EINVAL) 999 _mesa_warning(NULL, "drm_i915_getparam: %d", ret); 1000 } 1001 1002 return ret; 1003 } 1004 1005 static bool 1006 intel_get_boolean(struct intel_screen *screen, int param) 1007 { 1008 int value = 0; 1009 return (intel_get_param(screen, param, &value) == 0) && value; 1010 } 1011 1012 static int 1013 intel_get_integer(struct intel_screen *screen, int param) 1014 { 1015 int value = -1; 1016 1017 if (intel_get_param(screen, param, &value) == 0) 1018 return value; 1019 1020 return -1; 1021 } 1022 1023 static void 1024 intelDestroyScreen(__DRIscreen * sPriv) 1025 { 1026 struct intel_screen *screen = sPriv->driverPrivate; 1027 1028 dri_bufmgr_destroy(screen->bufmgr); 1029 driDestroyOptionInfo(&screen->optionCache); 1030 1031 ralloc_free(screen); 1032 sPriv->driverPrivate = NULL; 1033 } 1034 1035 1036 /** 1037 * This is called when we need to set up GL rendering to a new X window. 1038 */ 1039 static GLboolean 1040 intelCreateBuffer(__DRIscreen *dri_screen, 1041 __DRIdrawable * driDrawPriv, 1042 const struct gl_config * mesaVis, GLboolean isPixmap) 1043 { 1044 struct intel_renderbuffer *rb; 1045 struct intel_screen *screen = (struct intel_screen *) 1046 dri_screen->driverPrivate; 1047 mesa_format rgbFormat; 1048 unsigned num_samples = 1049 intel_quantize_num_samples(screen, mesaVis->samples); 1050 struct gl_framebuffer *fb; 1051 1052 if (isPixmap) 1053 return false; 1054 1055 fb = CALLOC_STRUCT(gl_framebuffer); 1056 if (!fb) 1057 return false; 1058 1059 _mesa_initialize_window_framebuffer(fb, mesaVis); 1060 1061 if (screen->winsys_msaa_samples_override != -1) { 1062 num_samples = screen->winsys_msaa_samples_override; 1063 fb->Visual.samples = num_samples; 1064 } 1065 1066 if (mesaVis->redBits == 5) { 1067 rgbFormat = mesaVis->redMask == 0x1f ? MESA_FORMAT_R5G6B5_UNORM 1068 : MESA_FORMAT_B5G6R5_UNORM; 1069 } else if (mesaVis->sRGBCapable) { 1070 rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8A8_SRGB 1071 : MESA_FORMAT_B8G8R8A8_SRGB; 1072 } else if (mesaVis->alphaBits == 0) { 1073 rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8X8_UNORM 1074 : MESA_FORMAT_B8G8R8X8_UNORM; 1075 } else { 1076 rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8A8_SRGB 1077 : MESA_FORMAT_B8G8R8A8_SRGB; 1078 fb->Visual.sRGBCapable = true; 1079 } 1080 1081 /* setup the hardware-based renderbuffers */ 1082 rb = intel_create_renderbuffer(rgbFormat, num_samples); 1083 _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &rb->Base.Base); 1084 1085 if (mesaVis->doubleBufferMode) { 1086 rb = intel_create_renderbuffer(rgbFormat, num_samples); 1087 _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &rb->Base.Base); 1088 } 1089 1090 /* 1091 * Assert here that the gl_config has an expected depth/stencil bit 1092 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(), 1093 * which constructs the advertised configs.) 1094 */ 1095 if (mesaVis->depthBits == 24) { 1096 assert(mesaVis->stencilBits == 8); 1097 1098 if (screen->devinfo.has_hiz_and_separate_stencil) { 1099 rb = intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT, 1100 num_samples); 1101 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base); 1102 rb = intel_create_private_renderbuffer(MESA_FORMAT_S_UINT8, 1103 num_samples); 1104 _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &rb->Base.Base); 1105 } else { 1106 /* 1107 * Use combined depth/stencil. Note that the renderbuffer is 1108 * attached to two attachment points. 1109 */ 1110 rb = intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT, 1111 num_samples); 1112 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base); 1113 _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &rb->Base.Base); 1114 } 1115 } 1116 else if (mesaVis->depthBits == 16) { 1117 assert(mesaVis->stencilBits == 0); 1118 rb = intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16, 1119 num_samples); 1120 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base); 1121 } 1122 else { 1123 assert(mesaVis->depthBits == 0); 1124 assert(mesaVis->stencilBits == 0); 1125 } 1126 1127 /* now add any/all software-based renderbuffers we may need */ 1128 _swrast_add_soft_renderbuffers(fb, 1129 false, /* never sw color */ 1130 false, /* never sw depth */ 1131 false, /* never sw stencil */ 1132 mesaVis->accumRedBits > 0, 1133 false, /* never sw alpha */ 1134 false /* never sw aux */ ); 1135 driDrawPriv->driverPrivate = fb; 1136 1137 return true; 1138 } 1139 1140 static void 1141 intelDestroyBuffer(__DRIdrawable * driDrawPriv) 1142 { 1143 struct gl_framebuffer *fb = driDrawPriv->driverPrivate; 1144 1145 _mesa_reference_framebuffer(&fb, NULL); 1146 } 1147 1148 static void 1149 intel_detect_sseu(struct intel_screen *screen) 1150 { 1151 assert(screen->devinfo.gen >= 8); 1152 int ret; 1153 1154 screen->subslice_total = -1; 1155 screen->eu_total = -1; 1156 1157 ret = intel_get_param(screen, I915_PARAM_SUBSLICE_TOTAL, 1158 &screen->subslice_total); 1159 if (ret < 0 && ret != -EINVAL) 1160 goto err_out; 1161 1162 ret = intel_get_param(screen, 1163 I915_PARAM_EU_TOTAL, &screen->eu_total); 1164 if (ret < 0 && ret != -EINVAL) 1165 goto err_out; 1166 1167 /* Without this information, we cannot get the right Braswell brandstrings, 1168 * and we have to use conservative numbers for GPGPU on many platforms, but 1169 * otherwise, things will just work. 1170 */ 1171 if (screen->subslice_total < 1 || screen->eu_total < 1) 1172 _mesa_warning(NULL, 1173 "Kernel 4.1 required to properly query GPU properties.\n"); 1174 1175 return; 1176 1177 err_out: 1178 screen->subslice_total = -1; 1179 screen->eu_total = -1; 1180 _mesa_warning(NULL, "Failed to query GPU properties (%s).\n", strerror(-ret)); 1181 } 1182 1183 static bool 1184 intel_init_bufmgr(struct intel_screen *screen) 1185 { 1186 __DRIscreen *dri_screen = screen->driScrnPriv; 1187 1188 screen->no_hw = getenv("INTEL_NO_HW") != NULL; 1189 1190 screen->bufmgr = intel_bufmgr_gem_init(dri_screen->fd, BATCH_SZ); 1191 if (screen->bufmgr == NULL) { 1192 fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n", 1193 __func__, __LINE__); 1194 return false; 1195 } 1196 1197 drm_intel_bufmgr_gem_enable_fenced_relocs(screen->bufmgr); 1198 1199 if (!intel_get_boolean(screen, I915_PARAM_HAS_RELAXED_DELTA)) { 1200 fprintf(stderr, "[%s: %u] Kernel 2.6.39 required.\n", __func__, __LINE__); 1201 return false; 1202 } 1203 1204 return true; 1205 } 1206 1207 static bool 1208 intel_detect_swizzling(struct intel_screen *screen) 1209 { 1210 drm_intel_bo *buffer; 1211 unsigned long flags = 0; 1212 unsigned long aligned_pitch; 1213 uint32_t tiling = I915_TILING_X; 1214 uint32_t swizzle_mode = 0; 1215 1216 buffer = drm_intel_bo_alloc_tiled(screen->bufmgr, "swizzle test", 1217 64, 64, 4, 1218 &tiling, &aligned_pitch, flags); 1219 if (buffer == NULL) 1220 return false; 1221 1222 drm_intel_bo_get_tiling(buffer, &tiling, &swizzle_mode); 1223 drm_intel_bo_unreference(buffer); 1224 1225 if (swizzle_mode == I915_BIT_6_SWIZZLE_NONE) 1226 return false; 1227 else 1228 return true; 1229 } 1230 1231 static int 1232 intel_detect_timestamp(struct intel_screen *screen) 1233 { 1234 uint64_t dummy = 0, last = 0; 1235 int upper, lower, loops; 1236 1237 /* On 64bit systems, some old kernels trigger a hw bug resulting in the 1238 * TIMESTAMP register being shifted and the low 32bits always zero. 1239 * 1240 * More recent kernels offer an interface to read the full 36bits 1241 * everywhere. 1242 */ 1243 if (drm_intel_reg_read(screen->bufmgr, TIMESTAMP | 1, &dummy) == 0) 1244 return 3; 1245 1246 /* Determine if we have a 32bit or 64bit kernel by inspecting the 1247 * upper 32bits for a rapidly changing timestamp. 1248 */ 1249 if (drm_intel_reg_read(screen->bufmgr, TIMESTAMP, &last)) 1250 return 0; 1251 1252 upper = lower = 0; 1253 for (loops = 0; loops < 10; loops++) { 1254 /* The TIMESTAMP should change every 80ns, so several round trips 1255 * through the kernel should be enough to advance it. 1256 */ 1257 if (drm_intel_reg_read(screen->bufmgr, TIMESTAMP, &dummy)) 1258 return 0; 1259 1260 upper += (dummy >> 32) != (last >> 32); 1261 if (upper > 1) /* beware 32bit counter overflow */ 1262 return 2; /* upper dword holds the low 32bits of the timestamp */ 1263 1264 lower += (dummy & 0xffffffff) != (last & 0xffffffff); 1265 if (lower > 1) 1266 return 1; /* timestamp is unshifted */ 1267 1268 last = dummy; 1269 } 1270 1271 /* No advancement? No timestamp! */ 1272 return 0; 1273 } 1274 1275 /** 1276 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer. 1277 * 1278 * Some combinations of hardware and kernel versions allow this feature, 1279 * while others don't. Instead of trying to enumerate every case, just 1280 * try and write a register and see if works. 1281 */ 1282 static bool 1283 intel_detect_pipelined_register(struct intel_screen *screen, 1284 int reg, uint32_t expected_value, bool reset) 1285 { 1286 drm_intel_bo *results, *bo; 1287 uint32_t *batch; 1288 uint32_t offset = 0; 1289 bool success = false; 1290 1291 /* Create a zero'ed temporary buffer for reading our results */ 1292 results = drm_intel_bo_alloc(screen->bufmgr, "registers", 4096, 0); 1293 if (results == NULL) 1294 goto err; 1295 1296 bo = drm_intel_bo_alloc(screen->bufmgr, "batchbuffer", 4096, 0); 1297 if (bo == NULL) 1298 goto err_results; 1299 1300 if (drm_intel_bo_map(bo, 1)) 1301 goto err_batch; 1302 1303 batch = bo->virtual; 1304 1305 /* Write the register. */ 1306 *batch++ = MI_LOAD_REGISTER_IMM | (3 - 2); 1307 *batch++ = reg; 1308 *batch++ = expected_value; 1309 1310 /* Save the register's value back to the buffer. */ 1311 *batch++ = MI_STORE_REGISTER_MEM | (3 - 2); 1312 *batch++ = reg; 1313 drm_intel_bo_emit_reloc(bo, (char *)batch -(char *)bo->virtual, 1314 results, offset*sizeof(uint32_t), 1315 I915_GEM_DOMAIN_INSTRUCTION, 1316 I915_GEM_DOMAIN_INSTRUCTION); 1317 *batch++ = results->offset + offset*sizeof(uint32_t); 1318 1319 /* And afterwards clear the register */ 1320 if (reset) { 1321 *batch++ = MI_LOAD_REGISTER_IMM | (3 - 2); 1322 *batch++ = reg; 1323 *batch++ = 0; 1324 } 1325 1326 *batch++ = MI_BATCH_BUFFER_END; 1327 1328 drm_intel_bo_mrb_exec(bo, ALIGN((char *)batch - (char *)bo->virtual, 8), 1329 NULL, 0, 0, 1330 I915_EXEC_RENDER); 1331 1332 /* Check whether the value got written. */ 1333 if (drm_intel_bo_map(results, false) == 0) { 1334 success = *((uint32_t *)results->virtual + offset) == expected_value; 1335 drm_intel_bo_unmap(results); 1336 } 1337 1338 err_batch: 1339 drm_intel_bo_unreference(bo); 1340 err_results: 1341 drm_intel_bo_unreference(results); 1342 err: 1343 return success; 1344 } 1345 1346 static bool 1347 intel_detect_pipelined_so(struct intel_screen *screen) 1348 { 1349 const struct gen_device_info *devinfo = &screen->devinfo; 1350 1351 /* Supposedly, Broadwell just works. */ 1352 if (devinfo->gen >= 8) 1353 return true; 1354 1355 if (devinfo->gen <= 6) 1356 return false; 1357 1358 /* See the big explanation about command parser versions below */ 1359 if (screen->cmd_parser_version >= (devinfo->is_haswell ? 7 : 2)) 1360 return true; 1361 1362 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the 1363 * statistics registers), and we already reset it to zero before using it. 1364 */ 1365 return intel_detect_pipelined_register(screen, 1366 GEN7_SO_WRITE_OFFSET(0), 1367 0x1337d0d0, 1368 false); 1369 } 1370 1371 /** 1372 * Return array of MSAA modes supported by the hardware. The array is 1373 * zero-terminated and sorted in decreasing order. 1374 */ 1375 const int* 1376 intel_supported_msaa_modes(const struct intel_screen *screen) 1377 { 1378 static const int gen9_modes[] = {16, 8, 4, 2, 0, -1}; 1379 static const int gen8_modes[] = {8, 4, 2, 0, -1}; 1380 static const int gen7_modes[] = {8, 4, 0, -1}; 1381 static const int gen6_modes[] = {4, 0, -1}; 1382 static const int gen4_modes[] = {0, -1}; 1383 1384 if (screen->devinfo.gen >= 9) { 1385 return gen9_modes; 1386 } else if (screen->devinfo.gen >= 8) { 1387 return gen8_modes; 1388 } else if (screen->devinfo.gen >= 7) { 1389 return gen7_modes; 1390 } else if (screen->devinfo.gen == 6) { 1391 return gen6_modes; 1392 } else { 1393 return gen4_modes; 1394 } 1395 } 1396 1397 static __DRIconfig** 1398 intel_screen_make_configs(__DRIscreen *dri_screen) 1399 { 1400 static const mesa_format formats[] = { 1401 MESA_FORMAT_B5G6R5_UNORM, 1402 MESA_FORMAT_B8G8R8A8_UNORM, 1403 MESA_FORMAT_B8G8R8X8_UNORM 1404 }; 1405 1406 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */ 1407 static const GLenum back_buffer_modes[] = { 1408 GLX_SWAP_UNDEFINED_OML, GLX_NONE, 1409 }; 1410 1411 static const uint8_t singlesample_samples[1] = {0}; 1412 static const uint8_t multisample_samples[2] = {4, 8}; 1413 1414 struct intel_screen *screen = dri_screen->driverPrivate; 1415 const struct gen_device_info *devinfo = &screen->devinfo; 1416 uint8_t depth_bits[4], stencil_bits[4]; 1417 __DRIconfig **configs = NULL; 1418 1419 /* Generate singlesample configs without accumulation buffer. */ 1420 for (unsigned i = 0; i < ARRAY_SIZE(formats); i++) { 1421 __DRIconfig **new_configs; 1422 int num_depth_stencil_bits = 2; 1423 1424 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil 1425 * buffer that has a different number of bits per pixel than the color 1426 * buffer, gen >= 6 supports this. 1427 */ 1428 depth_bits[0] = 0; 1429 stencil_bits[0] = 0; 1430 1431 if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) { 1432 depth_bits[1] = 16; 1433 stencil_bits[1] = 0; 1434 if (devinfo->gen >= 6) { 1435 depth_bits[2] = 24; 1436 stencil_bits[2] = 8; 1437 num_depth_stencil_bits = 3; 1438 } 1439 } else { 1440 depth_bits[1] = 24; 1441 stencil_bits[1] = 8; 1442 } 1443 1444 new_configs = driCreateConfigs(formats[i], 1445 depth_bits, 1446 stencil_bits, 1447 num_depth_stencil_bits, 1448 back_buffer_modes, 2, 1449 singlesample_samples, 1, 1450 false, false); 1451 configs = driConcatConfigs(configs, new_configs); 1452 } 1453 1454 /* Generate the minimum possible set of configs that include an 1455 * accumulation buffer. 1456 */ 1457 for (unsigned i = 0; i < ARRAY_SIZE(formats); i++) { 1458 __DRIconfig **new_configs; 1459 1460 if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) { 1461 depth_bits[0] = 16; 1462 stencil_bits[0] = 0; 1463 } else { 1464 depth_bits[0] = 24; 1465 stencil_bits[0] = 8; 1466 } 1467 1468 new_configs = driCreateConfigs(formats[i], 1469 depth_bits, stencil_bits, 1, 1470 back_buffer_modes, 1, 1471 singlesample_samples, 1, 1472 true, false); 1473 configs = driConcatConfigs(configs, new_configs); 1474 } 1475 1476 /* Generate multisample configs. 1477 * 1478 * This loop breaks early, and hence is a no-op, on gen < 6. 1479 * 1480 * Multisample configs must follow the singlesample configs in order to 1481 * work around an X server bug present in 1.12. The X server chooses to 1482 * associate the first listed RGBA888-Z24S8 config, regardless of its 1483 * sample count, with the 32-bit depth visual used for compositing. 1484 * 1485 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are 1486 * supported. Singlebuffer configs are not supported because no one wants 1487 * them. 1488 */ 1489 for (unsigned i = 0; i < ARRAY_SIZE(formats); i++) { 1490 if (devinfo->gen < 6) 1491 break; 1492 1493 __DRIconfig **new_configs; 1494 const int num_depth_stencil_bits = 2; 1495 int num_msaa_modes = 0; 1496 1497 depth_bits[0] = 0; 1498 stencil_bits[0] = 0; 1499 1500 if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) { 1501 depth_bits[1] = 16; 1502 stencil_bits[1] = 0; 1503 } else { 1504 depth_bits[1] = 24; 1505 stencil_bits[1] = 8; 1506 } 1507 1508 if (devinfo->gen >= 7) 1509 num_msaa_modes = 2; 1510 else if (devinfo->gen == 6) 1511 num_msaa_modes = 1; 1512 1513 new_configs = driCreateConfigs(formats[i], 1514 depth_bits, 1515 stencil_bits, 1516 num_depth_stencil_bits, 1517 back_buffer_modes, 1, 1518 multisample_samples, 1519 num_msaa_modes, 1520 false, false); 1521 configs = driConcatConfigs(configs, new_configs); 1522 } 1523 1524 if (configs == NULL) { 1525 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__, 1526 __LINE__); 1527 return NULL; 1528 } 1529 1530 return configs; 1531 } 1532 1533 static void 1534 set_max_gl_versions(struct intel_screen *screen) 1535 { 1536 __DRIscreen *dri_screen = screen->driScrnPriv; 1537 const bool has_astc = screen->devinfo.gen >= 9; 1538 1539 switch (screen->devinfo.gen) { 1540 case 9: 1541 case 8: 1542 dri_screen->max_gl_core_version = 45; 1543 dri_screen->max_gl_compat_version = 30; 1544 dri_screen->max_gl_es1_version = 11; 1545 dri_screen->max_gl_es2_version = has_astc ? 32 : 31; 1546 break; 1547 case 7: 1548 dri_screen->max_gl_core_version = 33; 1549 if (screen->devinfo.is_haswell && 1550 can_do_pipelined_register_writes(screen)) { 1551 dri_screen->max_gl_core_version = 42; 1552 if (can_do_compute_dispatch(screen)) 1553 dri_screen->max_gl_core_version = 43; 1554 if (can_do_mi_math_and_lrr(screen)) 1555 dri_screen->max_gl_core_version = 45; 1556 } 1557 dri_screen->max_gl_compat_version = 30; 1558 dri_screen->max_gl_es1_version = 11; 1559 dri_screen->max_gl_es2_version = screen->devinfo.is_haswell ? 31 : 30; 1560 break; 1561 case 6: 1562 dri_screen->max_gl_core_version = 33; 1563 dri_screen->max_gl_compat_version = 30; 1564 dri_screen->max_gl_es1_version = 11; 1565 dri_screen->max_gl_es2_version = 30; 1566 break; 1567 case 5: 1568 case 4: 1569 dri_screen->max_gl_core_version = 0; 1570 dri_screen->max_gl_compat_version = 21; 1571 dri_screen->max_gl_es1_version = 11; 1572 dri_screen->max_gl_es2_version = 20; 1573 break; 1574 default: 1575 unreachable("unrecognized intel_screen::gen"); 1576 } 1577 } 1578 1579 /** 1580 * Return the revision (generally the revid field of the PCI header) of the 1581 * graphics device. 1582 * 1583 * XXX: This function is useful to keep around even if it is not currently in 1584 * use. It is necessary for new platforms and revision specific workarounds or 1585 * features. Please don't remove it so that we know it at least continues to 1586 * build. 1587 */ 1588 static __attribute__((__unused__)) int 1589 brw_get_revision(int fd) 1590 { 1591 struct drm_i915_getparam gp; 1592 int revision; 1593 int ret; 1594 1595 memset(&gp, 0, sizeof(gp)); 1596 gp.param = I915_PARAM_REVISION; 1597 gp.value = &revision; 1598 1599 ret = drmCommandWriteRead(fd, DRM_I915_GETPARAM, &gp, sizeof(gp)); 1600 if (ret) 1601 revision = -1; 1602 1603 return revision; 1604 } 1605 1606 /* Drop when RS headers get pulled to libdrm */ 1607 #ifndef I915_PARAM_HAS_RESOURCE_STREAMER 1608 #define I915_PARAM_HAS_RESOURCE_STREAMER 36 1609 #endif 1610 1611 static void 1612 shader_debug_log_mesa(void *data, const char *fmt, ...) 1613 { 1614 struct brw_context *brw = (struct brw_context *)data; 1615 va_list args; 1616 1617 va_start(args, fmt); 1618 GLuint msg_id = 0; 1619 _mesa_gl_vdebug(&brw->ctx, &msg_id, 1620 MESA_DEBUG_SOURCE_SHADER_COMPILER, 1621 MESA_DEBUG_TYPE_OTHER, 1622 MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args); 1623 va_end(args); 1624 } 1625 1626 static void 1627 shader_perf_log_mesa(void *data, const char *fmt, ...) 1628 { 1629 struct brw_context *brw = (struct brw_context *)data; 1630 1631 va_list args; 1632 va_start(args, fmt); 1633 1634 if (unlikely(INTEL_DEBUG & DEBUG_PERF)) { 1635 va_list args_copy; 1636 va_copy(args_copy, args); 1637 vfprintf(stderr, fmt, args_copy); 1638 va_end(args_copy); 1639 } 1640 1641 if (brw->perf_debug) { 1642 GLuint msg_id = 0; 1643 _mesa_gl_vdebug(&brw->ctx, &msg_id, 1644 MESA_DEBUG_SOURCE_SHADER_COMPILER, 1645 MESA_DEBUG_TYPE_PERFORMANCE, 1646 MESA_DEBUG_SEVERITY_MEDIUM, fmt, args); 1647 } 1648 va_end(args); 1649 } 1650 1651 /** 1652 * This is the driver specific part of the createNewScreen entry point. 1653 * Called when using DRI2. 1654 * 1655 * \return the struct gl_config supported by this driver 1656 */ 1657 static const 1658 __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen) 1659 { 1660 struct intel_screen *screen; 1661 1662 if (dri_screen->image.loader) { 1663 } else if (dri_screen->dri2.loader->base.version <= 2 || 1664 dri_screen->dri2.loader->getBuffersWithFormat == NULL) { 1665 fprintf(stderr, 1666 "\nERROR! DRI2 loader with getBuffersWithFormat() " 1667 "support required\n"); 1668 return false; 1669 } 1670 1671 /* Allocate the private area */ 1672 screen = rzalloc(NULL, struct intel_screen); 1673 if (!screen) { 1674 fprintf(stderr, "\nERROR! Allocating private area failed\n"); 1675 return false; 1676 } 1677 /* parse information in __driConfigOptions */ 1678 driParseOptionInfo(&screen->optionCache, brw_config_options.xml); 1679 1680 screen->driScrnPriv = dri_screen; 1681 dri_screen->driverPrivate = (void *) screen; 1682 1683 if (!intel_init_bufmgr(screen)) 1684 return false; 1685 1686 screen->deviceID = drm_intel_bufmgr_gem_get_devid(screen->bufmgr); 1687 if (!gen_get_device_info(screen->deviceID, &screen->devinfo)) 1688 return false; 1689 1690 brw_process_intel_debug_variable(); 1691 1692 if (INTEL_DEBUG & DEBUG_BUFMGR) 1693 dri_bufmgr_set_debug(screen->bufmgr, true); 1694 1695 if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && screen->devinfo.gen < 7) { 1696 fprintf(stderr, 1697 "shader_time debugging requires gen7 (Ivybridge) or better.\n"); 1698 INTEL_DEBUG &= ~DEBUG_SHADER_TIME; 1699 } 1700 1701 if (INTEL_DEBUG & DEBUG_AUB) 1702 drm_intel_bufmgr_gem_set_aub_dump(screen->bufmgr, true); 1703 1704 #ifndef I915_PARAM_MMAP_GTT_VERSION 1705 #define I915_PARAM_MMAP_GTT_VERSION 40 /* XXX delete me with new libdrm */ 1706 #endif 1707 if (intel_get_integer(screen, I915_PARAM_MMAP_GTT_VERSION) >= 1) { 1708 /* Theorectically unlimited! At least for individual objects... 1709 * 1710 * Currently the entire (global) address space for all GTT maps is 1711 * limited to 64bits. That is all objects on the system that are 1712 * setup for GTT mmapping must fit within 64bits. An attempt to use 1713 * one that exceeds the limit with fail in drm_intel_bo_map_gtt(). 1714 * 1715 * Long before we hit that limit, we will be practically limited by 1716 * that any single object must fit in physical memory (RAM). The upper 1717 * limit on the CPU's address space is currently 48bits (Skylake), of 1718 * which only 39bits can be physical memory. (The GPU itself also has 1719 * a 48bit addressable virtual space.) We can fit over 32 million 1720 * objects of the current maximum allocable size before running out 1721 * of mmap space. 1722 */ 1723 screen->max_gtt_map_object_size = UINT64_MAX; 1724 } else { 1725 /* Estimate the size of the mappable aperture into the GTT. There's an 1726 * ioctl to get the whole GTT size, but not one to get the mappable subset. 1727 * It turns out it's basically always 256MB, though some ancient hardware 1728 * was smaller. 1729 */ 1730 uint32_t gtt_size = 256 * 1024 * 1024; 1731 1732 /* We don't want to map two objects such that a memcpy between them would 1733 * just fault one mapping in and then the other over and over forever. So 1734 * we would need to divide the GTT size by 2. Additionally, some GTT is 1735 * taken up by things like the framebuffer and the ringbuffer and such, so 1736 * be more conservative. 1737 */ 1738 screen->max_gtt_map_object_size = gtt_size / 4; 1739 } 1740 1741 screen->hw_has_swizzling = intel_detect_swizzling(screen); 1742 screen->hw_has_timestamp = intel_detect_timestamp(screen); 1743 1744 /* GENs prior to 8 do not support EU/Subslice info */ 1745 if (screen->devinfo.gen >= 8) { 1746 intel_detect_sseu(screen); 1747 } else if (screen->devinfo.gen == 7) { 1748 screen->subslice_total = 1 << (screen->devinfo.gt - 1); 1749 } 1750 1751 /* Gen7-7.5 kernel requirements / command parser saga: 1752 * 1753 * - pre-v3.16: 1754 * Haswell and Baytrail cannot use any privileged batchbuffer features. 1755 * 1756 * Ivybridge has aliasing PPGTT on by default, which accidentally marks 1757 * all batches secure, allowing them to use any feature with no checking. 1758 * This is effectively equivalent to a command parser version of 1759 * \infinity - everything is possible. 1760 * 1761 * The command parser does not exist, and querying the version will 1762 * return -EINVAL. 1763 * 1764 * - v3.16: 1765 * The kernel enables the command parser by default, for systems with 1766 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the 1767 * hardware checker is still enabled, so Haswell and Baytrail cannot 1768 * do anything. 1769 * 1770 * Ivybridge goes from "everything is possible" to "only what the 1771 * command parser allows" (if the user boots with i915.cmd_parser=0, 1772 * then everything is possible again). We can only safely use features 1773 * allowed by the supported command parser version. 1774 * 1775 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version 1776 * implemented by the kernel, even if it's turned off. So, checking 1777 * for version > 0 does not mean that you can write registers. We have 1778 * to try it and see. The version does, however, indicate the age of 1779 * the kernel. 1780 * 1781 * Instead of matching the hardware checker's behavior of converting 1782 * privileged commands to MI_NOOP, it makes execbuf2 start returning 1783 * -EINVAL, making it dangerous to try and use privileged features. 1784 * 1785 * Effective command parser versions: 1786 * - Haswell: 0 (reporting 1, writes don't work) 1787 * - Baytrail: 0 (reporting 1, writes don't work) 1788 * - Ivybridge: 1 (enabled) or infinite (disabled) 1789 * 1790 * - v3.17: 1791 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge: 1792 * effectively version 1 (enabled) or infinite (disabled). 1793 * 1794 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b 1795 * Command parser v2 supports predicate writes. 1796 * 1797 * - Haswell: 0 (reporting 1, writes don't work) 1798 * - Baytrail: 2 (enabled) or infinite (disabled) 1799 * - Ivybridge: 2 (enabled) or infinite (disabled) 1800 * 1801 * So version >= 2 is enough to know that Ivybridge and Baytrail 1802 * will work. Haswell still can't do anything. 1803 * 1804 * - v4.0: Version 3 happened. Largely not relevant. 1805 * 1806 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b 1807 * L3 config registers are properly saved and restored as part 1808 * of the hardware context. We can approximately detect this point 1809 * in time by checking if I915_PARAM_REVISION is recognized - it 1810 * landed in a later commit, but in the same release cycle. 1811 * 1812 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284 1813 * Command parser finally gains secure batch promotion. On Haswell, 1814 * the hardware checker gets disabled, which finally allows it to do 1815 * privileged commands. 1816 * 1817 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions: 1818 * - Haswell: 3 (enabled) or 0 (disabled) 1819 * - Baytrail: 3 (enabled) or infinite (disabled) 1820 * - Ivybridge: 3 (enabled) or infinite (disabled) 1821 * 1822 * Unfortunately, detecting this point in time is tricky, because 1823 * no version bump happened when this important change occurred. 1824 * On Haswell, if we can write any register, then the kernel is at 1825 * least this new, and we can start trusting the version number. 1826 * 1827 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and 1828 * Command parser reaches version 4, allowing access to Haswell 1829 * atomic scratch and chicken3 registers. If version >= 4, we know 1830 * the kernel is new enough to support privileged features on all 1831 * hardware. However, the user might have disabled it...and the 1832 * kernel will still report version 4. So we still have to guess 1833 * and check. 1834 * 1835 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8 1836 * Command parser v5 whitelists indirect compute shader dispatch 1837 * registers, needed for OpenGL 4.3 and later. 1838 * 1839 * - v4.8: 1840 * Command parser v7 lets us use MI_MATH on Haswell. 1841 * 1842 * Additionally, the kernel begins reporting version 0 when 1843 * the command parser is disabled, allowing us to skip the 1844 * guess-and-check step on Haswell. Unfortunately, this also 1845 * means that we can no longer use it as an indicator of the 1846 * age of the kernel. 1847 */ 1848 if (intel_get_param(screen, I915_PARAM_CMD_PARSER_VERSION, 1849 &screen->cmd_parser_version) < 0) { 1850 /* Command parser does not exist - getparam is unrecognized */ 1851 screen->cmd_parser_version = 0; 1852 } 1853 1854 if (!intel_detect_pipelined_so(screen)) { 1855 /* We can't do anything, so the effective version is 0. */ 1856 screen->cmd_parser_version = 0; 1857 } else { 1858 screen->kernel_features |= KERNEL_ALLOWS_SOL_OFFSET_WRITES; 1859 } 1860 1861 if (screen->devinfo.gen >= 8 || screen->cmd_parser_version >= 2) 1862 screen->kernel_features |= KERNEL_ALLOWS_PREDICATE_WRITES; 1863 1864 /* Haswell requires command parser version 4 in order to have L3 1865 * atomic scratch1 and chicken3 bits 1866 */ 1867 if (screen->devinfo.is_haswell && screen->cmd_parser_version >= 4) { 1868 screen->kernel_features |= 1869 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3; 1870 } 1871 1872 /* Haswell requires command parser version 6 in order to write to the 1873 * MI_MATH GPR registers, and version 7 in order to use 1874 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use). 1875 */ 1876 if (screen->devinfo.gen >= 8 || 1877 (screen->devinfo.is_haswell && screen->cmd_parser_version >= 7)) { 1878 screen->kernel_features |= KERNEL_ALLOWS_MI_MATH_AND_LRR; 1879 } 1880 1881 /* Gen7 needs at least command parser version 5 to support compute */ 1882 if (screen->devinfo.gen >= 8 || screen->cmd_parser_version >= 5) 1883 screen->kernel_features |= KERNEL_ALLOWS_COMPUTE_DISPATCH; 1884 1885 const char *force_msaa = getenv("INTEL_FORCE_MSAA"); 1886 if (force_msaa) { 1887 screen->winsys_msaa_samples_override = 1888 intel_quantize_num_samples(screen, atoi(force_msaa)); 1889 printf("Forcing winsys sample count to %d\n", 1890 screen->winsys_msaa_samples_override); 1891 } else { 1892 screen->winsys_msaa_samples_override = -1; 1893 } 1894 1895 set_max_gl_versions(screen); 1896 1897 /* Notification of GPU resets requires hardware contexts and a kernel new 1898 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is 1899 * supported, calling it with a context of 0 will either generate EPERM or 1900 * no error. If the ioctl is not supported, it always generate EINVAL. 1901 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS 1902 * extension to the loader. 1903 * 1904 * Don't even try on pre-Gen6, since we don't attempt to use contexts there. 1905 */ 1906 if (screen->devinfo.gen >= 6) { 1907 struct drm_i915_reset_stats stats; 1908 memset(&stats, 0, sizeof(stats)); 1909 1910 const int ret = drmIoctl(dri_screen->fd, DRM_IOCTL_I915_GET_RESET_STATS, &stats); 1911 1912 screen->has_context_reset_notification = 1913 (ret != -1 || errno != EINVAL); 1914 } 1915 1916 dri_screen->extensions = !screen->has_context_reset_notification 1917 ? screenExtensions : intelRobustScreenExtensions; 1918 1919 screen->compiler = brw_compiler_create(screen, 1920 &screen->devinfo); 1921 screen->compiler->shader_debug_log = shader_debug_log_mesa; 1922 screen->compiler->shader_perf_log = shader_perf_log_mesa; 1923 screen->program_id = 1; 1924 1925 if (screen->devinfo.has_resource_streamer) { 1926 screen->has_resource_streamer = 1927 intel_get_boolean(screen, I915_PARAM_HAS_RESOURCE_STREAMER); 1928 } 1929 1930 return (const __DRIconfig**) intel_screen_make_configs(dri_screen); 1931 } 1932 1933 struct intel_buffer { 1934 __DRIbuffer base; 1935 drm_intel_bo *bo; 1936 }; 1937 1938 static __DRIbuffer * 1939 intelAllocateBuffer(__DRIscreen *dri_screen, 1940 unsigned attachment, unsigned format, 1941 int width, int height) 1942 { 1943 struct intel_buffer *intelBuffer; 1944 struct intel_screen *screen = dri_screen->driverPrivate; 1945 1946 assert(attachment == __DRI_BUFFER_FRONT_LEFT || 1947 attachment == __DRI_BUFFER_BACK_LEFT); 1948 1949 intelBuffer = calloc(1, sizeof *intelBuffer); 1950 if (intelBuffer == NULL) 1951 return NULL; 1952 1953 /* The front and back buffers are color buffers, which are X tiled. */ 1954 uint32_t tiling = I915_TILING_X; 1955 unsigned long pitch; 1956 int cpp = format / 8; 1957 intelBuffer->bo = drm_intel_bo_alloc_tiled(screen->bufmgr, 1958 "intelAllocateBuffer", 1959 width, 1960 height, 1961 cpp, 1962 &tiling, &pitch, 1963 BO_ALLOC_FOR_RENDER); 1964 1965 if (intelBuffer->bo == NULL) { 1966 free(intelBuffer); 1967 return NULL; 1968 } 1969 1970 drm_intel_bo_flink(intelBuffer->bo, &intelBuffer->base.name); 1971 1972 intelBuffer->base.attachment = attachment; 1973 intelBuffer->base.cpp = cpp; 1974 intelBuffer->base.pitch = pitch; 1975 1976 return &intelBuffer->base; 1977 } 1978 1979 static void 1980 intelReleaseBuffer(__DRIscreen *dri_screen, __DRIbuffer *buffer) 1981 { 1982 struct intel_buffer *intelBuffer = (struct intel_buffer *) buffer; 1983 1984 drm_intel_bo_unreference(intelBuffer->bo); 1985 free(intelBuffer); 1986 } 1987 1988 static const struct __DriverAPIRec brw_driver_api = { 1989 .InitScreen = intelInitScreen2, 1990 .DestroyScreen = intelDestroyScreen, 1991 .CreateContext = brwCreateContext, 1992 .DestroyContext = intelDestroyContext, 1993 .CreateBuffer = intelCreateBuffer, 1994 .DestroyBuffer = intelDestroyBuffer, 1995 .MakeCurrent = intelMakeCurrent, 1996 .UnbindContext = intelUnbindContext, 1997 .AllocateBuffer = intelAllocateBuffer, 1998 .ReleaseBuffer = intelReleaseBuffer 1999 }; 2000 2001 static const struct __DRIDriverVtableExtensionRec brw_vtable = { 2002 .base = { __DRI_DRIVER_VTABLE, 1 }, 2003 .vtable = &brw_driver_api, 2004 }; 2005 2006 static const __DRIextension *brw_driver_extensions[] = { 2007 &driCoreExtension.base, 2008 &driImageDriverExtension.base, 2009 &driDRI2Extension.base, 2010 &brw_vtable.base, 2011 &brw_config_options.base, 2012 NULL 2013 }; 2014 2015 PUBLIC const __DRIextension **__driDriverGetExtensions_i965(void) 2016 { 2017 globalDriverAPI = &brw_driver_api; 2018 2019 return brw_driver_extensions; 2020 } 2021
