| /art/compiler/utils/arm/ |
| assembler_arm_vixl.h | 107 WITH_FLAGS_DONT_CARE_RD_OP(Mvn);
|
| assembler_arm_vixl.cc | 105 ___ Mvn(rd, ~value);
131 case MVN:
|
| /external/vixl/test/aarch32/ |
| test-disasm-a32.cc | 413 COMPARE_BOTH(Orn(r0, r1, 0), "mvn r0, #0\n");
421 "mvn r0, #1\n"
425 "mvn ip, #1\n"
436 "mvn r0, ip\n"
448 "mvn r0, r2\n"
452 "mvn ip, r1\n"
456 "mvn r0, r0\n"
460 "mvn ip, r0\n"
468 "mvn r0, r2, lsl #1\n"
472 "mvn ip, r2, lsr #2\n
[all...] |
| test-simulator-cond-rd-operand-const-a32.cc | 120 M(Mvn) \
449 #include "aarch32/traces/simulator-cond-rd-operand-const-mvn-a32.h"
|
| test-simulator-cond-rd-operand-const-t32.cc | 120 M(Mvn) \
564 #include "aarch32/traces/simulator-cond-rd-operand-const-mvn-t32.h"
[all...] |
| test-simulator-cond-rd-operand-rn-a32.cc | 120 M(Mvn) \
479 #include "aarch32/traces/simulator-cond-rd-operand-rn-mvn-a32.h"
|
| test-simulator-cond-rd-operand-rn-t32.cc | 120 M(Mvn) \
479 #include "aarch32/traces/simulator-cond-rd-operand-rn-mvn-t32.h"
|
| test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc | 120 M(Mvn) \
[all...] |
| test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc | 120 M(Mvn) \
[all...] |
| test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc | 120 M(Mvn) \
[all...] |
| test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc | 120 M(Mvn) \
[all...] |
| test-simulator-cond-rd-operand-rn-shift-rs-a32.cc | 120 M(Mvn) \
[all...] |
| /external/vixl/src/aarch64/ |
| macro-assembler-aarch64.cc | 859 Mvn(rd, rn);
928 // could also be achieved using an orr instruction (like orn used by Mvn),
[all...] |
| macro-assembler-aarch64.h | 702 void Mvn(const Register& rd, uint64_t imm) {
705 void Mvn(const Register& rd, const Operand& operand);
[all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceInstARM32.h | 407 Mvn,
[all...] |
| IceInstARM32.cpp | [all...] |
| /external/v8/src/arm64/ |
| macro-assembler-arm64.h | 258 inline void Mvn(const Register& rd, uint64_t imm);
259 void Mvn(const Register& rd, const Operand& operand);
[all...] |
| macro-assembler-arm64.cc | 112 Mvn(rd, rn);
260 // could also be achieved using an orr instruction (like orn used by Mvn),
296 void MacroAssembler::Mvn(const Register& rd, const Operand& operand) {
301 mvn(rd, rd);
312 mvn(rd, rd);
315 mvn(rd, operand);
[all...] |
| macro-assembler-arm64-inl.h | 287 void MacroAssembler::Mvn(const Register& rd, uint64_t imm) {
[all...] |
| /external/v8/src/compiler/arm64/ |
| code-generator-arm64.cc | [all...] |
| /external/vixl/test/aarch64/ |
| test-assembler-aarch64.cc | 414 TEST(mvn) {
418 __ Mvn(w0, 0xfff);
419 __ Mvn(x1, 0xfff);
420 __ Mvn(w2, Operand(w0, LSL, 1));
421 __ Mvn(x3, Operand(x1, LSL, 2));
422 __ Mvn(w4, Operand(w0, LSR, 3));
423 __ Mvn(x5, Operand(x1, LSR, 4));
424 __ Mvn(w6, Operand(w0, ASR, 11));
425 __ Mvn(x7, Operand(x1, ASR, 12));
426 __ Mvn(w8, Operand(w0, ROR, 13))
[all...] |
| test-disasm-aarch64.cc | 201 COMPARE_MACRO(Mvn(w0, Operand(0x101)), "mov w0, #0xfffffefe");
202 COMPARE_MACRO(Mvn(x1, Operand(0xfff1)), "mov x1, #0xffffffffffff000e");
203 COMPARE_MACRO(Mvn(w2, Operand(w3)), "mvn w2, w3");
204 COMPARE_MACRO(Mvn(x4, Operand(x5)), "mvn x4, x5");
205 COMPARE_MACRO(Mvn(w6, Operand(w7, LSL, 12)), "mvn w6, w7, lsl #12");
206 COMPARE_MACRO(Mvn(x8, Operand(x9, ASR, 63)), "mvn x8, x9, asr #63")
[all...] |
| /external/vixl/src/aarch32/ |
| macro-assembler-aarch32.h | [all...] |
| /art/compiler/optimizing/ |
| code_generator_arm_vixl.cc | [all...] |
| code_generator_arm64.cc | [all...] |
