1 /*++ 2 3 Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved 4 5 This program and the accompanying materials are licensed and made available under 6 the terms and conditions of the BSD License that accompanies this distribution. 7 The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php. 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 13 14 15 Module Name: 16 17 PchRegsLpss.h 18 19 Abstract: 20 21 Register names for VLV Low Input Output (LPSS) module. 22 23 Conventions: 24 25 - Prefixes: 26 Definitions beginning with "R_" are registers 27 Definitions beginning with "B_" are bits within registers 28 Definitions beginning with "V_" are meaningful values of bits within the registers 29 Definitions beginning with "S_" are register sizes 30 Definitions beginning with "N_" are the bit position 31 - In general, PCH registers are denoted by "_PCH_" in register names 32 - Registers / bits that are different between PCH generations are denoted by 33 "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_" 34 - Registers / bits that are different between SKUs are denoted by "_<SKU_name>" 35 at the end of the register/bit names 36 - Registers / bits of new devices introduced in a PCH generation will be just named 37 as "_PCH_" without <generation_name> inserted. 38 39 --*/ 40 #ifndef _PCH_REGS_LPSS_H_ 41 #define _PCH_REGS_LPSS_H_ 42 43 44 // 45 // Low Power Input Output (LPSS) Module Registers 46 // 47 48 // 49 // LPSS DMAC Modules 50 // PCI Config Space Registers 51 // 52 #define PCI_DEVICE_NUMBER_PCH_LPSS_DMAC0 30 53 #define PCI_DEVICE_NUMBER_PCH_LPSS_DMAC1 24 54 #define PCI_FUNCTION_NUMBER_PCH_LPSS_DMAC 0 55 56 #define R_PCH_LPSS_DMAC_DEVVENDID 0x00 // Device ID & Vendor ID 57 #define B_PCH_LPSS_DMAC_DEVVENDID_DID 0xFFFF0000 // Device ID 58 #define B_PCH_LPSS_DMAC_DEVVENDID_VID 0x0000FFFF // Vendor ID 59 60 #define R_PCH_LPSS_DMAC_STSCMD 0x04 // Status & Command 61 #define B_PCH_LPSS_DMAC_STSCMD_RMA BIT29 // RMA 62 #define B_PCH_LPSS_DMAC_STSCMD_RCA BIT28 // RCA 63 #define B_PCH_LPSS_DMAC_STSCMD_CAPLIST BIT20 // Capability List 64 #define B_PCH_LPSS_DMAC_STSCMD_INTRSTS BIT19 // Interrupt Status 65 #define B_PCH_LPSS_DMAC_STSCMD_INTRDIS BIT10 // Interrupt Disable 66 #define B_PCH_LPSS_DMAC_STSCMD_SERREN BIT8 // SERR# Enable 67 #define B_PCH_LPSS_DMAC_STSCMD_BME BIT2 // Bus Master Enable 68 #define B_PCH_LPSS_DMAC_STSCMD_MSE BIT1 // Memory Space Enable 69 70 #define R_PCH_LPSS_DMAC_REVCC 0x08 // Revision ID & Class Code 71 #define B_PCH_LPSS_DMAC_REVCC_CC 0xFFFFFF00 // Class Code 72 #define B_PCH_LPSS_DMAC_REVCC_RID 0x000000FF // Revision ID 73 74 #define R_PCH_LPSS_DMAC_CLHB 0x0C 75 #define B_PCH_LPSS_DMAC_CLHB_MULFNDEV BIT23 76 #define B_PCH_LPSS_DMAC_CLHB_HT 0x007F0000 // Header Type 77 #define B_PCH_LPSS_DMAC_CLHB_LT 0x0000FF00 // Latency Timer 78 #define B_PCH_LPSS_DMAC_CLHB_CLS 0x000000FF // Cache Line Size 79 80 #define R_PCH_LPSS_DMAC_BAR 0x10 // BAR 81 #define B_PCH_LPSS_DMAC_BAR_BA 0xFFFFC000 // Base Address 82 #define V_PCH_LPSS_DMAC_BAR_SIZE 0x4000 83 #define N_PCH_LPSS_DMAC_BAR_ALIGNMENT 14 84 #define B_PCH_LPSS_DMAC_BAR_SI 0x00000FF0 // Size Indicator 85 #define B_PCH_LPSS_DMAC_BAR_PF BIT3 // Prefetchable 86 #define B_PCH_LPSS_DMAC_BAR_TYPE (BIT2 | BIT1) // Type 87 #define B_PCH_LPSS_DMAC_BAR_MS BIT0 // Message Space 88 89 #define R_PCH_LPSS_DMAC_BAR1 0x14 // BAR 1 90 #define B_PCH_LPSS_DMAC_BAR1_BA 0xFFFFF000 // Base Address 91 #define B_PCH_LPSS_DMAC_BAR1_SI 0x00000FF0 // Size Indicator 92 #define B_PCH_LPSS_DMAC_BAR1_PF BIT3 // Prefetchable 93 #define B_PCH_LPSS_DMAC_BAR1_TYPE (BIT2 | BIT1) // Type 94 #define B_PCH_LPSS_DMAC_BAR1_MS BIT0 // Message Space 95 96 #define R_PCH_LPSS_DMAC_SSID 0x2C // Sub System ID 97 #define B_PCH_LPSS_DMAC_SSID_SID 0xFFFF0000 // Sub System ID 98 #define B_PCH_LPSS_DMAC_SSID_SVID 0x0000FFFF // Sub System Vendor ID 99 100 #define R_PCH_LPSS_DMAC_ERBAR 0x30 // Expansion ROM BAR 101 #define B_PCH_LPSS_DMAC_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address 102 103 #define R_PCH_LPSS_DMAC_CAPPTR 0x34 // Capability Pointer 104 #define B_PCH_LPSS_DMAC_CAPPTR_CPPWR 0xFF // Capability Pointer Power 105 106 #define R_PCH_LPSS_DMAC_INTR 0x3C // Interrupt 107 #define B_PCH_LPSS_DMAC_INTR_ML 0xFF000000 // Max Latency 108 #define B_PCH_LPSS_DMAC_INTR_MG 0x00FF0000 109 #define B_PCH_LPSS_DMAC_INTR_IP 0x00000F00 // Interrupt Pin 110 #define B_PCH_LPSS_DMAC_INTR_IL 0x000000FF // Interrupt Line 111 112 #define R_PCH_LPSS_DMAC_PCAPID 0x80 // Power Capability ID 113 #define B_PCH_LPSS_DMAC_PCAPID_PS 0xF8000000 // PME Support 114 #define B_PCH_LPSS_DMAC_PCAPID_VS 0x00070000 // Version 115 #define B_PCH_LPSS_DMAC_PCAPID_NC 0x0000FF00 // Next Capability 116 #define B_PCH_LPSS_DMAC_PCAPID_PC 0x000000FF // Power Capability 117 118 #define R_PCH_LPSS_DMAC_PCS 0x84 // PME Control Status 119 #define B_PCH_LPSS_DMAC_PCS_PMESTS BIT15 // PME Status 120 #define B_PCH_LPSS_DMAC_PCS_PMEEN BIT8 // PME Enable 121 #define B_PCH_LPSS_DMAC_PCS_NSS BIT3 // No Soft Reset 122 #define B_PCH_LPSS_DMAC_PCS_PS (BIT1 | BIT0) // Power State 123 124 #define R_PCH_LPSS_DMAC_MANID 0xF8 // Manufacturer ID 125 #define B_PCH_LPSS_DMAC_MANID_MANID 0xFFFFFFFF // Manufacturer ID 126 127 128 // 129 // LPSS I2C Module 130 // PCI Config Space Registers 131 // 132 #define PCI_DEVICE_NUMBER_PCH_LPSS_I2C 24 133 #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C0 1 134 #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C1 2 135 #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C2 3 136 #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C3 4 137 #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C4 5 138 #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C5 6 139 #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C6 7 140 141 #define R_PCH_LPSS_I2C_DEVVENDID 0x00 // Device ID & Vendor ID 142 #define B_PCH_LPSS_I2C_DEVVENDID_DID 0xFFFF0000 // Device ID 143 #define B_PCH_LPSS_I2C_DEVVENDID_VID 0x0000FFFF // Vendor ID 144 145 #define R_PCH_LPSS_I2C_STSCMD 0x04 // Status & Command 146 #define B_PCH_LPSS_I2C_STSCMD_RMA BIT29 // RMA 147 #define B_PCH_LPSS_I2C_STSCMD_RCA BIT28 // RCA 148 #define B_PCH_LPSS_I2C_STSCMD_CAPLIST BIT20 // Capability List 149 #define B_PCH_LPSS_I2C_STSCMD_INTRSTS BIT19 // Interrupt Status 150 #define B_PCH_LPSS_I2C_STSCMD_INTRDIS BIT10 // Interrupt Disable 151 #define B_PCH_LPSS_I2C_STSCMD_SERREN BIT8 // SERR# Enable 152 #define B_PCH_LPSS_I2C_STSCMD_BME BIT2 // Bus Master Enable 153 #define B_PCH_LPSS_I2C_STSCMD_MSE BIT1 // Memory Space Enable 154 155 #define R_PCH_LPSS_I2C_REVCC 0x08 // Revision ID & Class Code 156 #define B_PCH_LPSS_I2C_REVCC_CC 0xFFFFFF00 // Class Code 157 #define B_PCH_LPSS_I2C_REVCC_RID 0x000000FF // Revision ID 158 159 #define R_PCH_LPSS_I2C_CLHB 0x0C 160 #define B_PCH_LPSS_I2C_CLHB_MULFNDEV BIT23 161 #define B_PCH_LPSS_I2C_CLHB_HT 0x007F0000 // Header Type 162 #define B_PCH_LPSS_I2C_CLHB_LT 0x0000FF00 // Latency Timer 163 #define B_PCH_LPSS_I2C_CLHB_CLS 0x000000FF // Cache Line Size 164 165 #define R_PCH_LPSS_I2C_BAR 0x10 // BAR 166 #define B_PCH_LPSS_I2C_BAR_BA 0xFFFFF000 // Base Address 167 #define V_PCH_LPSS_I2C_BAR_SIZE 0x1000 168 #define N_PCH_LPSS_I2C_BAR_ALIGNMENT 12 169 #define B_PCH_LPSS_I2C_BAR_SI 0x00000FF0 // Size Indicator 170 #define B_PCH_LPSS_I2C_BAR_PF BIT3 // Prefetchable 171 #define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 | BIT1) // Type 172 #define B_PCH_LPSS_I2C_BAR_MS BIT0 // Message Space 173 174 #define R_PCH_LPSS_I2C_BAR1 0x14 // BAR 1 175 #define B_PCH_LPSS_I2C_BAR1_BA 0xFFFFF000 // Base Address 176 #define B_PCH_LPSS_I2C_BAR1_SI 0x00000FF0 // Size Indicator 177 #define B_PCH_LPSS_I2C_BAR1_PF BIT3 // Prefetchable 178 #define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 | BIT1) // Type 179 #define B_PCH_LPSS_I2C_BAR1_MS BIT0 // Message Space 180 181 #define R_PCH_LPSS_I2C_SSID 0x2C // Sub System ID 182 #define B_PCH_LPSS_I2C_SSID_SID 0xFFFF0000 // Sub System ID 183 #define B_PCH_LPSS_I2C_SSID_SVID 0x0000FFFF // Sub System Vendor ID 184 185 #define R_PCH_LPSS_I2C_ERBAR 0x30 // Expansion ROM BAR 186 #define B_PCH_LPSS_I2C_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address 187 188 #define R_PCH_LPSS_I2C_CAPPTR 0x34 // Capability Pointer 189 #define B_PCH_LPSS_I2C_CAPPTR_CPPWR 0xFF // Capability Pointer Power 190 191 #define R_PCH_LPSS_I2C_INTR 0x3C // Interrupt 192 #define B_PCH_LPSS_I2C_INTR_ML 0xFF000000 // Max Latency 193 #define B_PCH_LPSS_I2C_INTR_MG 0x00FF0000 194 #define B_PCH_LPSS_I2C_INTR_IP 0x00000F00 // Interrupt Pin 195 #define B_PCH_LPSS_I2C_INTR_IL 0x000000FF // Interrupt Line 196 197 #define R_PCH_LPSS_I2C_PCAPID 0x80 // Power Capability ID 198 #define B_PCH_LPSS_I2C_PCAPID_PS 0xF8000000 // PME Support 199 #define B_PCH_LPSS_I2C_PCAPID_VS 0x00070000 // Version 200 #define B_PCH_LPSS_I2C_PCAPID_NC 0x0000FF00 // Next Capability 201 #define B_PCH_LPSS_I2C_PCAPID_PC 0x000000FF // Power Capability 202 203 #define R_PCH_LPSS_I2C_PCS 0x84 // PME Control Status 204 #define B_PCH_LPSS_I2C_PCS_PMESTS BIT15 // PME Status 205 #define B_PCH_LPSS_I2C_PCS_PMEEN BIT8 // PME Enable 206 #define B_PCH_LPSS_I2C_PCS_NSS BIT3 // No Soft Reset 207 #define B_PCH_LPSS_I2C_PCS_PS (BIT1 | BIT0) // Power State 208 209 #define R_PCH_LPSS_I2C_MANID 0xF8 // Manufacturer ID 210 #define B_PCH_LPSS_I2C_MANID_MANID 0xFFFFFFFF // Manufacturer ID 211 212 // 213 // LPSS I2C Module 214 // Memory Space Registers 215 // 216 #define R_PCH_LPSS_I2C_MEM_RESETS 0x804 // Software Reset 217 #define B_PCH_LPSS_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset 218 #define B_PCH_LPSS_I2C_MEM_RESETS_APB BIT0 // APB Domain Reset 219 220 // 221 // LPSS PWM Modules 222 // PCI Config Space Registers 223 // 224 #define PCI_DEVICE_NUMBER_PCH_LPSS_PWM 30 225 #define PCI_FUNCTION_NUMBER_PCH_LPSS_PWM0 1 226 #define PCI_FUNCTION_NUMBER_PCH_LPSS_PWM1 2 227 228 #define R_PCH_LPSS_PWM_DEVVENDID 0x00 // Device ID & Vendor ID 229 #define B_PCH_LPSS_PWM_DEVVENDID_DID 0xFFFF0000 // Device ID 230 #define B_PCH_LPSS_PWM_DEVVENDID_VID 0x0000FFFF // Vendor ID 231 232 #define R_PCH_LPSS_PWM_STSCMD 0x04 // Status & Command 233 #define B_PCH_LPSS_PWM_STSCMD_RMA BIT29 // RMA 234 #define B_PCH_LPSS_PWM_STSCMD_RCA BIT28 // RCA 235 #define B_PCH_LPSS_PWM_STSCMD_CAPLIST BIT20 // Capability List 236 #define B_PCH_LPSS_PWM_STSCMD_INTRSTS BIT19 // Interrupt Status 237 #define B_PCH_LPSS_PWM_STSCMD_INTRDIS BIT10 // Interrupt Disable 238 #define B_PCH_LPSS_PWM_STSCMD_SERREN BIT8 // SERR# Enable 239 #define B_PCH_LPSS_PWM_STSCMD_BME BIT2 // Bus Master Enable 240 #define B_PCH_LPSS_PWM_STSCMD_MSE BIT1 // Memory Space Enable 241 242 #define R_PCH_LPSS_PWM_REVCC 0x08 // Revision ID & Class Code 243 #define B_PCH_LPSS_PWM_REVCC_CC 0xFFFFFF00 // Class Code 244 #define B_PCH_LPSS_PWM_REVCC_RID 0x000000FF // Revision ID 245 246 #define R_PCH_LPSS_PWM_CLHB 0x0C 247 #define B_PCH_LPSS_PWM_CLHB_MULFNDEV BIT23 248 #define B_PCH_LPSS_PWM_CLHB_HT 0x007F0000 // Header Type 249 #define B_PCH_LPSS_PWM_CLHB_LT 0x0000FF00 // Latency Timer 250 #define B_PCH_LPSS_PWM_CLHB_CLS 0x000000FF // Cache Line Size 251 252 #define R_PCH_LPSS_PWM_BAR 0x10 // BAR 253 #define B_PCH_LPSS_PWM_BAR_BA 0xFFFFF000 // Base Address 254 #define V_PCH_LPSS_PWM_BAR_SIZE 0x1000 255 #define N_PCH_LPSS_PWM_BAR_ALIGNMENT 12 256 #define B_PCH_LPSS_PWM_BAR_SI 0x00000FF0 // Size Indicator 257 #define B_PCH_LPSS_PWM_BAR_PF BIT3 // Prefetchable 258 #define B_PCH_LPSS_PWM_BAR_TYPE (BIT2 | BIT1) // Type 259 #define B_PCH_LPSS_PWM_BAR_MS BIT0 // Message Space 260 261 #define R_PCH_LPSS_PWM_BAR1 0x14 // BAR 1 262 #define B_PCH_LPSS_PWM_BAR1_BA 0xFFFFF000 // Base Address 263 #define B_PCH_LPSS_PWM_BAR1_SI 0x00000FF0 // Size Indicator 264 #define B_PCH_LPSS_PWM_BAR1_PF BIT3 // Prefetchable 265 #define B_PCH_LPSS_PWM_BAR1_TYPE (BIT2 | BIT1) // Type 266 #define B_PCH_LPSS_PWM_BAR1_MS BIT0 // Message Space 267 268 #define R_PCH_LPSS_PWM_SSID 0x2C // Sub System ID 269 #define B_PCH_LPSS_PWM_SSID_SID 0xFFFF0000 // Sub System ID 270 #define B_PCH_LPSS_PWM_SSID_SVID 0x0000FFFF // Sub System Vendor ID 271 272 #define R_PCH_LPSS_PWM_ERBAR 0x30 // Expansion ROM BAR 273 #define B_PCH_LPSS_PWM_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address 274 275 #define R_PCH_LPSS_PWM_CAPPTR 0x34 // Capability Pointer 276 #define B_PCH_LPSS_PWM_CAPPTR_CPPWR 0xFF // Capability Pointer Power 277 278 #define R_PCH_LPSS_PWM_INTR 0x3C // Interrupt 279 #define B_PCH_LPSS_PWM_INTR_ML 0xFF000000 // Max Latency 280 #define B_PCH_LPSS_PWM_INTR_MG 0x00FF0000 281 #define B_PCH_LPSS_PWM_INTR_IP 0x00000F00 // Interrupt Pin 282 #define B_PCH_LPSS_PWM_INTR_IL 0x000000FF // Interrupt Line 283 284 #define R_PCH_LPSS_PWM_PCAPID 0x80 // Power Capability ID 285 #define B_PCH_LPSS_PWM_PCAPID_PS 0xF8000000 // PME Support 286 #define B_PCH_LPSS_PWM_PCAPID_VS 0x00070000 // Version 287 #define B_PCH_LPSS_PWM_PCAPID_NC 0x0000FF00 // Next Capability 288 #define B_PCH_LPSS_PWM_PCAPID_PC 0x000000FF // Power Capability 289 290 #define R_PCH_LPSS_PWM_PCS 0x84 // PME Control Status 291 #define B_PCH_LPSS_PWM_PCS_PMESTS BIT15 // PME Status 292 #define B_PCH_LPSS_PWM_PCS_PMEEN BIT8 // PME Enable 293 #define B_PCH_LPSS_PWM_PCS_NSS BIT3 // No Soft Reset 294 #define B_PCH_LPSS_PWM_PCS_PS (BIT1 | BIT0) // Power State 295 296 #define R_PCH_LPSS_PWM_MANID 0xF8 // Manufacturer ID 297 #define B_PCH_LPSS_PWM_MANID_MANID 0xFFFFFFFF // Manufacturer ID 298 299 // 300 // LPSS PWM Module 301 // Memory Space Registers 302 // 303 #define R_PCH_LPSS_PWM_MEM_RESETS 0x804 // Software Reset 304 #define B_PCH_LPSS_PWM_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset 305 #define B_PCH_LPSS_PWM_MEM_RESETS_APB BIT0 // APB Domain Reset 306 307 // 308 // LPSS HSUART Modules 309 // PCI Config Space Registers 310 // 311 #define PCI_DEVICE_NUMBER_PCH_LPSS_HSUART 30 312 #define PCI_FUNCTION_NUMBER_PCH_LPSS_HSUART0 3 313 #define PCI_FUNCTION_NUMBER_PCH_LPSS_HSUART1 4 314 315 #define R_PCH_LPSS_HSUART_DEVVENDID 0x00 // Device ID & Vendor ID 316 #define B_PCH_LPSS_HSUART_DEVVENDID_DID 0xFFFF0000 // Device ID 317 #define B_PCH_LPSS_HSUART_DEVVENDID_VID 0x0000FFFF // Vendor ID 318 319 #define R_PCH_LPSS_HSUART_STSCMD 0x04 // Status & Command 320 #define B_PCH_LPSS_HSUART_STSCMD_RMA BIT29 // RMA 321 #define B_PCH_LPSS_HSUART_STSCMD_RCA BIT28 // RCA 322 #define B_PCH_LPSS_HSUART_STSCMD_CAPLIST BIT20 // Capability List 323 #define B_PCH_LPSS_HSUART_STSCMD_INTRSTS BIT19 // Interrupt Status 324 #define B_PCH_LPSS_HSUART_STSCMD_INTRDIS BIT10 // Interrupt Disable 325 #define B_PCH_LPSS_HSUART_STSCMD_SERREN BIT8 // SERR# Enable 326 #define B_PCH_LPSS_HSUART_STSCMD_BME BIT2 // Bus Master Enable 327 #define B_PCH_LPSS_HSUART_STSCMD_MSE BIT1 // Memory Space Enable 328 329 #define R_PCH_LPSS_HSUART_REVCC 0x08 // Revision ID & Class Code 330 #define B_PCH_LPSS_HSUART_REVCC_CC 0xFFFFFF00 // Class Code 331 #define B_PCH_LPSS_HSUART_REVCC_RID 0x000000FF // Revision ID 332 333 #define R_PCH_LPSS_HSUART_CLHB 0x0C 334 #define B_PCH_LPSS_HSUART_CLHB_MULFNDEV BIT23 335 #define B_PCH_LPSS_HSUART_CLHB_HT 0x007F0000 // Header Type 336 #define B_PCH_LPSS_HSUART_CLHB_LT 0x0000FF00 // Latency Timer 337 #define B_PCH_LPSS_HSUART_CLHB_CLS 0x000000FF // Cache Line Size 338 339 #define R_PCH_LPSS_HSUART_BAR 0x10 // BAR 340 #define B_PCH_LPSS_HSUART_BAR_BA 0xFFFFF000 // Base Address 341 #define V_PCH_LPSS_HSUART_BAR_SIZE 0x1000 342 #define N_PCH_LPSS_HSUART_BAR_ALIGNMENT 12 343 #define B_PCH_LPSS_HSUART_BAR_SI 0x00000FF0 // Size Indicator 344 #define B_PCH_LPSS_HSUART_BAR_PF BIT3 // Prefetchable 345 #define B_PCH_LPSS_HSUART_BAR_TYPE (BIT2 | BIT1) // Type 346 #define B_PCH_LPSS_HSUART_BAR_MS BIT0 // Message Space 347 348 #define R_PCH_LPSS_HSUART_BAR1 0x14 // BAR 1 349 #define B_PCH_LPSS_HSUART_BAR1_BA 0xFFFFF000 // Base Address 350 #define B_PCH_LPSS_HSUART_BAR1_SI 0x00000FF0 // Size Indicator 351 #define B_PCH_LPSS_HSUART_BAR1_PF BIT3 // Prefetchable 352 #define B_PCH_LPSS_HSUART_BAR1_TYPE (BIT2 | BIT1) // Type 353 #define B_PCH_LPSS_HSUART_BAR1_MS BIT0 // Message Space 354 355 #define R_PCH_LPSS_HSUART_SSID 0x2C // Sub System ID 356 #define B_PCH_LPSS_HSUART_SSID_SID 0xFFFF0000 // Sub System ID 357 #define B_PCH_LPSS_HSUART_SSID_SVID 0x0000FFFF // Sub System Vendor ID 358 359 #define R_PCH_LPSS_HSUART_ERBAR 0x30 // Expansion ROM BAR 360 #define B_PCH_LPSS_HSUART_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address 361 362 #define R_PCH_LPSS_HSUART_CAPPTR 0x34 // Capability Pointer 363 #define B_PCH_LPSS_HSUART_CAPPTR_CPPWR 0xFF // Capability Pointer Power 364 365 #define R_PCH_LPSS_HSUART_INTR 0x3C // Interrupt 366 #define B_PCH_LPSS_HSUART_INTR_ML 0xFF000000 // Max Latency 367 #define B_PCH_LPSS_HSUART_INTR_MG 0x00FF0000 368 #define B_PCH_LPSS_HSUART_INTR_IP 0x00000F00 // Interrupt Pin 369 #define B_PCH_LPSS_HSUART_INTR_IL 0x000000FF // Interrupt Line 370 371 #define R_PCH_LPSS_HSUART_PCAPID 0x80 // Power Capability ID 372 #define B_PCH_LPSS_HSUART_PCAPID_PS 0xF8000000 // PME Support 373 #define B_PCH_LPSS_HSUART_PCAPID_VS 0x00070000 // Version 374 #define B_PCH_LPSS_HSUART_PCAPID_NC 0x0000FF00 // Next Capability 375 #define B_PCH_LPSS_HSUART_PCAPID_PC 0x000000FF // Power Capability 376 377 #define R_PCH_LPSS_HSUART_PCS 0x84 // PME Control Status 378 #define B_PCH_LPSS_HSUART_PCS_PMESTS BIT15 // PME Status 379 #define B_PCH_LPSS_HSUART_PCS_PMEEN BIT8 // PME Enable 380 #define B_PCH_LPSS_HSUART_PCS_NSS BIT3 // No Soft Reset 381 #define B_PCH_LPSS_HSUART_PCS_PS (BIT1 | BIT0) // Power State 382 383 #define R_PCH_LPSS_HSUART_MANID 0xF8 // Manufacturer ID 384 #define B_PCH_LPSS_HSUART_MANID_MANID 0xFFFFFFFF // Manufacturer ID 385 386 // 387 // LPSS HSUART Module 388 // Memory Space Registers 389 // 390 #define R_PCH_LPSS_HSUART_MEM_PCP 0x800 // Private Clock Parameters 391 #define B_PCH_LPSS_HSUART_MEM_PCP_CLKUPDATE BIT31 // Clock Divider Update 392 #define B_PCH_LPSS_HSUART_MEM_PCP_NVAL 0x7FFF0000 // N value for the M over N divider 393 #define B_PCH_LPSS_HSUART_MEM_PCP_MVAL 0x0000FFFE // M value for the M over N divider 394 #define B_PCH_LPSS_HSUART_MEM_PCP_CLKEN BIT0 // Clock Enable 395 396 #define R_PCH_LPSS_HSUART_MEM_RESETS 0x804 // Software Reset 397 #define B_PCH_LPSS_HSUART_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset 398 #define B_PCH_LPSS_HSUART_MEM_RESETS_APB BIT0 // APB Domain Reset 399 400 // 401 // LPSS SPI Module 402 // PCI Config Space Registers 403 // 404 #define PCI_DEVICE_NUMBER_PCH_LPSS_SPI 30 405 #define PCI_FUNCTION_NUMBER_PCH_LPSS_SPI 5 406 407 #define R_PCH_LPSS_SPI_DEVVENDID 0x00 // Device ID & Vendor ID 408 #define B_PCH_LPSS_SPI_DEVVENDID_DID 0xFFFF0000 // Device ID 409 #define B_PCH_LPSS_SPI_DEVVENDID_VID 0x0000FFFF // Vendor ID 410 411 #define R_PCH_LPSS_SPI_STSCMD 0x04 // Status & Command 412 #define B_PCH_LPSS_SPI_STSCMD_RMA BIT29 // RMA 413 #define B_PCH_LPSS_SPI_STSCMD_RCA BIT28 // RCA 414 #define B_PCH_LPSS_SPI_STSCMD_CAPLIST BIT20 // Capability List 415 #define B_PCH_LPSS_SPI_STSCMD_INTRSTS BIT19 // Interrupt Status 416 #define B_PCH_LPSS_SPI_STSCMD_INTRDIS BIT10 // Interrupt Disable 417 #define B_PCH_LPSS_SPI_STSCMD_SERREN BIT8 // SERR# Enable 418 #define B_PCH_LPSS_SPI_STSCMD_BME BIT2 // Bus Master Enable 419 #define B_PCH_LPSS_SPI_STSCMD_MSE BIT1 // Memory Space Enable 420 421 #define R_PCH_LPSS_SPI_REVCC 0x08 // Revision ID & Class Code 422 #define B_PCH_LPSS_SPI_REVCC_CC 0xFFFFFF00 // Class Code 423 #define B_PCH_LPSS_SPI_REVCC_RID 0x000000FF // Revision ID 424 425 #define R_PCH_LPSS_SPI_CLHB 0x0C 426 #define B_PCH_LPSS_SPI_CLHB_MULFNDEV BIT23 427 #define B_PCH_LPSS_SPI_CLHB_HT 0x007F0000 // Header Type 428 #define B_PCH_LPSS_SPI_CLHB_LT 0x0000FF00 // Latency Timer 429 #define B_PCH_LPSS_SPI_CLHB_CLS 0x000000FF // Cache Line Size 430 431 #define R_PCH_LPSS_SPI_BAR 0x10 // BAR 432 #define B_PCH_LPSS_SPI_BAR_BA 0xFFFFF000 // Base Address 433 #define V_PCH_LPSS_SPI_BAR_SIZE 0x1000 434 #define N_PCH_LPSS_SPI_BAR_ALIGNMENT 12 435 #define B_PCH_LPSS_SPI_BAR_SI 0x00000FF0 // Size Indicator 436 #define B_PCH_LPSS_SPI_BAR_PF BIT3 // Prefetchable 437 #define B_PCH_LPSS_SPI_BAR_TYPE (BIT2 | BIT1) // Type 438 #define B_PCH_LPSS_SPI_BAR_MS BIT0 // Message Space 439 440 #define R_PCH_LPSS_SPI_BAR1 0x14 // BAR 1 441 #define B_PCH_LPSS_SPI_BAR1_BA 0xFFFFF000 // Base Address 442 #define B_PCH_LPSS_SPI_BAR1_SI 0x00000FF0 // Size Indicator 443 #define B_PCH_LPSS_SPI_BAR1_PF BIT3 // Prefetchable 444 #define B_PCH_LPSS_SPI_BAR1_TYPE (BIT2 | BIT1) // Type 445 #define B_PCH_LPSS_SPI_BAR1_MS BIT0 // Message Space 446 447 #define R_PCH_LPSS_SPI_SSID 0x2C // Sub System ID 448 #define B_PCH_LPSS_SPI_SSID_SID 0xFFFF0000 // Sub System ID 449 #define B_PCH_LPSS_SPI_SSID_SVID 0x0000FFFF // Sub System Vendor ID 450 451 #define R_PCH_LPSS_SPI_ERBAR 0x30 // Expansion ROM BAR 452 #define B_PCH_LPSS_SPI_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address 453 454 #define R_PCH_LPSS_SPI_CAPPTR 0x34 // Capability Pointer 455 #define B_PCH_LPSS_SPI_CAPPTR_CPPWR 0xFF // Capability Pointer Power 456 457 #define R_PCH_LPSS_SPI_INTR 0x3C // Interrupt 458 #define B_PCH_LPSS_SPI_INTR_ML 0xFF000000 // Max Latency 459 #define B_PCH_LPSS_SPI_INTR_MG 0x00FF0000 460 #define B_PCH_LPSS_SPI_INTR_IP 0x00000F00 // Interrupt Pin 461 #define B_PCH_LPSS_SPI_INTR_IL 0x000000FF // Interrupt Line 462 463 #define R_PCH_LPSS_SPI_PCAPID 0x80 // Power Capability ID 464 #define B_PCH_LPSS_SPI_PCAPID_PS 0xF8000000 // PME Support 465 #define B_PCH_LPSS_SPI_PCAPID_VS 0x00070000 // Version 466 #define B_PCH_LPSS_SPI_PCAPID_NC 0x0000FF00 // Next Capability 467 #define B_PCH_LPSS_SPI_PCAPID_PC 0x000000FF // Power Capability 468 469 #define R_PCH_LPSS_SPI_PCS 0x84 // PME Control Status 470 #define B_PCH_LPSS_SPI_PCS_PMESTS BIT15 // PME Status 471 #define B_PCH_LPSS_SPI_PCS_PMEEN BIT8 // PME Enable 472 #define B_PCH_LPSS_SPI_PCS_NSS BIT3 // No Soft Reset 473 #define B_PCH_LPSS_SPI_PCS_PS (BIT1 | BIT0) // Power State 474 475 #define R_PCH_LPSS_SPI_MANID 0xF8 // Manufacturer ID 476 #define B_PCH_LPSS_SPI_MANID_MANID 0xFFFFFFFF // Manufacturer ID 477 478 // 479 // LPSS SPI Module 480 // Memory Space Registers 481 // 482 #define R_PCH_LPSS_SPI_MEM_PCP 0x400 // Private Clock Parameters 483 #define B_PCH_LPSS_SPI_MEM_PCP_CLKUPDATE BIT31 // Clock Divider Update 484 #define B_PCH_LPSS_SPI_MEM_PCP_NVAL 0x7FFF0000 // N value for the M over N divider 485 #define B_PCH_LPSS_SPI_MEM_PCP_MVAL 0x0000FFFE // M value for the M over N divider 486 #define B_PCH_LPSS_SPI_MEM_PCP_CLKEN BIT0 // Clock Enable 487 488 #define R_PCH_LPSS_SPI_MEM_RESETS 0x404 // Software Reset 489 #define B_PCH_LPSS_SPI_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset 490 #define B_PCH_LPSS_SPI_MEM_RESETS_APB BIT0 // APB Domain Reset 491 492 #endif 493
