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  /device/linaro/bootloader/arm-trusted-firmware/services/spd/tlkd/
tlkd_common.c 25 /* save secure context */
26 cm_el1_sysregs_context_save(SECURE);
28 /* restore non-secure context */
31 /* switch NS bit to start using 64-bit, non-secure mappings */
58 /* Restore secure state */
61 /* restore secure context */
62 cm_el1_sysregs_context_restore(SECURE);
64 /* switch NS bit to start using 32-bit, secure mappings */
65 write_scr(cm_get_scr_el3(SECURE));
73 * Given a secure payload entrypoint, register width, cpu id & pointer to
    [all...]
tlkd_main.c 8 * This is the Secure Payload Dispatcher (SPD). The dispatcher is meant to be a
9 * plug-in component to the Secure Monitor, registered as a runtime service. The
10 * SPD is expected to be a functional extension of the Secure Payload (SP) that
11 * executes in Secure EL1. The Secure Monitor will delegate all SMCs targeting
13 * handle the request locally or delegate it to the Secure Payload. It is also
33 * Per-cpu Secure Payload state
50 * Secure Payload Dispatcher setup. The SPD finds out the SP entrypoint and type
59 * Get information about the Secure Payload (BL32) image. Its
62 tlk_ep_info = bl31_plat_get_next_image_ep_info(SECURE);
    [all...]
  /device/linaro/bootloader/arm-trusted-firmware/services/spd/tspd/
tspd_common.c 18 * Given a secure payload entrypoint info pointer, entry point PC, register
20 * initialize tsp context and entry point info for the secure payload
46 cm_set_context(&tsp_ctx->cpu_ctx, SECURE);
49 ep_attr = SECURE | EP_ST_ENABLE;
67 * from the tsp_ctx->cpu_ctx are used to enter the secure payload image.
76 /* Apply the Secure EL1 system register context and switch to it */
77 assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx);
78 cm_el1_sysregs_context_restore(SECURE);
79 cm_set_next_eret_context(SECURE);
101 /* Save the Secure EL1 system register context *
    [all...]
tspd_main.c 9 * This is the Secure Payload Dispatcher (SPD). The dispatcher is meant to be a
10 * plug-in component to the Secure Monitor, registered as a runtime service. The
11 * SPD is expected to be a functional extension of the Secure Payload (SP) that
12 * executes in Secure EL1. The Secure Monitor will delegate all SMCs targeting
14 * handle the request locally or delegate it to the Secure Payload. It is also
33 * Address of the entrypoint vector table in the Secure Payload. It is
39 * Array to keep track of per-cpu Secure Payload state
52 * This helper function handles Secure EL1 preemption. The preemption could be
53 * due Non Secure interrupts or EL3 interrupts. In both the cases we contex
    [all...]
tspd_pm.c 38 * Abort any preempted SMC request before overwriting the SECURE
44 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_off_entry);
77 * Abort any preempted SMC request before overwriting the SECURE
83 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_suspend_entry);
99 * before passing control back to the Secure Monitor. Entry in S-EL1 is done
118 /* Initialise this cpu's secure context */
126 disable_intr_rm_local(INTR_TYPE_NS, SECURE);
161 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_resume_entry);
197 * Abort any preempted SMC request before overwriting the SECURE
203 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_off_entry)
    [all...]
  /device/linaro/bootloader/arm-trusted-firmware/services/spd/opteed/
opteed_common.c 37 cm_set_context(&optee_ctx->cpu_ctx, SECURE);
40 ep_attr = SECURE | EP_ST_ENABLE;
75 /* Apply the Secure EL1 system register context and switch to it */
76 assert(cm_get_context(SECURE) == &optee_ctx->cpu_ctx);
77 cm_el1_sysregs_context_restore(SECURE);
78 cm_set_next_eret_context(SECURE);
100 /* Save the Secure EL1 system register context */
101 assert(cm_get_context(SECURE) == &optee_ctx->cpu_ctx);
102 cm_el1_sysregs_context_save(SECURE);
opteed_main.c 9 * This is the Secure Payload Dispatcher (SPD). The dispatcher is meant to be a
10 * plug-in component to the Secure Monitor, registered as a runtime service. The
11 * SPD is expected to be a functional extension of the Secure Payload (SP) that
12 * executes in Secure EL1. The Secure Monitor will delegate all SMCs targeting
14 * handle the request locally or delegate it to the Secure Payload. It is also
66 /* Save the non-secure context before entering the OPTEE */
72 assert(&optee_ctx->cpu_ctx == cm_get_context(SECURE));
74 cm_set_elr_el3(SECURE, (uint64_t)&optee_vectors->fiq_entry);
75 cm_el1_sysregs_context_restore(SECURE);
    [all...]
opteed_pm.c 37 cm_set_elr_el3(SECURE, (uint64_t) &optee_vectors->cpu_off_entry);
70 cm_set_elr_el3(SECURE, (uint64_t) &optee_vectors->cpu_suspend_entry);
86 * before passing control back to the Secure Monitor. Entry in S-El1 is done
104 /* Initialise this cpu's secure context */
139 cm_set_elr_el3(SECURE, (uint64_t) &optee_vectors->cpu_resume_entry);
175 cm_set_elr_el3(SECURE, (uint64_t) &optee_vectors->system_off_entry);
195 cm_set_elr_el3(SECURE, (uint64_t) &optee_vectors->system_reset_entry);
  /device/linaro/bootloader/arm-trusted-firmware/plat/arm/common/aarch64/
arm_bl2_mem_params_desc.c 28 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
46 SECURE | EXECUTABLE | EP_FIRST_EXE),
66 SECURE | EXECUTABLE | EP_FIRST_EXE),
92 VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
111 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
129 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
  /device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey/
hikey_bl2_mem_params_desc.c 28 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
46 SECURE | EXECUTABLE | EP_FIRST_EXE),
66 SECURE | EXECUTABLE | EP_FIRST_EXE),
92 VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
111 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
129 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
  /device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey960/
hikey960_bl2_mem_params_desc.c 28 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
46 SECURE | EXECUTABLE | EP_FIRST_EXE),
66 SECURE | EXECUTABLE | EP_FIRST_EXE),
92 VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
111 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
129 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
  /hardware/interfaces/memtrack/1.0/
types.hal 42 * NONSECURE/SECURE
43 * Flags to differentiate memory accessible by the CPU in non-secure mode vs.
45 * If none are set, record is assumed to count secure + nonsecure memory.
56 SECURE = 1 << 9,
  /device/linaro/bootloader/arm-trusted-firmware/bl1/tbbr/
tbbr_img_desc.c 21 VERSION_1, entry_point_info_t, SECURE),
41 VERSION_1, entry_point_info_t, SECURE),
54 VERSION_1, entry_point_info_t, SECURE | EXECUTABLE),
  /device/linaro/bootloader/arm-trusted-firmware/plat/qemu/
qemu_bl2_mem_params_desc.c 26 SECURE | EXECUTABLE | EP_FIRST_EXE),
42 SECURE | EXECUTABLE | EP_FIRST_EXE),
65 entry_point_info_t, SECURE | EXECUTABLE),
84 entry_point_info_t, SECURE | NON_EXECUTABLE),
102 entry_point_info_t, SECURE | NON_EXECUTABLE),
  /device/linaro/bootloader/arm-trusted-firmware/plat/arm/board/common/aarch64/
board_arm_helpers.S 26 mov x2, #(SECURE << V2M_SYS_LED_SS_SHIFT)
  /device/linaro/bootloader/arm-trusted-firmware/include/plat/common/
common_def.h 41 VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),\
51 VERSION_1, entry_point_info_t, SECURE | EXECUTABLE),\
  /device/linaro/bootloader/arm-trusted-firmware/plat/arm/common/aarch32/
arm_bl2_mem_params_desc.c 28 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
45 SECURE | EXECUTABLE | EP_FIRST_EXE),
  /device/linaro/bootloader/arm-trusted-firmware/bl1/
bl1_fwu.c 48 * This keeps track of last executed secure image id.
219 * This function is responsible for copying secure images in AP Secure RAM.
238 * The request must originate from a non-secure caller and target a
239 * secure image. Any other scenario is invalid.
241 if (GET_SECURITY_STATE(flags) == SECURE) {
242 WARN("BL1-FWU: Copy not allowed from secure world.\n");
246 WARN("BL1-FWU: Copy not allowed for non-secure images.\n");
367 * This function is responsible for authenticating Normal/Secure images.
383 if (GET_SECURITY_STATE(flags) == SECURE) {
    [all...]
  /device/linaro/bootloader/arm-trusted-firmware/plat/socionext/uniphier/
uniphier_image_desc.c 39 SECURE | EXECUTABLE | EP_FIRST_EXE),
61 SECURE | EXECUTABLE),
  /packages/apps/Settings/src/com/android/settings/search/
ResultPayload.java 116 @IntDef({SettingsSource.UNKNOWN, SettingsSource.SYSTEM, SettingsSource.SECURE,
122 int SECURE = 2;
  /packages/apps/SettingsIntelligence/src/com/android/settings/intelligence/search/
ResultPayload.java 116 @IntDef({SettingsSource.UNKNOWN, SettingsSource.SYSTEM, SettingsSource.SECURE,
122 int SECURE = 2;
  /device/linaro/bootloader/arm-trusted-firmware/services/spd/trusty/
trusty.c 232 entry_point_info_t *ep_info = bl31_plat_get_next_image_ep_info(SECURE);
247 ret = trusty_context_switch(SECURE, x1, 0, 0, 0);
299 ep_info = bl31_plat_get_next_image_ep_info(SECURE);
304 cm_set_context(&ctx->cpu_ctx, SECURE);
314 cm_set_elr_el3(SECURE, ep_info->pc + (1U << 5));
317 cm_el1_sysregs_context_restore(SECURE);
318 cm_set_next_eret_context(SECURE);
395 ep_info = bl31_plat_get_next_image_ep_info(SECURE);
402 SET_PARAM_HEAD(ep_info, PARAM_EP, VERSION_1, SECURE | EP_ST_ENABLE);
  /packages/apps/Settings/tests/robotests/src/com/android/settings/search/
InlinePayloadTest.java 33 InlinePayload payload = getDummyPayload(SettingsSource.SECURE);
35 Settings.Secure.putInt(mContext.getContentResolver(), KEY, currentValue);
66 InlinePayload payload = getDummyPayload(SettingsSource.SECURE);
69 Settings.Secure.putInt(resolver, KEY, 0);
92 InlinePayload payload = getDummyPayload(SettingsSource.SECURE);
  /device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/
plat_memctrl.c 100 mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE),
103 mc_make_sec_cfg(GPUSWR2, SECURE, NO_OVERRIDE, DISABLE),
115 mc_make_sec_cfg(GPUSRD, SECURE, NO_OVERRIDE, DISABLE),
125 mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE),
156 mc_make_sec_cfg(GPUSWR, SECURE, NO_OVERRIDE, DISABLE),
159 mc_make_sec_cfg(GPUSRD2, SECURE, NO_OVERRIDE, DISABLE),
  /device/linaro/bootloader/arm-trusted-firmware/include/common/
ep_info.h 13 #define SECURE U(0x0)
15 #define sec_state_is_valid(s) (((s) == SECURE) || ((s) == NON_SECURE))

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