| /external/libchrome/base/numerics/ |
| safe_math_impl.h | 308 using ShiftType = typename std::make_unsigned<T>::type;
309 static const ShiftType kBitWidth = IntegerBitsPlusSign<T>::value;
310 const ShiftType real_shift = static_cast<ShiftType>(shift);
338 using ShiftType = typename std::make_unsigned<T>::type;
339 if (static_cast<ShiftType>(shift) < IntegerBitsPlusSign<T>::value) {
|
| /external/pdfium/third_party/base/numerics/ |
| safe_math_impl.h | 309 using ShiftType = typename std::make_unsigned<T>::type;
310 static const ShiftType kBitWidth = IntegerBitsPlusSign<T>::value;
311 const auto real_shift = static_cast<ShiftType>(shift);
339 using ShiftType = typename std::make_unsigned<T>::type;
340 if (static_cast<ShiftType>(shift) < IntegerBitsPlusSign<T>::value) {
|
| /external/vixl/src/aarch32/ |
| instructions-aarch32.h | [all...] |
| /art/compiler/optimizing/ |
| code_generator_arm_vixl.cc | [all...] |
| code_generator_vector_arm_vixl.cc | 848 __ Add(*scratch, base, Operand(RegisterFrom(index), ShiftType::LSL, shift));
875 __ Add(*scratch, *scratch, Operand(RegisterFrom(index), ShiftType::LSL, shift));
[all...] |
| /external/vixl/tools/ |
| generate_tests.py | 156 "Register", "uint32_t", "ShiftType", ...etc.
250 ShiftType type = ...;
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 90 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
333 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
708 if (Memory.ShiftType != ARM_AM::no_shift) return false;
740 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
746 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
761 if (Memory.ShiftType == ARM_AM::no_shift)
763 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
771 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
[all...] |
| /external/vixl/tools/test_generator/ |
| data_types.py | 35 to represent it (e.g. "Register", "ShiftType", "MemOperand", ...) and a name
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 169 AArch64_AM::ShiftExtendType ShiftType,
201 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
[all...] |
| /external/vixl/test/aarch32/ |
| test-assembler-cond-rd-operand-rn-shift-rs-narrow-out-it-block-t32.cc | 68 ShiftType shift;
378 ShiftType shift = kTests[i].operands.shift;
|
| test-simulator-cond-rd-operand-rn-ror-amount-a32.cc | 139 ShiftType ror;
597 ShiftType ror = kTests[i].operands.ror;
[all...] |
| test-simulator-cond-rd-operand-rn-ror-amount-t32.cc | 139 ShiftType ror;
597 ShiftType ror = kTests[i].operands.ror;
[all...] |
| test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc | 141 ShiftType shift;
[all...] |
| test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc | 141 ShiftType shift;
[all...] |
| test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc | 141 ShiftType shift;
[all...] |
| test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc | 141 ShiftType shift;
[all...] |
| test-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc | 76 ShiftType shift;
[all...] |
| test-assembler-cond-rd-operand-rn-shift-amount-1to32-in-it-block-t32.cc | 68 ShiftType shift;
[all...] |
| test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc | 76 ShiftType shift;
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 89 ShiftType shift;
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 89 ShiftType shift;
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 89 ShiftType shift;
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 89 ShiftType shift;
[all...] |
| test-assembler-cond-rd-operand-rn-ror-amount-t32.cc | 74 ShiftType ror;
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 204 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
515 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
[all...] |
