1 // Copyright 2016, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 28 // ----------------------------------------------------------------------------- 29 // This file is auto generated from the 30 // test/aarch32/config/template-assembler-aarch32.cc.in template file using 31 // tools/generate_tests.py. 32 // 33 // PLEASE DO NOT EDIT. 34 // ----------------------------------------------------------------------------- 35 36 37 #include "test-runner.h" 38 39 #include "test-utils.h" 40 #include "test-utils-aarch32.h" 41 42 #include "aarch32/assembler-aarch32.h" 43 #include "aarch32/macro-assembler-aarch32.h" 44 45 #define BUF_SIZE (4096) 46 47 namespace vixl { 48 namespace aarch32 { 49 50 // List of instruction mnemonics. 51 #define FOREACH_INSTRUCTION(M) \ 52 M(cmn) \ 53 M(cmp) \ 54 M(mov) \ 55 M(movs) \ 56 M(mvn) \ 57 M(mvns) \ 58 M(teq) \ 59 M(tst) 60 61 62 // The following definitions are defined again in each generated test, therefore 63 // we need to place them in an anomymous namespace. It expresses that they are 64 // local to this file only, and the compiler is not allowed to share these types 65 // across test files during template instantiation. Specifically, `Operands` has 66 // various layouts across generated tests so it absolutely cannot be shared. 67 68 #ifdef VIXL_INCLUDE_TARGET_T32 69 namespace { 70 71 // Values to be passed to the assembler to produce the instruction under test. 72 struct Operands { 73 Condition cond; 74 Register rd; 75 Register rn; 76 ShiftType shift; 77 uint32_t amount; 78 }; 79 80 // This structure contains all data needed to test one specific 81 // instruction. 82 struct TestData { 83 // The `operands` field represents what to pass to the assembler to 84 // produce the instruction. 85 Operands operands; 86 // True if we need to generate an IT instruction for this test to be valid. 87 bool in_it_block; 88 // The condition to give the IT instruction, this will be set to "al" by 89 // default. 90 Condition it_condition; 91 // Description of the operands, used for error reporting. 92 const char* operands_description; 93 // Unique identifier, used for generating traces. 94 const char* identifier; 95 }; 96 97 struct TestResult { 98 size_t size; 99 const byte* encoding; 100 }; 101 102 // Each element of this array produce one instruction encoding. 103 const TestData kTests[] = { 104 {{al, r7, r7, LSR, 5}, false, al, "al r7 r7 LSR 5", "al_r7_r7_LSR_5"}, 105 {{al, r0, r3, ASR, 30}, false, al, "al r0 r3 ASR 30", "al_r0_r3_ASR_30"}, 106 {{al, r10, r5, ASR, 31}, false, al, "al r10 r5 ASR 31", "al_r10_r5_ASR_31"}, 107 {{al, r12, r9, ASR, 16}, false, al, "al r12 r9 ASR 16", "al_r12_r9_ASR_16"}, 108 {{al, r5, r3, ASR, 31}, false, al, "al r5 r3 ASR 31", "al_r5_r3_ASR_31"}, 109 {{al, r10, r8, ASR, 10}, false, al, "al r10 r8 ASR 10", "al_r10_r8_ASR_10"}, 110 {{al, r6, r7, LSR, 11}, false, al, "al r6 r7 LSR 11", "al_r6_r7_LSR_11"}, 111 {{al, r13, r12, ASR, 31}, 112 false, 113 al, 114 "al r13 r12 ASR 31", 115 "al_r13_r12_ASR_31"}, 116 {{al, r4, r0, ASR, 22}, false, al, "al r4 r0 ASR 22", "al_r4_r0_ASR_22"}, 117 {{al, r3, r10, ASR, 23}, false, al, "al r3 r10 ASR 23", "al_r3_r10_ASR_23"}, 118 {{al, r3, r11, LSR, 6}, false, al, "al r3 r11 LSR 6", "al_r3_r11_LSR_6"}, 119 {{al, r3, r0, LSR, 7}, false, al, "al r3 r0 LSR 7", "al_r3_r0_LSR_7"}, 120 {{al, r12, r14, LSR, 17}, 121 false, 122 al, 123 "al r12 r14 LSR 17", 124 "al_r12_r14_LSR_17"}, 125 {{al, r10, r7, ASR, 15}, false, al, "al r10 r7 ASR 15", "al_r10_r7_ASR_15"}, 126 {{al, r10, r8, LSR, 10}, false, al, "al r10 r8 LSR 10", "al_r10_r8_LSR_10"}, 127 {{al, r11, r1, LSR, 12}, false, al, "al r11 r1 LSR 12", "al_r11_r1_LSR_12"}, 128 {{al, r14, r3, ASR, 31}, false, al, "al r14 r3 ASR 31", "al_r14_r3_ASR_31"}, 129 {{al, r1, r3, LSR, 5}, false, al, "al r1 r3 LSR 5", "al_r1_r3_LSR_5"}, 130 {{al, r10, r14, ASR, 23}, 131 false, 132 al, 133 "al r10 r14 ASR 23", 134 "al_r10_r14_ASR_23"}, 135 {{al, r0, r0, LSR, 18}, false, al, "al r0 r0 LSR 18", "al_r0_r0_LSR_18"}, 136 {{al, r1, r5, LSR, 13}, false, al, "al r1 r5 LSR 13", "al_r1_r5_LSR_13"}, 137 {{al, r4, r2, LSR, 20}, false, al, "al r4 r2 LSR 20", "al_r4_r2_LSR_20"}, 138 {{al, r1, r6, ASR, 8}, false, al, "al r1 r6 ASR 8", "al_r1_r6_ASR_8"}, 139 {{al, r7, r1, LSR, 22}, false, al, "al r7 r1 LSR 22", "al_r7_r1_LSR_22"}, 140 {{al, r11, r9, LSR, 32}, false, al, "al r11 r9 LSR 32", "al_r11_r9_LSR_32"}, 141 {{al, r3, r5, LSR, 32}, false, al, "al r3 r5 LSR 32", "al_r3_r5_LSR_32"}, 142 {{al, r9, r3, LSR, 12}, false, al, "al r9 r3 LSR 12", "al_r9_r3_LSR_12"}, 143 {{al, r13, r10, LSR, 23}, 144 false, 145 al, 146 "al r13 r10 LSR 23", 147 "al_r13_r10_LSR_23"}, 148 {{al, r8, r11, ASR, 3}, false, al, "al r8 r11 ASR 3", "al_r8_r11_ASR_3"}, 149 {{al, r12, r1, ASR, 6}, false, al, "al r12 r1 ASR 6", "al_r12_r1_ASR_6"}, 150 {{al, r6, r9, ASR, 8}, false, al, "al r6 r9 ASR 8", "al_r6_r9_ASR_8"}, 151 {{al, r1, r12, LSR, 4}, false, al, "al r1 r12 LSR 4", "al_r1_r12_LSR_4"}, 152 {{al, r13, r7, ASR, 13}, false, al, "al r13 r7 ASR 13", "al_r13_r7_ASR_13"}, 153 {{al, r13, r10, LSR, 22}, 154 false, 155 al, 156 "al r13 r10 LSR 22", 157 "al_r13_r10_LSR_22"}, 158 {{al, r13, r2, LSR, 5}, false, al, "al r13 r2 LSR 5", "al_r13_r2_LSR_5"}, 159 {{al, r13, r2, LSR, 11}, false, al, "al r13 r2 LSR 11", "al_r13_r2_LSR_11"}, 160 {{al, r10, r0, ASR, 14}, false, al, "al r10 r0 ASR 14", "al_r10_r0_ASR_14"}, 161 {{al, r5, r8, LSR, 24}, false, al, "al r5 r8 LSR 24", "al_r5_r8_LSR_24"}, 162 {{al, r14, r1, ASR, 12}, false, al, "al r14 r1 ASR 12", "al_r14_r1_ASR_12"}, 163 {{al, r7, r3, ASR, 27}, false, al, "al r7 r3 ASR 27", "al_r7_r3_ASR_27"}, 164 {{al, r7, r0, LSR, 26}, false, al, "al r7 r0 LSR 26", "al_r7_r0_LSR_26"}, 165 {{al, r2, r0, ASR, 31}, false, al, "al r2 r0 ASR 31", "al_r2_r0_ASR_31"}, 166 {{al, r8, r0, ASR, 21}, false, al, "al r8 r0 ASR 21", "al_r8_r0_ASR_21"}, 167 {{al, r12, r7, ASR, 21}, false, al, "al r12 r7 ASR 21", "al_r12_r7_ASR_21"}, 168 {{al, r0, r10, LSR, 32}, false, al, "al r0 r10 LSR 32", "al_r0_r10_LSR_32"}, 169 {{al, r5, r5, LSR, 12}, false, al, "al r5 r5 LSR 12", "al_r5_r5_LSR_12"}, 170 {{al, r3, r10, LSR, 30}, false, al, "al r3 r10 LSR 30", "al_r3_r10_LSR_30"}, 171 {{al, r5, r6, ASR, 25}, false, al, "al r5 r6 ASR 25", "al_r5_r6_ASR_25"}, 172 {{al, r9, r4, LSR, 12}, false, al, "al r9 r4 LSR 12", "al_r9_r4_LSR_12"}, 173 {{al, r8, r10, ASR, 32}, false, al, "al r8 r10 ASR 32", "al_r8_r10_ASR_32"}, 174 {{al, r3, r4, ASR, 4}, false, al, "al r3 r4 ASR 4", "al_r3_r4_ASR_4"}, 175 {{al, r13, r2, LSR, 22}, false, al, "al r13 r2 LSR 22", "al_r13_r2_LSR_22"}, 176 {{al, r9, r7, LSR, 25}, false, al, "al r9 r7 LSR 25", "al_r9_r7_LSR_25"}, 177 {{al, r14, r12, ASR, 26}, 178 false, 179 al, 180 "al r14 r12 ASR 26", 181 "al_r14_r12_ASR_26"}, 182 {{al, r10, r0, LSR, 19}, false, al, "al r10 r0 LSR 19", "al_r10_r0_LSR_19"}, 183 {{al, r6, r8, LSR, 10}, false, al, "al r6 r8 LSR 10", "al_r6_r8_LSR_10"}, 184 {{al, r14, r12, ASR, 15}, 185 false, 186 al, 187 "al r14 r12 ASR 15", 188 "al_r14_r12_ASR_15"}, 189 {{al, r14, r14, LSR, 10}, 190 false, 191 al, 192 "al r14 r14 LSR 10", 193 "al_r14_r14_LSR_10"}, 194 {{al, r3, r2, ASR, 3}, false, al, "al r3 r2 ASR 3", "al_r3_r2_ASR_3"}, 195 {{al, r13, r6, ASR, 26}, false, al, "al r13 r6 ASR 26", "al_r13_r6_ASR_26"}, 196 {{al, r14, r9, LSR, 19}, false, al, "al r14 r9 LSR 19", "al_r14_r9_LSR_19"}, 197 {{al, r14, r6, ASR, 13}, false, al, "al r14 r6 ASR 13", "al_r14_r6_ASR_13"}, 198 {{al, r4, r8, LSR, 6}, false, al, "al r4 r8 LSR 6", "al_r4_r8_LSR_6"}, 199 {{al, r3, r11, LSR, 17}, false, al, "al r3 r11 LSR 17", "al_r3_r11_LSR_17"}, 200 {{al, r13, r8, ASR, 17}, false, al, "al r13 r8 ASR 17", "al_r13_r8_ASR_17"}, 201 {{al, r1, r13, ASR, 14}, false, al, "al r1 r13 ASR 14", "al_r1_r13_ASR_14"}, 202 {{al, r13, r7, ASR, 14}, false, al, "al r13 r7 ASR 14", "al_r13_r7_ASR_14"}, 203 {{al, r12, r11, ASR, 4}, false, al, "al r12 r11 ASR 4", "al_r12_r11_ASR_4"}, 204 {{al, r9, r11, LSR, 23}, false, al, "al r9 r11 LSR 23", "al_r9_r11_LSR_23"}, 205 {{al, r7, r0, ASR, 16}, false, al, "al r7 r0 ASR 16", "al_r7_r0_ASR_16"}, 206 {{al, r14, r13, ASR, 32}, 207 false, 208 al, 209 "al r14 r13 ASR 32", 210 "al_r14_r13_ASR_32"}, 211 {{al, r7, r8, ASR, 9}, false, al, "al r7 r8 ASR 9", "al_r7_r8_ASR_9"}, 212 {{al, r4, r8, ASR, 5}, false, al, "al r4 r8 ASR 5", "al_r4_r8_ASR_5"}, 213 {{al, r3, r9, LSR, 30}, false, al, "al r3 r9 LSR 30", "al_r3_r9_LSR_30"}, 214 {{al, r3, r12, ASR, 12}, false, al, "al r3 r12 ASR 12", "al_r3_r12_ASR_12"}, 215 {{al, r8, r6, ASR, 15}, false, al, "al r8 r6 ASR 15", "al_r8_r6_ASR_15"}, 216 {{al, r8, r13, ASR, 25}, false, al, "al r8 r13 ASR 25", "al_r8_r13_ASR_25"}, 217 {{al, r3, r10, LSR, 28}, false, al, "al r3 r10 LSR 28", "al_r3_r10_LSR_28"}, 218 {{al, r1, r14, LSR, 30}, false, al, "al r1 r14 LSR 30", "al_r1_r14_LSR_30"}, 219 {{al, r4, r9, ASR, 22}, false, al, "al r4 r9 ASR 22", "al_r4_r9_ASR_22"}, 220 {{al, r2, r13, LSR, 15}, false, al, "al r2 r13 LSR 15", "al_r2_r13_LSR_15"}, 221 {{al, r10, r0, ASR, 4}, false, al, "al r10 r0 ASR 4", "al_r10_r0_ASR_4"}, 222 {{al, r11, r12, ASR, 4}, false, al, "al r11 r12 ASR 4", "al_r11_r12_ASR_4"}, 223 {{al, r6, r9, LSR, 4}, false, al, "al r6 r9 LSR 4", "al_r6_r9_LSR_4"}, 224 {{al, r0, r3, ASR, 18}, false, al, "al r0 r3 ASR 18", "al_r0_r3_ASR_18"}, 225 {{al, r9, r4, ASR, 24}, false, al, "al r9 r4 ASR 24", "al_r9_r4_ASR_24"}, 226 {{al, r7, r3, LSR, 15}, false, al, "al r7 r3 LSR 15", "al_r7_r3_LSR_15"}, 227 {{al, r6, r4, LSR, 20}, false, al, "al r6 r4 LSR 20", "al_r6_r4_LSR_20"}, 228 {{al, r3, r9, ASR, 19}, false, al, "al r3 r9 ASR 19", "al_r3_r9_ASR_19"}, 229 {{al, r5, r14, LSR, 12}, false, al, "al r5 r14 LSR 12", "al_r5_r14_LSR_12"}, 230 {{al, r7, r12, LSR, 6}, false, al, "al r7 r12 LSR 6", "al_r7_r12_LSR_6"}, 231 {{al, r10, r5, LSR, 14}, false, al, "al r10 r5 LSR 14", "al_r10_r5_LSR_14"}, 232 {{al, r13, r9, LSR, 26}, false, al, "al r13 r9 LSR 26", "al_r13_r9_LSR_26"}, 233 {{al, r0, r6, LSR, 29}, false, al, "al r0 r6 LSR 29", "al_r0_r6_LSR_29"}, 234 {{al, r9, r11, ASR, 7}, false, al, "al r9 r11 ASR 7", "al_r9_r11_ASR_7"}, 235 {{al, r14, r14, LSR, 1}, false, al, "al r14 r14 LSR 1", "al_r14_r14_LSR_1"}, 236 {{al, r6, r3, ASR, 7}, false, al, "al r6 r3 ASR 7", "al_r6_r3_ASR_7"}, 237 {{al, r4, r8, ASR, 30}, false, al, "al r4 r8 ASR 30", "al_r4_r8_ASR_30"}, 238 {{al, r2, r9, LSR, 29}, false, al, "al r2 r9 LSR 29", "al_r2_r9_LSR_29"}, 239 {{al, r11, r3, LSR, 23}, false, al, "al r11 r3 LSR 23", "al_r11_r3_LSR_23"}, 240 {{al, r12, r3, ASR, 20}, false, al, "al r12 r3 ASR 20", "al_r12_r3_ASR_20"}, 241 {{al, r10, r5, LSR, 30}, false, al, "al r10 r5 LSR 30", "al_r10_r5_LSR_30"}, 242 {{al, r9, r10, ASR, 25}, false, al, "al r9 r10 ASR 25", "al_r9_r10_ASR_25"}, 243 {{al, r13, r9, LSR, 10}, false, al, "al r13 r9 LSR 10", "al_r13_r9_LSR_10"}, 244 {{al, r6, r4, ASR, 28}, false, al, "al r6 r4 ASR 28", "al_r6_r4_ASR_28"}, 245 {{al, r8, r6, ASR, 10}, false, al, "al r8 r6 ASR 10", "al_r8_r6_ASR_10"}, 246 {{al, r2, r11, LSR, 23}, false, al, "al r2 r11 LSR 23", "al_r2_r11_LSR_23"}, 247 {{al, r14, r7, ASR, 22}, false, al, "al r14 r7 ASR 22", "al_r14_r7_ASR_22"}, 248 {{al, r5, r3, ASR, 23}, false, al, "al r5 r3 ASR 23", "al_r5_r3_ASR_23"}, 249 {{al, r9, r4, LSR, 13}, false, al, "al r9 r4 LSR 13", "al_r9_r4_LSR_13"}, 250 {{al, r3, r10, ASR, 9}, false, al, "al r3 r10 ASR 9", "al_r3_r10_ASR_9"}, 251 {{al, r6, r6, ASR, 1}, false, al, "al r6 r6 ASR 1", "al_r6_r6_ASR_1"}, 252 {{al, r3, r11, ASR, 13}, false, al, "al r3 r11 ASR 13", "al_r3_r11_ASR_13"}, 253 {{al, r6, r9, LSR, 10}, false, al, "al r6 r9 LSR 10", "al_r6_r9_LSR_10"}, 254 {{al, r1, r5, ASR, 6}, false, al, "al r1 r5 ASR 6", "al_r1_r5_ASR_6"}, 255 {{al, r13, r0, ASR, 12}, false, al, "al r13 r0 ASR 12", "al_r13_r0_ASR_12"}, 256 {{al, r10, r10, ASR, 20}, 257 false, 258 al, 259 "al r10 r10 ASR 20", 260 "al_r10_r10_ASR_20"}, 261 {{al, r2, r3, LSR, 12}, false, al, "al r2 r3 LSR 12", "al_r2_r3_LSR_12"}, 262 {{al, r3, r1, ASR, 20}, false, al, "al r3 r1 ASR 20", "al_r3_r1_ASR_20"}, 263 {{al, r5, r6, LSR, 8}, false, al, "al r5 r6 LSR 8", "al_r5_r6_LSR_8"}, 264 {{al, r2, r13, ASR, 28}, false, al, "al r2 r13 ASR 28", "al_r2_r13_ASR_28"}, 265 {{al, r6, r14, LSR, 26}, false, al, "al r6 r14 LSR 26", "al_r6_r14_LSR_26"}, 266 {{al, r2, r4, LSR, 7}, false, al, "al r2 r4 LSR 7", "al_r2_r4_LSR_7"}, 267 {{al, r2, r13, LSR, 8}, false, al, "al r2 r13 LSR 8", "al_r2_r13_LSR_8"}, 268 {{al, r5, r6, ASR, 9}, false, al, "al r5 r6 ASR 9", "al_r5_r6_ASR_9"}, 269 {{al, r1, r12, ASR, 20}, false, al, "al r1 r12 ASR 20", "al_r1_r12_ASR_20"}, 270 {{al, r1, r8, LSR, 15}, false, al, "al r1 r8 LSR 15", "al_r1_r8_LSR_15"}, 271 {{al, r14, r5, ASR, 26}, false, al, "al r14 r5 ASR 26", "al_r14_r5_ASR_26"}, 272 {{al, r14, r3, LSR, 23}, false, al, "al r14 r3 LSR 23", "al_r14_r3_LSR_23"}, 273 {{al, r1, r0, ASR, 15}, false, al, "al r1 r0 ASR 15", "al_r1_r0_ASR_15"}, 274 {{al, r4, r2, LSR, 7}, false, al, "al r4 r2 LSR 7", "al_r4_r2_LSR_7"}, 275 {{al, r11, r13, LSR, 27}, 276 false, 277 al, 278 "al r11 r13 LSR 27", 279 "al_r11_r13_LSR_27"}, 280 {{al, r8, r1, LSR, 15}, false, al, "al r8 r1 LSR 15", "al_r8_r1_LSR_15"}, 281 {{al, r5, r10, ASR, 8}, false, al, "al r5 r10 ASR 8", "al_r5_r10_ASR_8"}, 282 {{al, r8, r9, ASR, 23}, false, al, "al r8 r9 ASR 23", "al_r8_r9_ASR_23"}, 283 {{al, r9, r6, LSR, 12}, false, al, "al r9 r6 LSR 12", "al_r9_r6_LSR_12"}, 284 {{al, r9, r1, LSR, 28}, false, al, "al r9 r1 LSR 28", "al_r9_r1_LSR_28"}, 285 {{al, r3, r0, LSR, 19}, false, al, "al r3 r0 LSR 19", "al_r3_r0_LSR_19"}, 286 {{al, r13, r2, LSR, 3}, false, al, "al r13 r2 LSR 3", "al_r13_r2_LSR_3"}, 287 {{al, r11, r11, LSR, 11}, 288 false, 289 al, 290 "al r11 r11 LSR 11", 291 "al_r11_r11_LSR_11"}, 292 {{al, r2, r13, LSR, 32}, false, al, "al r2 r13 LSR 32", "al_r2_r13_LSR_32"}, 293 {{al, r9, r5, ASR, 11}, false, al, "al r9 r5 ASR 11", "al_r9_r5_ASR_11"}, 294 {{al, r14, r11, ASR, 19}, 295 false, 296 al, 297 "al r14 r11 ASR 19", 298 "al_r14_r11_ASR_19"}, 299 {{al, r1, r3, LSR, 22}, false, al, "al r1 r3 LSR 22", "al_r1_r3_LSR_22"}, 300 {{al, r9, r10, ASR, 7}, false, al, "al r9 r10 ASR 7", "al_r9_r10_ASR_7"}, 301 {{al, r9, r0, LSR, 1}, false, al, "al r9 r0 LSR 1", "al_r9_r0_LSR_1"}, 302 {{al, r1, r8, LSR, 3}, false, al, "al r1 r8 LSR 3", "al_r1_r8_LSR_3"}, 303 {{al, r12, r4, ASR, 16}, false, al, "al r12 r4 ASR 16", "al_r12_r4_ASR_16"}, 304 {{al, r14, r10, LSR, 27}, 305 false, 306 al, 307 "al r14 r10 LSR 27", 308 "al_r14_r10_LSR_27"}, 309 {{al, r13, r5, ASR, 16}, false, al, "al r13 r5 ASR 16", "al_r13_r5_ASR_16"}, 310 {{al, r5, r11, LSR, 13}, false, al, "al r5 r11 LSR 13", "al_r5_r11_LSR_13"}, 311 {{al, r8, r8, ASR, 13}, false, al, "al r8 r8 ASR 13", "al_r8_r8_ASR_13"}, 312 {{al, r11, r14, LSR, 19}, 313 false, 314 al, 315 "al r11 r14 LSR 19", 316 "al_r11_r14_LSR_19"}, 317 {{al, r14, r4, LSR, 32}, false, al, "al r14 r4 LSR 32", "al_r14_r4_LSR_32"}, 318 {{al, r1, r7, LSR, 9}, false, al, "al r1 r7 LSR 9", "al_r1_r7_LSR_9"}, 319 {{al, r4, r13, LSR, 10}, false, al, "al r4 r13 LSR 10", "al_r4_r13_LSR_10"}, 320 {{al, r4, r13, LSR, 7}, false, al, "al r4 r13 LSR 7", "al_r4_r13_LSR_7"}, 321 {{al, r0, r8, LSR, 10}, false, al, "al r0 r8 LSR 10", "al_r0_r8_LSR_10"}, 322 {{al, r4, r14, LSR, 9}, false, al, "al r4 r14 LSR 9", "al_r4_r14_LSR_9"}, 323 {{al, r3, r9, ASR, 14}, false, al, "al r3 r9 ASR 14", "al_r3_r9_ASR_14"}, 324 {{al, r8, r2, LSR, 31}, false, al, "al r8 r2 LSR 31", "al_r8_r2_LSR_31"}, 325 {{al, r1, r14, ASR, 9}, false, al, "al r1 r14 ASR 9", "al_r1_r14_ASR_9"}, 326 {{al, r10, r3, ASR, 31}, false, al, "al r10 r3 ASR 31", "al_r10_r3_ASR_31"}, 327 {{al, r5, r6, LSR, 9}, false, al, "al r5 r6 LSR 9", "al_r5_r6_LSR_9"}, 328 {{al, r0, r0, LSR, 15}, false, al, "al r0 r0 LSR 15", "al_r0_r0_LSR_15"}, 329 {{al, r14, r7, LSR, 16}, false, al, "al r14 r7 LSR 16", "al_r14_r7_LSR_16"}, 330 {{al, r12, r0, ASR, 23}, false, al, "al r12 r0 ASR 23", "al_r12_r0_ASR_23"}, 331 {{al, r10, r3, ASR, 30}, false, al, "al r10 r3 ASR 30", "al_r10_r3_ASR_30"}, 332 {{al, r13, r13, LSR, 21}, 333 false, 334 al, 335 "al r13 r13 LSR 21", 336 "al_r13_r13_LSR_21"}, 337 {{al, r7, r1, LSR, 27}, false, al, "al r7 r1 LSR 27", "al_r7_r1_LSR_27"}, 338 {{al, r10, r9, ASR, 27}, false, al, "al r10 r9 ASR 27", "al_r10_r9_ASR_27"}, 339 {{al, r11, r11, LSR, 19}, 340 false, 341 al, 342 "al r11 r11 LSR 19", 343 "al_r11_r11_LSR_19"}, 344 {{al, r3, r1, LSR, 25}, false, al, "al r3 r1 LSR 25", "al_r3_r1_LSR_25"}, 345 {{al, r0, r5, ASR, 5}, false, al, "al r0 r5 ASR 5", "al_r0_r5_ASR_5"}, 346 {{al, r4, r11, ASR, 32}, false, al, "al r4 r11 ASR 32", "al_r4_r11_ASR_32"}, 347 {{al, r2, r7, ASR, 8}, false, al, "al r2 r7 ASR 8", "al_r2_r7_ASR_8"}, 348 {{al, r4, r13, LSR, 18}, false, al, "al r4 r13 LSR 18", "al_r4_r13_LSR_18"}, 349 {{al, r8, r10, LSR, 31}, false, al, "al r8 r10 LSR 31", "al_r8_r10_LSR_31"}, 350 {{al, r10, r3, LSR, 21}, false, al, "al r10 r3 LSR 21", "al_r10_r3_LSR_21"}, 351 {{al, r3, r5, LSR, 23}, false, al, "al r3 r5 LSR 23", "al_r3_r5_LSR_23"}, 352 {{al, r8, r9, ASR, 15}, false, al, "al r8 r9 ASR 15", "al_r8_r9_ASR_15"}, 353 {{al, r11, r11, LSR, 9}, false, al, "al r11 r11 LSR 9", "al_r11_r11_LSR_9"}, 354 {{al, r13, r13, ASR, 25}, 355 false, 356 al, 357 "al r13 r13 ASR 25", 358 "al_r13_r13_ASR_25"}, 359 {{al, r6, r13, ASR, 24}, false, al, "al r6 r13 ASR 24", "al_r6_r13_ASR_24"}, 360 {{al, r8, r2, LSR, 4}, false, al, "al r8 r2 LSR 4", "al_r8_r2_LSR_4"}, 361 {{al, r0, r10, ASR, 4}, false, al, "al r0 r10 ASR 4", "al_r0_r10_ASR_4"}, 362 {{al, r2, r1, LSR, 32}, false, al, "al r2 r1 LSR 32", "al_r2_r1_LSR_32"}, 363 {{al, r11, r10, LSR, 25}, 364 false, 365 al, 366 "al r11 r10 LSR 25", 367 "al_r11_r10_LSR_25"}, 368 {{al, r14, r13, LSR, 17}, 369 false, 370 al, 371 "al r14 r13 LSR 17", 372 "al_r14_r13_LSR_17"}, 373 {{al, r8, r4, ASR, 25}, false, al, "al r8 r4 ASR 25", "al_r8_r4_ASR_25"}, 374 {{al, r9, r0, ASR, 11}, false, al, "al r9 r0 ASR 11", "al_r9_r0_ASR_11"}, 375 {{al, r3, r2, ASR, 16}, false, al, "al r3 r2 ASR 16", "al_r3_r2_ASR_16"}, 376 {{al, r6, r3, ASR, 28}, false, al, "al r6 r3 ASR 28", "al_r6_r3_ASR_28"}, 377 {{al, r11, r8, LSR, 20}, false, al, "al r11 r8 LSR 20", "al_r11_r8_LSR_20"}, 378 {{al, r8, r13, ASR, 2}, false, al, "al r8 r13 ASR 2", "al_r8_r13_ASR_2"}, 379 {{al, r13, r6, LSR, 19}, false, al, "al r13 r6 LSR 19", "al_r13_r6_LSR_19"}, 380 {{al, r13, r10, ASR, 20}, 381 false, 382 al, 383 "al r13 r10 ASR 20", 384 "al_r13_r10_ASR_20"}, 385 {{al, r8, r7, LSR, 26}, false, al, "al r8 r7 LSR 26", "al_r8_r7_LSR_26"}, 386 {{al, r12, r4, LSR, 30}, false, al, "al r12 r4 LSR 30", "al_r12_r4_LSR_30"}, 387 {{al, r13, r6, LSR, 27}, false, al, "al r13 r6 LSR 27", "al_r13_r6_LSR_27"}, 388 {{al, r3, r3, LSR, 8}, false, al, "al r3 r3 LSR 8", "al_r3_r3_LSR_8"}, 389 {{al, r14, r1, ASR, 22}, false, al, "al r14 r1 ASR 22", "al_r14_r1_ASR_22"}, 390 {{al, r10, r10, LSR, 7}, false, al, "al r10 r10 LSR 7", "al_r10_r10_LSR_7"}, 391 {{al, r12, r0, ASR, 10}, false, al, "al r12 r0 ASR 10", "al_r12_r0_ASR_10"}, 392 {{al, r8, r4, ASR, 2}, false, al, "al r8 r4 ASR 2", "al_r8_r4_ASR_2"}, 393 {{al, r14, r14, LSR, 18}, 394 false, 395 al, 396 "al r14 r14 LSR 18", 397 "al_r14_r14_LSR_18"}, 398 {{al, r12, r5, LSR, 27}, false, al, "al r12 r5 LSR 27", "al_r12_r5_LSR_27"}, 399 {{al, r10, r8, LSR, 2}, false, al, "al r10 r8 LSR 2", "al_r10_r8_LSR_2"}, 400 {{al, r5, r4, LSR, 13}, false, al, "al r5 r4 LSR 13", "al_r5_r4_LSR_13"}, 401 {{al, r0, r12, LSR, 2}, false, al, "al r0 r12 LSR 2", "al_r0_r12_LSR_2"}, 402 {{al, r8, r6, LSR, 13}, false, al, "al r8 r6 LSR 13", "al_r8_r6_LSR_13"}, 403 {{al, r14, r4, LSR, 19}, false, al, "al r14 r4 LSR 19", "al_r14_r4_LSR_19"}, 404 {{al, r8, r1, LSR, 30}, false, al, "al r8 r1 LSR 30", "al_r8_r1_LSR_30"}, 405 {{al, r1, r1, LSR, 28}, false, al, "al r1 r1 LSR 28", "al_r1_r1_LSR_28"}, 406 {{al, r14, r1, ASR, 16}, false, al, "al r14 r1 ASR 16", "al_r14_r1_ASR_16"}, 407 {{al, r0, r11, LSR, 25}, false, al, "al r0 r11 LSR 25", "al_r0_r11_LSR_25"}, 408 {{al, r9, r11, LSR, 30}, false, al, "al r9 r11 LSR 30", "al_r9_r11_LSR_30"}, 409 {{al, r2, r10, ASR, 11}, false, al, "al r2 r10 ASR 11", "al_r2_r10_ASR_11"}, 410 {{al, r9, r11, LSR, 9}, false, al, "al r9 r11 LSR 9", "al_r9_r11_LSR_9"}, 411 {{al, r9, r12, LSR, 20}, false, al, "al r9 r12 LSR 20", "al_r9_r12_LSR_20"}, 412 {{al, r3, r1, ASR, 21}, false, al, "al r3 r1 ASR 21", "al_r3_r1_ASR_21"}, 413 {{al, r14, r14, ASR, 9}, false, al, "al r14 r14 ASR 9", "al_r14_r14_ASR_9"}, 414 {{al, r14, r13, LSR, 27}, 415 false, 416 al, 417 "al r14 r13 LSR 27", 418 "al_r14_r13_LSR_27"}, 419 {{al, r3, r3, LSR, 11}, false, al, "al r3 r3 LSR 11", "al_r3_r3_LSR_11"}, 420 {{al, r7, r3, LSR, 28}, false, al, "al r7 r3 LSR 28", "al_r7_r3_LSR_28"}, 421 {{al, r6, r14, ASR, 29}, false, al, "al r6 r14 ASR 29", "al_r6_r14_ASR_29"}, 422 {{al, r3, r12, ASR, 15}, false, al, "al r3 r12 ASR 15", "al_r3_r12_ASR_15"}, 423 {{al, r11, r12, LSR, 32}, 424 false, 425 al, 426 "al r11 r12 LSR 32", 427 "al_r11_r12_LSR_32"}, 428 {{al, r3, r8, LSR, 5}, false, al, "al r3 r8 LSR 5", "al_r3_r8_LSR_5"}, 429 {{al, r6, r12, LSR, 18}, false, al, "al r6 r12 LSR 18", "al_r6_r12_LSR_18"}, 430 {{al, r10, r6, LSR, 19}, false, al, "al r10 r6 LSR 19", "al_r10_r6_LSR_19"}, 431 {{al, r5, r7, LSR, 25}, false, al, "al r5 r7 LSR 25", "al_r5_r7_LSR_25"}, 432 {{al, r3, r13, LSR, 2}, false, al, "al r3 r13 LSR 2", "al_r3_r13_LSR_2"}, 433 {{al, r8, r3, ASR, 26}, false, al, "al r8 r3 ASR 26", "al_r8_r3_ASR_26"}, 434 {{al, r13, r3, LSR, 23}, false, al, "al r13 r3 LSR 23", "al_r13_r3_LSR_23"}, 435 {{al, r5, r2, LSR, 23}, false, al, "al r5 r2 LSR 23", "al_r5_r2_LSR_23"}, 436 {{al, r3, r12, ASR, 22}, false, al, "al r3 r12 ASR 22", "al_r3_r12_ASR_22"}, 437 {{al, r11, r10, ASR, 25}, 438 false, 439 al, 440 "al r11 r10 ASR 25", 441 "al_r11_r10_ASR_25"}, 442 {{al, r2, r11, LSR, 31}, false, al, "al r2 r11 LSR 31", "al_r2_r11_LSR_31"}, 443 {{al, r7, r8, LSR, 11}, false, al, "al r7 r8 LSR 11", "al_r7_r8_LSR_11"}, 444 {{al, r9, r14, ASR, 32}, false, al, "al r9 r14 ASR 32", "al_r9_r14_ASR_32"}, 445 {{al, r11, r14, ASR, 21}, 446 false, 447 al, 448 "al r11 r14 ASR 21", 449 "al_r11_r14_ASR_21"}, 450 {{al, r11, r13, ASR, 2}, false, al, "al r11 r13 ASR 2", "al_r11_r13_ASR_2"}, 451 {{al, r12, r3, ASR, 16}, false, al, "al r12 r3 ASR 16", "al_r12_r3_ASR_16"}, 452 {{al, r9, r11, ASR, 24}, false, al, "al r9 r11 ASR 24", "al_r9_r11_ASR_24"}, 453 {{al, r5, r7, LSR, 20}, false, al, "al r5 r7 LSR 20", "al_r5_r7_LSR_20"}, 454 {{al, r9, r4, ASR, 8}, false, al, "al r9 r4 ASR 8", "al_r9_r4_ASR_8"}, 455 {{al, r12, r9, ASR, 10}, false, al, "al r12 r9 ASR 10", "al_r12_r9_ASR_10"}, 456 {{al, r7, r10, LSR, 9}, false, al, "al r7 r10 LSR 9", "al_r7_r10_LSR_9"}, 457 {{al, r7, r4, LSR, 16}, false, al, "al r7 r4 LSR 16", "al_r7_r4_LSR_16"}, 458 {{al, r11, r5, LSR, 22}, false, al, "al r11 r5 LSR 22", "al_r11_r5_LSR_22"}, 459 {{al, r4, r8, LSR, 12}, false, al, "al r4 r8 LSR 12", "al_r4_r8_LSR_12"}, 460 {{al, r14, r7, ASR, 4}, false, al, "al r14 r7 ASR 4", "al_r14_r7_ASR_4"}, 461 {{al, r12, r13, LSR, 25}, 462 false, 463 al, 464 "al r12 r13 LSR 25", 465 "al_r12_r13_LSR_25"}, 466 {{al, r12, r5, LSR, 8}, false, al, "al r12 r5 LSR 8", "al_r12_r5_LSR_8"}, 467 {{al, r8, r11, LSR, 13}, false, al, "al r8 r11 LSR 13", "al_r8_r11_LSR_13"}, 468 {{al, r8, r11, ASR, 8}, false, al, "al r8 r11 ASR 8", "al_r8_r11_ASR_8"}, 469 {{al, r13, r13, LSR, 10}, 470 false, 471 al, 472 "al r13 r13 LSR 10", 473 "al_r13_r13_LSR_10"}, 474 {{al, r2, r4, ASR, 9}, false, al, "al r2 r4 ASR 9", "al_r2_r4_ASR_9"}, 475 {{al, r0, r5, ASR, 4}, false, al, "al r0 r5 ASR 4", "al_r0_r5_ASR_4"}, 476 {{al, r6, r0, LSR, 7}, false, al, "al r6 r0 LSR 7", "al_r6_r0_LSR_7"}, 477 {{al, r0, r2, ASR, 27}, false, al, "al r0 r2 ASR 27", "al_r0_r2_ASR_27"}, 478 {{al, r5, r9, ASR, 6}, false, al, "al r5 r9 ASR 6", "al_r5_r9_ASR_6"}, 479 {{al, r10, r10, ASR, 17}, 480 false, 481 al, 482 "al r10 r10 ASR 17", 483 "al_r10_r10_ASR_17"}, 484 {{al, r7, r9, ASR, 23}, false, al, "al r7 r9 ASR 23", "al_r7_r9_ASR_23"}, 485 {{al, r11, r11, LSR, 13}, 486 false, 487 al, 488 "al r11 r11 LSR 13", 489 "al_r11_r11_LSR_13"}, 490 {{al, r11, r4, ASR, 29}, false, al, "al r11 r4 ASR 29", "al_r11_r4_ASR_29"}, 491 {{al, r3, r3, LSR, 30}, false, al, "al r3 r3 LSR 30", "al_r3_r3_LSR_30"}, 492 {{al, r12, r11, ASR, 29}, 493 false, 494 al, 495 "al r12 r11 ASR 29", 496 "al_r12_r11_ASR_29"}, 497 {{al, r0, r9, ASR, 22}, false, al, "al r0 r9 ASR 22", "al_r0_r9_ASR_22"}, 498 {{al, r11, r5, ASR, 12}, false, al, "al r11 r5 ASR 12", "al_r11_r5_ASR_12"}, 499 {{al, r8, r9, ASR, 12}, false, al, "al r8 r9 ASR 12", "al_r8_r9_ASR_12"}, 500 {{al, r11, r0, LSR, 3}, false, al, "al r11 r0 LSR 3", "al_r11_r0_LSR_3"}, 501 {{al, r6, r13, LSR, 18}, false, al, "al r6 r13 LSR 18", "al_r6_r13_LSR_18"}, 502 {{al, r8, r10, ASR, 1}, false, al, "al r8 r10 ASR 1", "al_r8_r10_ASR_1"}, 503 {{al, r3, r2, LSR, 25}, false, al, "al r3 r2 LSR 25", "al_r3_r2_LSR_25"}, 504 {{al, r7, r6, ASR, 30}, false, al, "al r7 r6 ASR 30", "al_r7_r6_ASR_30"}, 505 {{al, r6, r2, LSR, 16}, false, al, "al r6 r2 LSR 16", "al_r6_r2_LSR_16"}, 506 {{al, r13, r8, ASR, 1}, false, al, "al r13 r8 ASR 1", "al_r13_r8_ASR_1"}, 507 {{al, r9, r12, LSR, 2}, false, al, "al r9 r12 LSR 2", "al_r9_r12_LSR_2"}, 508 {{al, r1, r7, LSR, 31}, false, al, "al r1 r7 LSR 31", "al_r1_r7_LSR_31"}, 509 {{al, r12, r13, ASR, 28}, 510 false, 511 al, 512 "al r12 r13 ASR 28", 513 "al_r12_r13_ASR_28"}, 514 {{al, r2, r11, LSR, 5}, false, al, "al r2 r11 LSR 5", "al_r2_r11_LSR_5"}, 515 {{al, r10, r2, LSR, 19}, false, al, "al r10 r2 LSR 19", "al_r10_r2_LSR_19"}, 516 {{al, r11, r2, LSR, 8}, false, al, "al r11 r2 LSR 8", "al_r11_r2_LSR_8"}, 517 {{al, r8, r8, LSR, 3}, false, al, "al r8 r8 LSR 3", "al_r8_r8_LSR_3"}, 518 {{al, r3, r3, LSR, 1}, false, al, "al r3 r3 LSR 1", "al_r3_r3_LSR_1"}, 519 {{al, r5, r4, LSR, 7}, false, al, "al r5 r4 LSR 7", "al_r5_r4_LSR_7"}, 520 {{al, r3, r2, ASR, 22}, false, al, "al r3 r2 ASR 22", "al_r3_r2_ASR_22"}, 521 {{al, r13, r14, LSR, 29}, 522 false, 523 al, 524 "al r13 r14 LSR 29", 525 "al_r13_r14_LSR_29"}, 526 {{al, r3, r8, LSR, 13}, false, al, "al r3 r8 LSR 13", "al_r3_r8_LSR_13"}, 527 {{al, r10, r11, LSR, 27}, 528 false, 529 al, 530 "al r10 r11 LSR 27", 531 "al_r10_r11_LSR_27"}, 532 {{al, r14, r3, LSR, 18}, false, al, "al r14 r3 LSR 18", "al_r14_r3_LSR_18"}, 533 {{al, r10, r0, ASR, 9}, false, al, "al r10 r0 ASR 9", "al_r10_r0_ASR_9"}, 534 {{al, r3, r1, ASR, 23}, false, al, "al r3 r1 ASR 23", "al_r3_r1_ASR_23"}, 535 {{al, r7, r10, LSR, 31}, false, al, "al r7 r10 LSR 31", "al_r7_r10_LSR_31"}, 536 {{al, r7, r7, LSR, 16}, false, al, "al r7 r7 LSR 16", "al_r7_r7_LSR_16"}, 537 {{al, r0, r10, ASR, 20}, false, al, "al r0 r10 ASR 20", "al_r0_r10_ASR_20"}, 538 {{al, r4, r14, LSR, 3}, false, al, "al r4 r14 LSR 3", "al_r4_r14_LSR_3"}, 539 {{al, r10, r12, LSR, 21}, 540 false, 541 al, 542 "al r10 r12 LSR 21", 543 "al_r10_r12_LSR_21"}, 544 {{al, r1, r10, ASR, 20}, false, al, "al r1 r10 ASR 20", "al_r1_r10_ASR_20"}, 545 {{al, r12, r5, ASR, 32}, false, al, "al r12 r5 ASR 32", "al_r12_r5_ASR_32"}, 546 {{al, r6, r3, LSR, 26}, false, al, "al r6 r3 LSR 26", "al_r6_r3_LSR_26"}, 547 {{al, r4, r12, ASR, 11}, false, al, "al r4 r12 ASR 11", "al_r4_r12_ASR_11"}, 548 {{al, r1, r7, LSR, 1}, false, al, "al r1 r7 LSR 1", "al_r1_r7_LSR_1"}, 549 {{al, r0, r3, LSR, 27}, false, al, "al r0 r3 LSR 27", "al_r0_r3_LSR_27"}, 550 {{al, r7, r9, LSR, 32}, false, al, "al r7 r9 LSR 32", "al_r7_r9_LSR_32"}, 551 {{al, r10, r1, LSR, 3}, false, al, "al r10 r1 LSR 3", "al_r10_r1_LSR_3"}, 552 {{al, r1, r11, LSR, 23}, false, al, "al r1 r11 LSR 23", "al_r1_r11_LSR_23"}, 553 {{al, r14, r6, ASR, 5}, false, al, "al r14 r6 ASR 5", "al_r14_r6_ASR_5"}, 554 {{al, r1, r12, LSR, 9}, false, al, "al r1 r12 LSR 9", "al_r1_r12_LSR_9"}, 555 {{al, r0, r1, LSR, 15}, false, al, "al r0 r1 LSR 15", "al_r0_r1_LSR_15"}, 556 {{al, r11, r2, ASR, 11}, false, al, "al r11 r2 ASR 11", "al_r11_r2_ASR_11"}, 557 {{al, r14, r14, ASR, 15}, 558 false, 559 al, 560 "al r14 r14 ASR 15", 561 "al_r14_r14_ASR_15"}, 562 {{al, r12, r4, LSR, 32}, false, al, "al r12 r4 LSR 32", "al_r12_r4_LSR_32"}, 563 {{al, r6, r6, ASR, 23}, false, al, "al r6 r6 ASR 23", "al_r6_r6_ASR_23"}, 564 {{al, r4, r10, ASR, 25}, false, al, "al r4 r10 ASR 25", "al_r4_r10_ASR_25"}, 565 {{al, r11, r10, LSR, 10}, 566 false, 567 al, 568 "al r11 r10 LSR 10", 569 "al_r11_r10_LSR_10"}, 570 {{al, r14, r4, LSR, 1}, false, al, "al r14 r4 LSR 1", "al_r14_r4_LSR_1"}, 571 {{al, r8, r11, LSR, 15}, false, al, "al r8 r11 LSR 15", "al_r8_r11_LSR_15"}, 572 {{al, r13, r8, ASR, 10}, false, al, "al r13 r8 ASR 10", "al_r13_r8_ASR_10"}, 573 {{al, r3, r0, LSR, 31}, false, al, "al r3 r0 LSR 31", "al_r3_r0_LSR_31"}, 574 {{al, r0, r14, LSR, 19}, false, al, "al r0 r14 LSR 19", "al_r0_r14_LSR_19"}, 575 {{al, r2, r14, ASR, 8}, false, al, "al r2 r14 ASR 8", "al_r2_r14_ASR_8"}, 576 {{al, r6, r5, LSR, 2}, false, al, "al r6 r5 LSR 2", "al_r6_r5_LSR_2"}, 577 {{al, r12, r10, ASR, 22}, 578 false, 579 al, 580 "al r12 r10 ASR 22", 581 "al_r12_r10_ASR_22"}, 582 {{al, r7, r0, LSR, 18}, false, al, "al r7 r0 LSR 18", "al_r7_r0_LSR_18"}, 583 {{al, r9, r13, ASR, 10}, false, al, "al r9 r13 ASR 10", "al_r9_r13_ASR_10"}, 584 {{al, r10, r13, ASR, 5}, false, al, "al r10 r13 ASR 5", "al_r10_r13_ASR_5"}, 585 {{al, r7, r2, ASR, 24}, false, al, "al r7 r2 ASR 24", "al_r7_r2_ASR_24"}, 586 {{al, r6, r5, LSR, 30}, false, al, "al r6 r5 LSR 30", "al_r6_r5_LSR_30"}, 587 {{al, r0, r11, ASR, 4}, false, al, "al r0 r11 ASR 4", "al_r0_r11_ASR_4"}, 588 {{al, r10, r8, ASR, 18}, false, al, "al r10 r8 ASR 18", "al_r10_r8_ASR_18"}, 589 {{al, r4, r11, LSR, 12}, false, al, "al r4 r11 LSR 12", "al_r4_r11_LSR_12"}, 590 {{al, r4, r7, ASR, 11}, false, al, "al r4 r7 ASR 11", "al_r4_r7_ASR_11"}, 591 {{al, r1, r10, LSR, 32}, false, al, "al r1 r10 LSR 32", "al_r1_r10_LSR_32"}, 592 {{al, r9, r11, ASR, 31}, false, al, "al r9 r11 ASR 31", "al_r9_r11_ASR_31"}, 593 {{al, r2, r6, ASR, 23}, false, al, "al r2 r6 ASR 23", "al_r2_r6_ASR_23"}, 594 {{al, r9, r14, LSR, 16}, false, al, "al r9 r14 LSR 16", "al_r9_r14_LSR_16"}, 595 {{al, r0, r14, ASR, 18}, false, al, "al r0 r14 ASR 18", "al_r0_r14_ASR_18"}, 596 {{al, r5, r6, LSR, 29}, false, al, "al r5 r6 LSR 29", "al_r5_r6_LSR_29"}, 597 {{al, r12, r9, LSR, 16}, false, al, "al r12 r9 LSR 16", "al_r12_r9_LSR_16"}, 598 {{al, r5, r9, LSR, 9}, false, al, "al r5 r9 LSR 9", "al_r5_r9_LSR_9"}, 599 {{al, r13, r9, LSR, 18}, false, al, "al r13 r9 LSR 18", "al_r13_r9_LSR_18"}, 600 {{al, r2, r11, ASR, 21}, false, al, "al r2 r11 ASR 21", "al_r2_r11_ASR_21"}, 601 {{al, r3, r2, LSR, 17}, false, al, "al r3 r2 LSR 17", "al_r3_r2_LSR_17"}, 602 {{al, r3, r13, ASR, 21}, false, al, "al r3 r13 ASR 21", "al_r3_r13_ASR_21"}, 603 {{al, r5, r2, LSR, 26}, false, al, "al r5 r2 LSR 26", "al_r5_r2_LSR_26"}, 604 {{al, r12, r1, LSR, 13}, false, al, "al r12 r1 LSR 13", "al_r12_r1_LSR_13"}, 605 {{al, r8, r7, ASR, 15}, false, al, "al r8 r7 ASR 15", "al_r8_r7_ASR_15"}, 606 {{al, r8, r1, LSR, 24}, false, al, "al r8 r1 LSR 24", "al_r8_r1_LSR_24"}, 607 {{al, r0, r12, ASR, 8}, false, al, "al r0 r12 ASR 8", "al_r0_r12_ASR_8"}, 608 {{al, r13, r10, ASR, 30}, 609 false, 610 al, 611 "al r13 r10 ASR 30", 612 "al_r13_r10_ASR_30"}, 613 {{al, r14, r10, ASR, 31}, 614 false, 615 al, 616 "al r14 r10 ASR 31", 617 "al_r14_r10_ASR_31"}, 618 {{al, r0, r0, LSR, 26}, false, al, "al r0 r0 LSR 26", "al_r0_r0_LSR_26"}, 619 {{al, r14, r4, ASR, 17}, false, al, "al r14 r4 ASR 17", "al_r14_r4_ASR_17"}, 620 {{al, r0, r13, LSR, 19}, false, al, "al r0 r13 LSR 19", "al_r0_r13_LSR_19"}, 621 {{al, r1, r9, ASR, 17}, false, al, "al r1 r9 ASR 17", "al_r1_r9_ASR_17"}, 622 {{al, r3, r11, ASR, 6}, false, al, "al r3 r11 ASR 6", "al_r3_r11_ASR_6"}, 623 {{al, r5, r1, LSR, 3}, false, al, "al r5 r1 LSR 3", "al_r5_r1_LSR_3"}, 624 {{al, r11, r3, LSR, 8}, false, al, "al r11 r3 LSR 8", "al_r11_r3_LSR_8"}, 625 {{al, r12, r3, LSR, 4}, false, al, "al r12 r3 LSR 4", "al_r12_r3_LSR_4"}, 626 {{al, r14, r5, ASR, 8}, false, al, "al r14 r5 ASR 8", "al_r14_r5_ASR_8"}, 627 {{al, r8, r7, LSR, 9}, false, al, "al r8 r7 LSR 9", "al_r8_r7_LSR_9"}, 628 {{al, r2, r2, ASR, 8}, false, al, "al r2 r2 ASR 8", "al_r2_r2_ASR_8"}, 629 {{al, r0, r14, ASR, 16}, false, al, "al r0 r14 ASR 16", "al_r0_r14_ASR_16"}, 630 {{al, r6, r14, LSR, 4}, false, al, "al r6 r14 LSR 4", "al_r6_r14_LSR_4"}, 631 {{al, r8, r5, ASR, 32}, false, al, "al r8 r5 ASR 32", "al_r8_r5_ASR_32"}, 632 {{al, r1, r14, LSR, 16}, false, al, "al r1 r14 LSR 16", "al_r1_r14_LSR_16"}, 633 {{al, r9, r11, LSR, 13}, false, al, "al r9 r11 LSR 13", "al_r9_r11_LSR_13"}, 634 {{al, r7, r6, ASR, 9}, false, al, "al r7 r6 ASR 9", "al_r7_r6_ASR_9"}, 635 {{al, r7, r6, ASR, 3}, false, al, "al r7 r6 ASR 3", "al_r7_r6_ASR_3"}, 636 {{al, r10, r3, LSR, 16}, false, al, "al r10 r3 LSR 16", "al_r10_r3_LSR_16"}, 637 {{al, r6, r4, ASR, 13}, false, al, "al r6 r4 ASR 13", "al_r6_r4_ASR_13"}, 638 {{al, r9, r7, ASR, 7}, false, al, "al r9 r7 ASR 7", "al_r9_r7_ASR_7"}, 639 {{al, r13, r12, LSR, 30}, 640 false, 641 al, 642 "al r13 r12 LSR 30", 643 "al_r13_r12_LSR_30"}, 644 {{al, r12, r9, LSR, 24}, false, al, "al r12 r9 LSR 24", "al_r12_r9_LSR_24"}, 645 {{al, r7, r2, ASR, 2}, false, al, "al r7 r2 ASR 2", "al_r7_r2_ASR_2"}, 646 {{al, r14, r12, ASR, 13}, 647 false, 648 al, 649 "al r14 r12 ASR 13", 650 "al_r14_r12_ASR_13"}, 651 {{al, r1, r5, LSR, 24}, false, al, "al r1 r5 LSR 24", "al_r1_r5_LSR_24"}, 652 {{al, r13, r2, ASR, 28}, false, al, "al r13 r2 ASR 28", "al_r13_r2_ASR_28"}, 653 {{al, r7, r5, LSR, 16}, false, al, "al r7 r5 LSR 16", "al_r7_r5_LSR_16"}, 654 {{al, r4, r0, ASR, 4}, false, al, "al r4 r0 ASR 4", "al_r4_r0_ASR_4"}, 655 {{al, r9, r9, ASR, 31}, false, al, "al r9 r9 ASR 31", "al_r9_r9_ASR_31"}, 656 {{al, r5, r5, ASR, 10}, false, al, "al r5 r5 ASR 10", "al_r5_r5_ASR_10"}, 657 {{al, r3, r8, ASR, 19}, false, al, "al r3 r8 ASR 19", "al_r3_r8_ASR_19"}, 658 {{al, r8, r12, ASR, 22}, false, al, "al r8 r12 ASR 22", "al_r8_r12_ASR_22"}, 659 {{al, r4, r10, LSR, 8}, false, al, "al r4 r10 LSR 8", "al_r4_r10_LSR_8"}, 660 {{al, r1, r11, LSR, 32}, false, al, "al r1 r11 LSR 32", "al_r1_r11_LSR_32"}, 661 {{al, r12, r13, LSR, 14}, 662 false, 663 al, 664 "al r12 r13 LSR 14", 665 "al_r12_r13_LSR_14"}, 666 {{al, r13, r0, LSR, 12}, false, al, "al r13 r0 LSR 12", "al_r13_r0_LSR_12"}, 667 {{al, r12, r1, LSR, 5}, false, al, "al r12 r1 LSR 5", "al_r12_r1_LSR_5"}, 668 {{al, r10, r8, ASR, 9}, false, al, "al r10 r8 ASR 9", "al_r10_r8_ASR_9"}, 669 {{al, r11, r2, LSR, 22}, false, al, "al r11 r2 LSR 22", "al_r11_r2_LSR_22"}, 670 {{al, r11, r3, ASR, 24}, false, al, "al r11 r3 ASR 24", "al_r11_r3_ASR_24"}, 671 {{al, r3, r11, ASR, 9}, false, al, "al r3 r11 ASR 9", "al_r3_r11_ASR_9"}, 672 {{al, r0, r7, LSR, 20}, false, al, "al r0 r7 LSR 20", "al_r0_r7_LSR_20"}, 673 {{al, r13, r11, LSR, 19}, 674 false, 675 al, 676 "al r13 r11 LSR 19", 677 "al_r13_r11_LSR_19"}, 678 {{al, r9, r3, LSR, 19}, false, al, "al r9 r3 LSR 19", "al_r9_r3_LSR_19"}, 679 {{al, r8, r12, LSR, 13}, false, al, "al r8 r12 LSR 13", "al_r8_r12_LSR_13"}, 680 {{al, r9, r4, ASR, 10}, false, al, "al r9 r4 ASR 10", "al_r9_r4_ASR_10"}, 681 {{al, r10, r6, LSR, 22}, false, al, "al r10 r6 LSR 22", "al_r10_r6_LSR_22"}, 682 {{al, r1, r14, ASR, 3}, false, al, "al r1 r14 ASR 3", "al_r1_r14_ASR_3"}, 683 {{al, r0, r11, LSR, 15}, false, al, "al r0 r11 LSR 15", "al_r0_r11_LSR_15"}, 684 {{al, r7, r14, LSR, 9}, false, al, "al r7 r14 LSR 9", "al_r7_r14_LSR_9"}, 685 {{al, r14, r7, ASR, 5}, false, al, "al r14 r7 ASR 5", "al_r14_r7_ASR_5"}, 686 {{al, r5, r0, ASR, 20}, false, al, "al r5 r0 ASR 20", "al_r5_r0_ASR_20"}, 687 {{al, r3, r3, ASR, 3}, false, al, "al r3 r3 ASR 3", "al_r3_r3_ASR_3"}, 688 {{al, r12, r13, ASR, 19}, 689 false, 690 al, 691 "al r12 r13 ASR 19", 692 "al_r12_r13_ASR_19"}, 693 {{al, r3, r10, LSR, 15}, false, al, "al r3 r10 LSR 15", "al_r3_r10_LSR_15"}, 694 {{al, r0, r4, LSR, 30}, false, al, "al r0 r4 LSR 30", "al_r0_r4_LSR_30"}, 695 {{al, r4, r12, ASR, 32}, false, al, "al r4 r12 ASR 32", "al_r4_r12_ASR_32"}, 696 {{al, r7, r13, ASR, 14}, false, al, "al r7 r13 ASR 14", "al_r7_r13_ASR_14"}, 697 {{al, r13, r8, LSR, 2}, false, al, "al r13 r8 LSR 2", "al_r13_r8_LSR_2"}, 698 {{al, r11, r1, LSR, 9}, false, al, "al r11 r1 LSR 9", "al_r11_r1_LSR_9"}, 699 {{al, r1, r12, LSR, 30}, false, al, "al r1 r12 LSR 30", "al_r1_r12_LSR_30"}, 700 {{al, r3, r4, ASR, 27}, false, al, "al r3 r4 ASR 27", "al_r3_r4_ASR_27"}, 701 {{al, r2, r0, LSR, 12}, false, al, "al r2 r0 LSR 12", "al_r2_r0_LSR_12"}, 702 {{al, r9, r14, ASR, 17}, false, al, "al r9 r14 ASR 17", "al_r9_r14_ASR_17"}, 703 {{al, r2, r0, LSR, 9}, false, al, "al r2 r0 LSR 9", "al_r2_r0_LSR_9"}, 704 {{al, r0, r3, ASR, 19}, false, al, "al r0 r3 ASR 19", "al_r0_r3_ASR_19"}, 705 {{al, r1, r8, LSR, 18}, false, al, "al r1 r8 LSR 18", "al_r1_r8_LSR_18"}, 706 {{al, r2, r2, ASR, 20}, false, al, "al r2 r2 ASR 20", "al_r2_r2_ASR_20"}, 707 {{al, r5, r9, LSR, 28}, false, al, "al r5 r9 LSR 28", "al_r5_r9_LSR_28"}, 708 {{al, r8, r14, ASR, 1}, false, al, "al r8 r14 ASR 1", "al_r8_r14_ASR_1"}, 709 {{al, r0, r12, ASR, 7}, false, al, "al r0 r12 ASR 7", "al_r0_r12_ASR_7"}, 710 {{al, r4, r13, ASR, 22}, false, al, "al r4 r13 ASR 22", "al_r4_r13_ASR_22"}, 711 {{al, r9, r3, LSR, 3}, false, al, "al r9 r3 LSR 3", "al_r9_r3_LSR_3"}, 712 {{al, r6, r7, ASR, 26}, false, al, "al r6 r7 ASR 26", "al_r6_r7_ASR_26"}, 713 {{al, r11, r7, LSR, 16}, false, al, "al r11 r7 LSR 16", "al_r11_r7_LSR_16"}, 714 {{al, r12, r1, LSR, 12}, false, al, "al r12 r1 LSR 12", "al_r12_r1_LSR_12"}, 715 {{al, r3, r4, LSR, 12}, false, al, "al r3 r4 LSR 12", "al_r3_r4_LSR_12"}, 716 {{al, r13, r9, LSR, 15}, false, al, "al r13 r9 LSR 15", "al_r13_r9_LSR_15"}, 717 {{al, r4, r5, LSR, 7}, false, al, "al r4 r5 LSR 7", "al_r4_r5_LSR_7"}, 718 {{al, r1, r13, ASR, 18}, false, al, "al r1 r13 ASR 18", "al_r1_r13_ASR_18"}, 719 {{al, r7, r8, LSR, 20}, false, al, "al r7 r8 LSR 20", "al_r7_r8_LSR_20"}, 720 {{al, r1, r4, LSR, 19}, false, al, "al r1 r4 LSR 19", "al_r1_r4_LSR_19"}, 721 {{al, r13, r5, LSR, 2}, false, al, "al r13 r5 LSR 2", "al_r13_r5_LSR_2"}, 722 {{al, r2, r9, LSR, 23}, false, al, "al r2 r9 LSR 23", "al_r2_r9_LSR_23"}, 723 {{al, r0, r0, LSR, 17}, false, al, "al r0 r0 LSR 17", "al_r0_r0_LSR_17"}, 724 {{al, r6, r7, LSR, 12}, false, al, "al r6 r7 LSR 12", "al_r6_r7_LSR_12"}, 725 {{al, r14, r10, ASR, 11}, 726 false, 727 al, 728 "al r14 r10 ASR 11", 729 "al_r14_r10_ASR_11"}, 730 {{al, r2, r10, LSR, 14}, false, al, "al r2 r10 LSR 14", "al_r2_r10_LSR_14"}, 731 {{al, r11, r1, LSR, 30}, false, al, "al r11 r1 LSR 30", "al_r11_r1_LSR_30"}, 732 {{al, r2, r8, ASR, 10}, false, al, "al r2 r8 ASR 10", "al_r2_r8_ASR_10"}, 733 {{al, r6, r10, ASR, 3}, false, al, "al r6 r10 ASR 3", "al_r6_r10_ASR_3"}, 734 {{al, r3, r4, LSR, 25}, false, al, "al r3 r4 LSR 25", "al_r3_r4_LSR_25"}, 735 {{al, r1, r1, ASR, 11}, false, al, "al r1 r1 ASR 11", "al_r1_r1_ASR_11"}, 736 {{al, r13, r6, LSR, 30}, false, al, "al r13 r6 LSR 30", "al_r13_r6_LSR_30"}, 737 {{al, r5, r6, ASR, 23}, false, al, "al r5 r6 ASR 23", "al_r5_r6_ASR_23"}, 738 {{al, r1, r6, LSR, 12}, false, al, "al r1 r6 LSR 12", "al_r1_r6_LSR_12"}, 739 {{al, r0, r0, LSR, 2}, false, al, "al r0 r0 LSR 2", "al_r0_r0_LSR_2"}, 740 {{al, r13, r13, ASR, 14}, 741 false, 742 al, 743 "al r13 r13 ASR 14", 744 "al_r13_r13_ASR_14"}, 745 {{al, r9, r12, ASR, 31}, false, al, "al r9 r12 ASR 31", "al_r9_r12_ASR_31"}, 746 {{al, r8, r6, ASR, 24}, false, al, "al r8 r6 ASR 24", "al_r8_r6_ASR_24"}, 747 {{al, r10, r5, ASR, 19}, false, al, "al r10 r5 ASR 19", "al_r10_r5_ASR_19"}, 748 {{al, r6, r13, LSR, 5}, false, al, "al r6 r13 LSR 5", "al_r6_r13_LSR_5"}, 749 {{al, r1, r0, LSR, 15}, false, al, "al r1 r0 LSR 15", "al_r1_r0_LSR_15"}, 750 {{al, r9, r2, LSR, 11}, false, al, "al r9 r2 LSR 11", "al_r9_r2_LSR_11"}, 751 {{al, r14, r0, ASR, 30}, false, al, "al r14 r0 ASR 30", "al_r14_r0_ASR_30"}, 752 {{al, r0, r1, ASR, 28}, false, al, "al r0 r1 ASR 28", "al_r0_r1_ASR_28"}, 753 {{al, r4, r7, ASR, 4}, false, al, "al r4 r7 ASR 4", "al_r4_r7_ASR_4"}, 754 {{al, r0, r13, ASR, 17}, false, al, "al r0 r13 ASR 17", "al_r0_r13_ASR_17"}, 755 {{al, r10, r1, LSR, 17}, false, al, "al r10 r1 LSR 17", "al_r10_r1_LSR_17"}, 756 {{al, r8, r6, LSR, 25}, false, al, "al r8 r6 LSR 25", "al_r8_r6_LSR_25"}, 757 {{al, r2, r6, ASR, 2}, false, al, "al r2 r6 ASR 2", "al_r2_r6_ASR_2"}, 758 {{al, r6, r12, ASR, 18}, false, al, "al r6 r12 ASR 18", "al_r6_r12_ASR_18"}, 759 {{al, r4, r7, ASR, 27}, false, al, "al r4 r7 ASR 27", "al_r4_r7_ASR_27"}, 760 {{al, r9, r12, LSR, 21}, false, al, "al r9 r12 LSR 21", "al_r9_r12_LSR_21"}, 761 {{al, r13, r9, ASR, 7}, false, al, "al r13 r9 ASR 7", "al_r13_r9_ASR_7"}, 762 {{al, r13, r0, ASR, 29}, false, al, "al r13 r0 ASR 29", "al_r13_r0_ASR_29"}, 763 {{al, r11, r4, ASR, 19}, false, al, "al r11 r4 ASR 19", "al_r11_r4_ASR_19"}, 764 {{al, r7, r9, ASR, 28}, false, al, "al r7 r9 ASR 28", "al_r7_r9_ASR_28"}, 765 {{al, r6, r7, LSR, 32}, false, al, "al r6 r7 LSR 32", "al_r6_r7_LSR_32"}, 766 {{al, r11, r13, ASR, 21}, 767 false, 768 al, 769 "al r11 r13 ASR 21", 770 "al_r11_r13_ASR_21"}, 771 {{al, r14, r6, LSR, 29}, false, al, "al r14 r6 LSR 29", "al_r14_r6_LSR_29"}, 772 {{al, r5, r13, LSR, 10}, false, al, "al r5 r13 LSR 10", "al_r5_r13_LSR_10"}, 773 {{al, r9, r4, ASR, 17}, false, al, "al r9 r4 ASR 17", "al_r9_r4_ASR_17"}, 774 {{al, r13, r4, ASR, 32}, false, al, "al r13 r4 ASR 32", "al_r13_r4_ASR_32"}, 775 {{al, r1, r12, ASR, 7}, false, al, "al r1 r12 ASR 7", "al_r1_r12_ASR_7"}, 776 {{al, r13, r1, LSR, 25}, false, al, "al r13 r1 LSR 25", "al_r13_r1_LSR_25"}, 777 {{al, r7, r0, ASR, 5}, false, al, "al r7 r0 ASR 5", "al_r7_r0_ASR_5"}, 778 {{al, r1, r13, ASR, 15}, false, al, "al r1 r13 ASR 15", "al_r1_r13_ASR_15"}, 779 {{al, r3, r14, ASR, 8}, false, al, "al r3 r14 ASR 8", "al_r3_r14_ASR_8"}, 780 {{al, r2, r14, LSR, 26}, false, al, "al r2 r14 LSR 26", "al_r2_r14_LSR_26"}, 781 {{al, r13, r9, ASR, 22}, false, al, "al r13 r9 ASR 22", "al_r13_r9_ASR_22"}, 782 {{al, r10, r3, LSR, 17}, false, al, "al r10 r3 LSR 17", "al_r10_r3_LSR_17"}, 783 {{al, r14, r7, LSR, 7}, false, al, "al r14 r7 LSR 7", "al_r14_r7_LSR_7"}, 784 {{al, r14, r13, LSR, 29}, 785 false, 786 al, 787 "al r14 r13 LSR 29", 788 "al_r14_r13_LSR_29"}, 789 {{al, r14, r0, ASR, 12}, false, al, "al r14 r0 ASR 12", "al_r14_r0_ASR_12"}, 790 {{al, r3, r3, ASR, 20}, false, al, "al r3 r3 ASR 20", "al_r3_r3_ASR_20"}, 791 {{al, r2, r7, ASR, 32}, false, al, "al r2 r7 ASR 32", "al_r2_r7_ASR_32"}, 792 {{al, r12, r13, LSR, 23}, 793 false, 794 al, 795 "al r12 r13 LSR 23", 796 "al_r12_r13_LSR_23"}, 797 {{al, r8, r3, ASR, 5}, false, al, "al r8 r3 ASR 5", "al_r8_r3_ASR_5"}, 798 {{al, r9, r0, LSR, 28}, false, al, "al r9 r0 LSR 28", "al_r9_r0_LSR_28"}, 799 {{al, r8, r13, LSR, 22}, false, al, "al r8 r13 LSR 22", "al_r8_r13_LSR_22"}, 800 {{al, r4, r3, LSR, 1}, false, al, "al r4 r3 LSR 1", "al_r4_r3_LSR_1"}, 801 {{al, r1, r2, ASR, 5}, false, al, "al r1 r2 ASR 5", "al_r1_r2_ASR_5"}, 802 {{al, r14, r1, LSR, 26}, false, al, "al r14 r1 LSR 26", "al_r14_r1_LSR_26"}, 803 {{al, r14, r11, ASR, 17}, 804 false, 805 al, 806 "al r14 r11 ASR 17", 807 "al_r14_r11_ASR_17"}}; 808 809 // These headers each contain an array of `TestResult` with the reference output 810 // values. The reference arrays are names `kReference{mnemonic}`. 811 #include "aarch32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-cmn-t32.h" 812 #include "aarch32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-cmp-t32.h" 813 #include "aarch32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-mov-t32.h" 814 #include "aarch32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-movs-t32.h" 815 #include "aarch32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-mvn-t32.h" 816 #include "aarch32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-mvns-t32.h" 817 #include "aarch32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-teq-t32.h" 818 #include "aarch32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-tst-t32.h" 819 820 821 // The maximum number of errors to report in detail for each test. 822 const unsigned kErrorReportLimit = 8; 823 824 typedef void (MacroAssembler::*Fn)(Condition cond, 825 Register rd, 826 const Operand& op); 827 828 void TestHelper(Fn instruction, 829 const char* mnemonic, 830 const TestResult reference[]) { 831 unsigned total_error_count = 0; 832 MacroAssembler masm(BUF_SIZE); 833 834 masm.UseT32(); 835 836 for (unsigned i = 0; i < ARRAY_SIZE(kTests); i++) { 837 // Values to pass to the macro-assembler. 838 Condition cond = kTests[i].operands.cond; 839 Register rd = kTests[i].operands.rd; 840 Register rn = kTests[i].operands.rn; 841 ShiftType shift = kTests[i].operands.shift; 842 uint32_t amount = kTests[i].operands.amount; 843 Operand op(rn, shift, amount); 844 845 int32_t start = masm.GetCursorOffset(); 846 { 847 // We never generate more that 4 bytes, as IT instructions are only 848 // allowed for narrow encodings. 849 ExactAssemblyScope scope(&masm, 4, ExactAssemblyScope::kMaximumSize); 850 if (kTests[i].in_it_block) { 851 masm.it(kTests[i].it_condition); 852 } 853 (masm.*instruction)(cond, rd, op); 854 } 855 int32_t end = masm.GetCursorOffset(); 856 857 const byte* result_ptr = 858 masm.GetBuffer()->GetOffsetAddress<const byte*>(start); 859 VIXL_ASSERT(start < end); 860 uint32_t result_size = end - start; 861 862 if (Test::generate_test_trace()) { 863 // Print the result bytes. 864 printf("const byte kInstruction_%s_%s[] = {\n", 865 mnemonic, 866 kTests[i].identifier); 867 for (uint32_t j = 0; j < result_size; j++) { 868 if (j == 0) { 869 printf(" 0x%02" PRIx8, result_ptr[j]); 870 } else { 871 printf(", 0x%02" PRIx8, result_ptr[j]); 872 } 873 } 874 // This comment is meant to be used by external tools to validate 875 // the encoding. We can parse the comment to figure out what 876 // instruction this corresponds to. 877 if (kTests[i].in_it_block) { 878 printf(" // It %s; %s %s\n};\n", 879 kTests[i].it_condition.GetName(), 880 mnemonic, 881 kTests[i].operands_description); 882 } else { 883 printf(" // %s %s\n};\n", mnemonic, kTests[i].operands_description); 884 } 885 } else { 886 // Check we've emitted the exact same encoding as present in the 887 // trace file. Only print up to `kErrorReportLimit` errors. 888 if (((result_size != reference[i].size) || 889 (memcmp(result_ptr, reference[i].encoding, reference[i].size) != 890 0)) && 891 (++total_error_count <= kErrorReportLimit)) { 892 printf("Error when testing \"%s\" with operands \"%s\":\n", 893 mnemonic, 894 kTests[i].operands_description); 895 printf(" Expected: "); 896 for (uint32_t j = 0; j < reference[i].size; j++) { 897 if (j == 0) { 898 printf("0x%02" PRIx8, reference[i].encoding[j]); 899 } else { 900 printf(", 0x%02" PRIx8, reference[i].encoding[j]); 901 } 902 } 903 printf("\n"); 904 printf(" Found: "); 905 for (uint32_t j = 0; j < result_size; j++) { 906 if (j == 0) { 907 printf("0x%02" PRIx8, result_ptr[j]); 908 } else { 909 printf(", 0x%02" PRIx8, result_ptr[j]); 910 } 911 } 912 printf("\n"); 913 } 914 } 915 } 916 917 masm.FinalizeCode(); 918 919 if (Test::generate_test_trace()) { 920 // Finalize the trace file by writing the final `TestResult` array 921 // which links all generated instruction encodings. 922 printf("const TestResult kReference%s[] = {\n", mnemonic); 923 for (unsigned i = 0; i < ARRAY_SIZE(kTests); i++) { 924 printf(" {\n"); 925 printf(" ARRAY_SIZE(kInstruction_%s_%s),\n", 926 mnemonic, 927 kTests[i].identifier); 928 printf(" kInstruction_%s_%s,\n", mnemonic, kTests[i].identifier); 929 printf(" },\n"); 930 } 931 printf("};\n"); 932 } else { 933 if (total_error_count > kErrorReportLimit) { 934 printf("%u other errors follow.\n", 935 total_error_count - kErrorReportLimit); 936 } 937 // Crash if the test failed. 938 VIXL_CHECK(total_error_count == 0); 939 } 940 } 941 942 // Instantiate tests for each instruction in the list. 943 #define TEST(mnemonic) \ 944 void Test_##mnemonic() { \ 945 TestHelper(&MacroAssembler::mnemonic, #mnemonic, kReference##mnemonic); \ 946 } \ 947 Test test_##mnemonic( \ 948 "AARCH32_ASSEMBLER_COND_RD_OPERAND_RN_SHIFT_AMOUNT_1TO32_" #mnemonic \ 949 "_T32", \ 950 &Test_##mnemonic); 951 FOREACH_INSTRUCTION(TEST) 952 #undef TEST 953 954 } // namespace 955 #endif 956 957 } // namespace aarch32 958 } // namespace vixl 959
