1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __UART_16550_H__ 8 #define __UART_16550_H__ 9 10 /* UART16550 Registers */ 11 #define UARTTX 0x0 12 #define UARTRX 0x0 13 #define UARTDLL 0x0 14 #define UARTIER 0x4 15 #define UARTDLLM 0x4 16 #define UARTIIR 0x8 17 #define UARTFCR 0x8 18 #define UARTLCR 0xc 19 #define UARTMCR 0x10 20 #define UARTLSR 0x14 21 #define UARTMSR 0x18 22 #define UARTSPR 0x1c 23 #define UARTCSR 0x20 24 #define UARTRXFIFOCFG 0x24 25 #define UARTMIE 0x28 26 #define UARTVNDR 0x2c 27 #define UARTASR 0x3c 28 29 /* FIFO Control Register bits */ 30 #define UARTFCR_FIFOMD_16450 (0 << 6) 31 #define UARTFCR_FIFOMD_16550 (1 << 6) 32 #define UARTFCR_RXTRIG_1 (0 << 6) 33 #define UARTFCR_RXTRIG_4 (1 << 6) 34 #define UARTFCR_RXTRIG_8 (2 << 6) 35 #define UARTFCR_RXTRIG_16 (3 << 6) 36 #define UARTFCR_TXTRIG_1 (0 << 4) 37 #define UARTFCR_TXTRIG_4 (1 << 4) 38 #define UARTFCR_TXTRIG_8 (2 << 4) 39 #define UARTFCR_TXTRIG_16 (3 << 4) 40 #define UARTFCR_DMAEN (1 << 3) /* Enable DMA mode */ 41 #define UARTFCR_TXCLR (1 << 2) /* Clear contents of Tx FIFO */ 42 #define UARTFCR_RXCLR (1 << 1) /* Clear contents of Rx FIFO */ 43 #define UARTFCR_FIFOEN (1 << 0) /* Enable the Tx/Rx FIFO */ 44 45 /* Line Control Register bits */ 46 #define UARTLCR_DLAB (1 << 7) /* Divisor Latch Access */ 47 #define UARTLCR_SETB (1 << 6) /* Set BREAK Condition */ 48 #define UARTLCR_SETP (1 << 5) /* Set Parity to LCR[4] */ 49 #define UARTLCR_EVEN (1 << 4) /* Even Parity Format */ 50 #define UARTLCR_PAR (1 << 3) /* Parity */ 51 #define UARTLCR_STOP (1 << 2) /* Stop Bit */ 52 #define UARTLCR_WORDSZ_5 0 /* Word Length of 5 */ 53 #define UARTLCR_WORDSZ_6 1 /* Word Length of 6 */ 54 #define UARTLCR_WORDSZ_7 2 /* Word Length of 7 */ 55 #define UARTLCR_WORDSZ_8 3 /* Word Length of 8 */ 56 57 /* Line Status Register bits */ 58 #define UARTLSR_RXFIFOEMT (1 << 9) /* Rx Fifo Empty */ 59 #define UARTLSR_TXFIFOFULL (1 << 8) /* Tx Fifo Full */ 60 #define UARTLSR_RXFIFOERR (1 << 7) /* Rx Fifo Error */ 61 #define UARTLSR_TEMT (1 << 6) /* Tx Shift Register Empty */ 62 #define UARTLSR_THRE (1 << 5) /* Tx Holding Register Empty */ 63 #define UARTLSR_BRK (1 << 4) /* Break Condition Detected */ 64 #define UARTLSR_FERR (1 << 3) /* Framing Error */ 65 #define UARTLSR_PERR (1 << 3) /* Parity Error */ 66 #define UARTLSR_OVRF (1 << 2) /* Rx Overrun Error */ 67 #define UARTLSR_RDR_BIT (0) /* Rx Data Ready Bit */ 68 #define UARTLSR_RDR (1 << UARTLSR_RDR_BIT) /* Rx Data Ready */ 69 70 #endif /* __UART_16550_H__ */ 71
