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  /external/mesa3d/src/mesa/program/
prog_instruction.c 54 inst[i].DstReg.WriteMask = WRITEMASK_XYZW;
210 if (inst->DstReg.WriteMask == WRITEMASK_X ||
211 inst->DstReg.WriteMask == WRITEMASK_Y ||
212 inst->DstReg.WriteMask == WRITEMASK_Z ||
213 inst->DstReg.WriteMask == WRITEMASK_W ||
214 inst->DstReg.WriteMask == 0x0) {
226 if (inst->DstReg.WriteMask & (1 << chan)) {
prog_optimize.c 79 channel_mask = inst->DstReg.WriteMask & dst_mask;
123 const GLuint mask = mov->DstReg.WriteMask;
309 inst->DstReg.WriteMask & (1 << chan)) {
311 printf("Remove writemask on %u.%c\n", i,
314 inst->DstReg.WriteMask &= ~(1 << chan);
319 if (inst->DstReg.WriteMask == 0) {
398 mask &= ~inst->DstReg.WriteMask;
494 dst_mask = mov->DstReg.WriteMask;
543 dst_mask &= ~inst2->DstReg.WriteMask;
551 src_mask &= ~inst2->DstReg.WriteMask;
    [all...]
programopt.c 92 newInst[i].DstReg.WriteMask = (WRITEMASK_X << i);
163 newInst[0].DstReg.WriteMask = WRITEMASK_XYZW;
175 newInst[i].DstReg.WriteMask = WRITEMASK_XYZW;
190 newInst[3].DstReg.WriteMask = WRITEMASK_XYZW;
321 inst->DstReg.WriteMask = WRITEMASK_X;
342 inst->DstReg.WriteMask = WRITEMASK_X;
356 inst->DstReg.WriteMask = WRITEMASK_X;
369 inst->DstReg.WriteMask = WRITEMASK_X;
381 inst->DstReg.WriteMask = WRITEMASK_XYZ;
396 inst->DstReg.WriteMask = WRITEMASK_W
    [all...]
  /external/mesa3d/src/gallium/drivers/r300/compiler/
radeon_pair_translate.c 90 *needrgb = (inst->DstReg.WriteMask & RC_MASK_XYZ) ? 1 : 0;
91 *needalpha = (inst->DstReg.WriteMask & RC_MASK_W) ? 1 : 0;
275 inst->DstReg.WriteMask);
286 pair->Alpha.DepthWriteMask |= GET_BIT(inst->DstReg.WriteMask, 3);
293 inst->DstReg.WriteMask & RC_MASK_XYZ;
295 GET_BIT(inst->DstReg.WriteMask, 3);
303 pair->RGB.WriteMask |= inst->DstReg.WriteMask & RC_MASK_XYZ;
307 pair->Alpha.WriteMask |= (GET_BIT(inst->DstReg.WriteMask, 3) << 3)
    [all...]
r3xx_fragprog.c 64 if (inst->DstReg.WriteMask & RC_MASK_Z) {
65 inst->DstReg.WriteMask = RC_MASK_W;
67 inst->DstReg.WriteMask = 0;
radeon_dataflow_deadcode.c 41 unsigned char WriteMask:4;
162 usedmask = *pused & inst->U.I.DstReg.WriteMask;
167 insts->WriteMask |= usedmask;
257 ptr->U.I.DstReg.WriteMask, srcmasks);
324 inst->U.I.DstReg.WriteMask = s.Instructions[ip].WriteMask;
325 if (s.Instructions[ip].WriteMask)
341 usemask = s.Instructions[ip].WriteMask;
radeon_variable.c 39 * Rewrite the index and writemask for the destination register of var
61 if (var_ptr->Dst.WriteMask == RC_MASK_W) {
157 unsigned int mask = var->Readers[i].WriteMask;
286 new->Dst.WriteMask = DstWriteMask;
321 unsigned int writemask; local
333 if (sub_inst->WriteMask) {
335 writemask = sub_inst->WriteMask;
338 writemask = sub_inst->OutputWriteMask;
340 writemask = 0
393 unsigned int writemask = 0; local
    [all...]
radeon_program.h 60 unsigned int WriteMask:4;
radeon_program_pair.h 74 unsigned int WriteMask:4;
radeon_program_tex.c 92 inst_rcp->U.I.DstReg.WriteMask = RC_MASK_W;
173 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
183 inst_rcp->U.I.DstReg.WriteMask = RC_MASK_W;
194 inst_mul->U.I.DstReg.WriteMask = RC_MASK_W;
210 inst_add->U.I.DstReg.WriteMask = RC_MASK_W;
311 inst_frc->U.I.DstReg.WriteMask = RC_MASK_XYZ;
333 inst_mul->U.I.DstReg.WriteMask = RC_MASK_XYZ;
342 inst_frc->U.I.DstReg.WriteMask = RC_MASK_XYZ;
353 inst_mad->U.I.DstReg.WriteMask = RC_MASK_XYZ;
368 inst_add->U.I.DstReg.WriteMask = RC_MASK_XYZ
    [all...]
radeon_dataflow.h 76 unsigned int WriteMask;
  /external/mesa3d/src/gallium/drivers/i915/
i915_fpc_optimize.c 193 * of writemask which are set, swizzle to identity otherwise.
237 o->WriteMask = i->WriteMask;
460 if (dst_reg2->Register.WriteMask & TGSI_WRITEMASK_X)
462 if (dst_reg2->Register.WriteMask & TGSI_WRITEMASK_Y)
464 if (dst_reg2->Register.WriteMask & TGSI_WRITEMASK_Z)
466 if (dst_reg2->Register.WriteMask & TGSI_WRITEMASK_W)
469 dst_reg2->Register.WriteMask |= dst_reg1->Register.WriteMask;
499 is_unswizzled(&current->FullInstruction.Src[0], current->FullInstruction.Dst[0].Register.WriteMask) &
    [all...]
  /external/mesa3d/src/mesa/drivers/dri/i965/
gen8_wm_depth_stencil.c 59 SET_FIELD(stencil->WriteMask[0] & 0xff, GEN8_WM_DS_STENCIL_WRITE_MASK) |
72 dw2 |= SET_FIELD(stencil->WriteMask[b] & 0xff,
gen6_depthstencil.c 62 ds->ds1.stencil_write_mask = ctx->Stencil.WriteMask[0];
75 ds->ds1.bf_stencil_write_mask = ctx->Stencil.WriteMask[back];
brw_cc.c 137 cc->cc1.stencil_write_mask = ctx->Stencil.WriteMask[0];
151 cc->cc2.bf_stencil_write_mask = ctx->Stencil.WriteMask[back];
157 if (ctx->Stencil.WriteMask[0] ||
158 (ctx->Stencil._TestTwoSide && ctx->Stencil.WriteMask[back]))
  /external/skia/src/gpu/
GrUserStencilSettings.h 18 * modify these bits. GrOpList will ignore ref, mask, and writemask bits
118 GrUserStencilOp PassOp, GrUserStencilOp FailOp, uint16_t WriteMask> struct Init {};
128 GrUserStencilOp PassOp, GrUserStencilOp FailOp, uint16_t WriteMask>
129 constexpr static Init<Ref, Test, TestMask, PassOp, FailOp, WriteMask> StaticInit() {
130 return Init<Ref, Test, TestMask, PassOp, FailOp, WriteMask>();
149 GrUserStencilOp PassOp, GrUserStencilOp FailOp, uint16_t WriteMask,
152 const Init<Ref, Test, TestMask, PassOp, FailOp, WriteMask>&)
156 Attrs::EffectiveWriteMask(WriteMask)}
160 Attrs::EffectiveWriteMask(WriteMask)} {
244 constexpr static uint16_t EffectiveWriteMask(uint16_t writeMask) {
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  /external/skqp/src/gpu/
GrUserStencilSettings.h 18 * modify these bits. GrOpList will ignore ref, mask, and writemask bits
118 GrUserStencilOp PassOp, GrUserStencilOp FailOp, uint16_t WriteMask> struct Init {};
128 GrUserStencilOp PassOp, GrUserStencilOp FailOp, uint16_t WriteMask>
129 constexpr static Init<Ref, Test, TestMask, PassOp, FailOp, WriteMask> StaticInit() {
130 return Init<Ref, Test, TestMask, PassOp, FailOp, WriteMask>();
149 GrUserStencilOp PassOp, GrUserStencilOp FailOp, uint16_t WriteMask,
152 const Init<Ref, Test, TestMask, PassOp, FailOp, WriteMask>&)
156 Attrs::EffectiveWriteMask(WriteMask)}
160 Attrs::EffectiveWriteMask(WriteMask)} {
244 constexpr static uint16_t EffectiveWriteMask(uint16_t writeMask) {
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  /external/mesa3d/src/gallium/drivers/r300/compiler/tests/
rc_test_helpers.c 251 struct match_info WriteMask;
284 tokens.WriteMask.String = dst_str + matches[3].rm_so;
285 tokens.WriteMask.Length = match_length(matches, 3);
309 /* WriteMask */
310 if (tokens.WriteMask.Length == 0) {
311 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
313 inst->U.I.DstReg.WriteMask = 0;
315 if (tokens.WriteMask.String[0] != '.') {
316 fprintf(stderr, "1st char of writemask is not valid.\n");
319 for (i = 1; i < tokens.WriteMask.Length; i++)
    [all...]
  /external/mesa3d/src/mesa/main/
stencil.c 249 * Updates gl_stencil_attrib::WriteMask. On change flushes the vertices and
264 if (ctx->Stencil.WriteMask[face] == mask)
267 ctx->Stencil.WriteMask[face] = mask;
278 if (ctx->Stencil.WriteMask[0] == mask &&
279 ctx->Stencil.WriteMask[1] == mask)
282 ctx->Stencil.WriteMask[0] = ctx->Stencil.WriteMask[1] = mask;
506 ctx->Stencil.WriteMask[0] = mask;
509 ctx->Stencil.WriteMask[1] = mask;
536 ctx->Stencil.WriteMask[0] != ctx->Stencil.WriteMask[face])
    [all...]
  /device/linaro/bootloader/edk2/UefiCpuPkg/Include/Register/
StmResourceDescriptor.h 119 UINT64 WriteMask;
195 UINT64 WriteMask;
  /external/mesa3d/src/gallium/auxiliary/tgsi/
tgsi_lowering.c 71 dst->Register.WriteMask &= wrmask;
72 assert(dst->Register.WriteMask);
215 if (dst->Register.WriteMask & TGSI_WRITEMASK_Y) {
227 if (dst->Register.WriteMask & TGSI_WRITEMASK_Z) {
238 if (dst->Register.WriteMask & TGSI_WRITEMASK_W) {
249 if (dst->Register.WriteMask & TGSI_WRITEMASK_X) {
284 if (dst->Register.WriteMask & TGSI_WRITEMASK_XYZ) {
308 if (dst->Register.WriteMask & TGSI_WRITEMASK_W) {
351 if (dst->Register.WriteMask & TGSI_WRITEMASK_X) {
362 if (dst->Register.WriteMask & TGSI_WRITEMASK_Y)
    [all...]
tgsi_exec.c 1063 uint writemask = inst->Dst[0].Register.WriteMask; local
1064 if (writemask == TGSI_WRITEMASK_X ||
1065 writemask == TGSI_WRITEMASK_Y ||
1066 writemask == TGSI_WRITEMASK_Z ||
1067 writemask == TGSI_WRITEMASK_W ||
1068 writemask == TGSI_WRITEMASK_NONE) {
    [all...]
tgsi_transform.h 226 unsigned file, unsigned index, unsigned writemask)
230 reg->Register.WriteMask = writemask;
266 inst.Dst[0].Register.WriteMask = dst_writemask;
294 inst.Dst[0].Register.WriteMask = dst_writemask;
326 inst.Dst[0].Register.WriteMask = dst_writemask;
357 inst.Dst[0].Register.WriteMask = dst_writemask;
403 inst.Dst[0].Register.WriteMask = dst_writemask;
459 inst.Dst[0].Register.WriteMask = dst_writemask;
  /external/mesa3d/src/mesa/drivers/dri/nouveau/
nv04_state_raster.c 175 if (ctx->Stencil.WriteMask[0])
184 ctx->Stencil.WriteMask[0] << 24;
  /external/mesa3d/src/mesa/state_tracker/
st_atom_depth.c 111 dsa->depth.writemask = ctx->Depth.Mask;
128 dsa->stencil[0].writemask = ctx->Stencil.WriteMask[0] & 0xff;
139 dsa->stencil[1].writemask = ctx->Stencil.WriteMask[back] & 0xff;

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