1 /** @file 2 * 3 * Copyright (c) 2015, Hisilicon Limited. All rights reserved. 4 * Copyright (c) 2015, Linaro Limited. All rights reserved. 5 * 6 * This program and the accompanying materials 7 * are licensed and made available under the terms and conditions of the BSD License 8 * which accompanies this distribution. The full text of the license may be found at 9 * http://opensource.org/licenses/bsd-license.php 10 * 11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 * 14 **/ 15 16 #ifndef _HW_MEM_INIT_LIB_H_ 17 #define _HW_MEM_INIT_LIB_H_ 18 19 #include <PlatformArch.h> 20 21 #define I2C_CHANNEL 2 22 #define MAX_I2C_DEV 6 23 24 #define SPD_MODULE_PART 18 25 #define SPD_MODULE_PART_DDR4 20 26 27 #define NVRAM_ADDR 0x00D00000 28 29 typedef enum { 30 DDR_FREQ_AUTO = 0, 31 DDR_FREQ_800, 32 DDR_FREQ_1000, 33 DDR_FREQ_1066, 34 DDR_FREQ_1200, 35 DDR_FREQ_1333, 36 DDR_FREQ_1400, 37 DDR_FREQ_1600, 38 DDR_FREQ_1800, 39 DDR_FREQ_1866, 40 DDR_FREQ_2000, 41 DDR_FREQ_2133, 42 DDR_FREQ_2200, 43 DDR_FREQ_2400, 44 DDR_FREQ_2600, 45 DDR_FREQ_2666, 46 DDR_FREQ_2800, 47 DDR_FREQ_2933, 48 DDR_FREQ_3000, 49 DDR_FREQ_3200, 50 DDR_FREQ_MAX 51 } DDR_FREQUENCY_INDEX; 52 53 typedef struct _DDR_FREQ_TCK 54 { 55 UINT32 ddrFreq; 56 UINT32 ddrCk; 57 }DDR_FREQ_TCK; 58 59 typedef struct _GBL_CFG{ 60 61 62 }GBL_CFG; 63 64 typedef struct _GBL_VAR{ 65 66 67 }GBL_VAR; 68 69 typedef struct _GBL_NVDATA{ 70 71 72 }GBL_NVDATA; 73 74 typedef struct _GOBAL { 75 const GBL_CFG Config; // constant input data 76 GBL_VAR Variable; // variable, volatile data 77 GBL_NVDATA NvData; // variable, non-volatile data for S3, warm boot path 78 UINT32 PreBootFailed; 79 }GOBAL, *PGOBAL; 80 81 struct DDR_RANK { 82 BOOLEAN Status; 83 UINT16 RttNom; 84 UINT16 RttPark; 85 UINT16 RttWr; 86 UINT16 MR0; 87 UINT16 MR1; 88 UINT16 MR2; 89 UINT16 MR3; 90 UINT16 MR4; 91 UINT16 MR5; 92 UINT16 MR6[9]; 93 }; 94 95 struct baseMargin { 96 INT16 n; 97 INT16 p; 98 }; 99 100 struct rankMargin { 101 struct baseMargin rank[MAX_CHANNEL][MAX_RANK_CH]; 102 }; 103 104 typedef struct _DDR_DIMM{ 105 BOOLEAN Status; 106 UINT8 mapout; 107 UINT8 DramType; //Byte 2 108 UINT8 ModuleType; //Byte 3 109 UINT8 ExtendModuleType; 110 UINT8 SDRAMCapacity; //Byte 4 111 UINT8 BankNum; 112 UINT8 BGNum; //Byte 4 For DDR4 113 UINT8 RowBits; //Byte 5 114 UINT8 ColBits; //Byte 5 115 UINT8 SpdVdd; //Byte 6 116 UINT8 DramWidth; //Byte 7 117 UINT8 RankNum; //Byte 7 118 UINT8 PrimaryBusWidth; //Byte 8 119 UINT8 ExtensionBusWidth; //Byte 8 120 UINT32 Mtb; 121 UINT32 Ftb; 122 UINT32 minTck; 123 UINT8 MtbDividend; 124 UINT8 MtbDivsor; 125 UINT8 nCL; 126 UINT32 nRCD; 127 UINT32 nRP; 128 UINT8 SPDftb; 129 UINT8 SpdMinTCK; 130 UINT8 SpdMinTCKFtb; 131 UINT8 SpdMaxTCK; 132 UINT8 SpdMinTCL; 133 UINT8 SpdMinTCLFtb; 134 UINT8 SpdMinTWR; 135 UINT8 SpdMinTRCD; 136 UINT8 SpdMinTRCDFtb; 137 UINT8 SpdMinTRRD; 138 UINT8 SpdMinTRRDL; 139 UINT16 SpdMinTRAS; 140 UINT16 SpdMinTRC; 141 UINT16 SpdMinTRCFtb; 142 UINT16 SpdMinTRFC; 143 UINT8 SpdMinTWTR; 144 UINT8 SpdMinTRTP; 145 UINT8 SpdMinTAA; 146 UINT8 SpdMinTAAFtb; 147 UINT8 SpdMinTFAW; 148 UINT8 SpdMinTRP; 149 UINT8 SpdMinTRPFtb; 150 UINT8 SpdMinTCCDL; 151 UINT8 SpdMinTCCDLFtb; 152 UINT8 SpdAddrMap; 153 UINT8 SpdModuleAttr; 154 155 UINT8 SpdModPart[SPD_MODULE_PART]; // Module Part Number 156 UINT8 SpdModPartDDR4[SPD_MODULE_PART_DDR4]; // Module Part Number DDR4 157 UINT16 SpdMMfgId; // Module Mfg Id from SPD 158 UINT16 SpdRMId; // Register Manufacturer Id 159 UINT16 SpdMMDate; // Module Manufacturing Date 160 UINT32 SpdSerialNum; 161 UINT16 DimmSize; 162 UINT16 DimmSpeed; 163 UINT32 RankSize; 164 UINT8 SpdMirror; //Denote the dram address mapping is standard mode or mirrored mode 165 struct DDR_RANK Rank[MAX_RANK_DIMM]; 166 }DDR_DIMM; 167 168 typedef struct { 169 UINT32 ddrcTiming0; 170 UINT32 ddrcTiming1; 171 UINT32 ddrcTiming2; 172 UINT32 ddrcTiming3; 173 UINT32 ddrcTiming4; 174 UINT32 ddrcTiming5; 175 UINT32 ddrcTiming6; 176 UINT32 ddrcTiming7; 177 UINT32 ddrcTiming8; 178 }DDRC_TIMING; 179 180 typedef struct _MARGIN_RESULT{ 181 UINT32 OptimalDramVref[12]; 182 UINT32 optimalPhyVref[18]; 183 }MARGIN_RESULT; 184 185 typedef struct _DDR_Channel{ 186 BOOLEAN Status; 187 UINT8 CurrentDimmNum; 188 UINT8 CurrentRankNum; 189 UINT16 RankPresent; 190 UINT8 DramType; 191 UINT8 DramWidth; 192 UINT8 ModuleType; 193 UINT32 MemSize; 194 UINT32 tck; 195 UINT32 ratio; 196 UINT32 CLSupport; 197 UINT32 minTck; 198 UINT32 taref; 199 UINT32 nAA; 200 UINT32 nAOND; 201 UINT32 nCKE; 202 UINT32 nCL; 203 UINT32 nCCDL; 204 UINT32 nCKSRX; 205 UINT32 nCKSRE; 206 UINT32 nCCDNSW; 207 UINT32 nCCDNSR; 208 UINT32 nFAW; 209 UINT32 nMRD; 210 UINT32 nMOD; 211 UINT32 nRCD; 212 UINT32 nRRD; 213 UINT32 nRRDL; 214 UINT32 nRAS; 215 UINT32 nRC; 216 UINT32 nRFC; 217 UINT32 nRFCAB; 218 UINT32 nRTP; 219 UINT32 nRTW; 220 UINT32 nRP; 221 UINT32 nSRE; 222 UINT32 nWL; 223 UINT32 nWR; 224 UINT32 nWTR; 225 UINT32 nWTRL; 226 UINT32 nXARD; 227 UINT32 nZQPRD; 228 UINT32 nZQINIT; 229 UINT32 nZQCS; 230 UINT8 cwl; //tWL? 231 UINT8 pl; //parity latency 232 UINT8 wr_pre_2t_en; 233 UINT8 rd_pre_2t_en; 234 UINT8 cmd_2t_en; 235 UINT8 parity_en; 236 UINT8 wr_dbi_en; 237 UINT8 wr_dm_en; 238 UINT8 ddr4_crc_en; 239 UINT16 emrs0; 240 UINT16 emrs1; 241 UINT16 emrs1Wr; 242 UINT16 emrs2; 243 UINT16 emrs3; 244 UINT16 emrs4; 245 UINT16 emrs5; 246 UINT16 emrs5Wr; 247 UINT16 emrs6; 248 UINT16 emrs7; 249 UINT8 phy_rddata_set; 250 UINT8 phyif_tim_rdcs; 251 UINT8 phyif_tim_rden; 252 UINT8 phyif_tim_wden; 253 UINT8 phyif_tim_wdda; 254 UINT8 phyif_tim_wdcs; 255 UINT8 per_cs_training_en; 256 UINT32 phyRdDataEnIeDly; 257 UINT32 phyPadCalConfig; 258 UINT32 phyDqsFallRiseDelay; 259 UINT32 ddrcCfgDfiLat0; 260 UINT32 ddrcCfgDfiLat1; 261 UINT32 parityLatency; 262 UINT32 dimm_parity_en; 263 DDRC_TIMING ddrcTiming; 264 DDR_DIMM Dimm[MAX_DIMM]; 265 MARGIN_RESULT sMargin; 266 }DDR_CHANNEL; 267 268 typedef struct _NVRAM_RANK{ 269 UINT16 MR0; 270 UINT16 MR1; 271 UINT16 MR2; 272 UINT16 MR3; 273 UINT16 MR4; 274 UINT16 MR5; 275 UINT16 MR6[9]; 276 }NVRAM_RANK; 277 278 typedef struct _NVRAM_DIMM{ 279 NVRAM_RANK Rank[MAX_RANK_DIMM]; 280 }NVRAM_DIMM; 281 282 283 typedef struct _NVRAM_CHANNEL{ 284 NVRAM_DIMM Dimm[MAX_DIMM]; 285 UINT32 DDRC_CFG_ECC; 286 UINT32 DDRC_CFG_WORKMODE; 287 UINT32 DDRC_CFG_WORKMODE1; 288 UINT32 DDRC_CFG_WORKMODE2; 289 UINT32 DDRC_CFG_DDRMODE; 290 UINT32 DDRC_CFG_DIMM; 291 UINT32 DDRC_CFG_RNKVOL_0; 292 UINT32 DDRC_CFG_RNKVOL_1; 293 UINT32 DDRC_CFG_RNKVOL_2; 294 UINT32 DDRC_CFG_RNKVOL_3; 295 UINT32 DDRC_CFG_RNKVOL_4; 296 UINT32 DDRC_CFG_RNKVOL_5; 297 UINT32 DDRC_CFG_RNKVOL_6; 298 UINT32 DDRC_CFG_RNKVOL_7; 299 UINT32 DDRC_CFG_RNKVOL_8; 300 UINT32 DDRC_CFG_RNKVOL_9; 301 UINT32 DDRC_CFG_RNKVOL_10; 302 UINT32 DDRC_CFG_RNKVOL_11; 303 UINT32 DDRC_CFG_ODT_0; 304 UINT32 DDRC_CFG_ODT_1; 305 UINT32 DDRC_CFG_ODT_2; 306 UINT32 DDRC_CFG_ODT_3; 307 UINT32 DDRC_CFG_ODT_4; 308 UINT32 DDRC_CFG_ODT_5; 309 UINT32 DDRC_CFG_ODT_6; 310 UINT32 DDRC_CFG_ODT_7; 311 UINT32 DDRC_CFG_ODT_8; 312 UINT32 DDRC_CFG_ODT_9; 313 UINT32 DDRC_CFG_ODT_10; 314 UINT32 DDRC_CFG_ODT_11; 315 UINT32 DDRC_CFG_TIMING0; 316 UINT32 DDRC_CFG_TIMING1; 317 UINT32 DDRC_CFG_TIMING2; 318 UINT32 DDRC_CFG_TIMING3; 319 UINT32 DDRC_CFG_TIMING4; 320 UINT32 DDRC_CFG_TIMING5; 321 UINT32 DDRC_CFG_TIMING6; 322 UINT32 DDRC_CFG_TIMING7; 323 UINT32 DDRC_CFG_DFI_LAT0; 324 UINT32 DDRC_CFG_DFI_LAT1; 325 UINT32 DDRC_CFG_DDRPHY; 326 UINT32 Config[24]; 327 BOOLEAN Status; 328 }NVRAM_CHANNEL; 329 330 typedef struct _NVRAM{ 331 UINT32 NvramCrc; 332 NVRAM_CHANNEL Channel[MAX_SOCKET][MAX_CHANNEL]; 333 UINT32 DdrFreqIdx; 334 335 }NVRAM; 336 337 typedef struct _MEMORY{ 338 UINT8 Config0; 339 UINT8 marginTest; 340 UINT8 Config1[5]; 341 UINT8 ErrorBypass; //register of spd mirror mode 342 UINT32 Config2; 343 }MEMORY; 344 345 typedef struct _NUMAINFO{ 346 UINT8 NodeId; 347 UINT64 Base; 348 UINT64 Length; 349 UINT32 ScclInterleaveEn; 350 }NUMAINFO; 351 352 353 typedef struct _GBL_DATA 354 { 355 DDR_CHANNEL Channel[MAX_SOCKET][MAX_CHANNEL]; 356 UINT8 DramType; 357 UINT8 CurrentDimmNum; 358 UINT8 CurrentRankNum; 359 UINT8 MaxSPCNum; 360 UINT32 Freq; 361 UINT32 SpdTckMtb; 362 UINT32 SpdTckFtb; 363 UINT32 SpdTck; 364 UINT32 Tck; 365 UINT32 DdrFreqIdx; 366 UINT32 DevParaFreqIdx; //Maximum frequency of DDR device 367 UINT32 MemSize; 368 UINT32 EccEn; 369 370 BOOLEAN SetupExist; 371 UINT8 warmReset; 372 UINT8 needColdReset; 373 374 UINT8 cl; 375 UINT8 cwl; 376 UINT8 pl; 377 UINT8 wr_pre_2t_en; 378 UINT8 rd_pre_2t_en; 379 UINT8 cmd_2t_en; 380 UINT8 ddr4_parity_en; 381 UINT8 wr_dbi_en; 382 UINT8 wr_dm_en; 383 UINT8 ddr4_crc_en; 384 UINT16 emrs0; 385 UINT16 emrs1; 386 UINT16 emrs2; 387 UINT16 emrs3; 388 UINT16 emrs4; 389 UINT16 emrs5; 390 UINT16 emrs6; 391 UINT16 emrs7; 392 UINT8 phy_rddata_set; 393 UINT8 phyif_tim_rdcs; 394 UINT8 phyif_tim_rden; 395 UINT8 phyif_tim_wden; 396 UINT8 phyif_tim_wdda; 397 UINT8 phyif_tim_wdcs; 398 UINT8 dimm_trtr; 399 UINT8 dimm_twtw; 400 UINT8 rnk_trtr; 401 UINT8 rnk_twtw; 402 UINT8 rnk_trtw; 403 UINT8 rnk_twtr; 404 UINT8 per_cs_training_en; 405 UINT8 scale; 406 UINT8 ddrFreq; 407 UINT8 debugNeed; 408 UINT8 ddr3OdtEnable; 409 double fprd; 410 BOOLEAN chipIsEc; 411 NVRAM nvram; 412 MEMORY mem; 413 NUMAINFO NumaInfo[MAX_SOCKET][MAX_NUM_PER_TYPE]; 414 415 }GBL_DATA, *pGBL_DATA; 416 417 typedef union { 418 struct { 419 UINT16 freqIndex:4; //Frequency Index; 420 UINT16 slot0:4; //Channel slot0 for DIMM 421 UINT16 slot1:4; //Channel slot1 for DIMM 422 UINT16 slot2:4; //Channel slot2 for DIMM 423 }Bits; 424 UINT16 Data; 425 }ODT_VALUE_INDEX; 426 427 typedef union { 428 struct { 429 UINT8 RTTNom:3; 430 UINT8 reserved_3:1; 431 UINT8 RTTWr:2; 432 UINT8 reserved_6:2; 433 }Bits; 434 UINT8 Data; 435 }ODT_RTT_VALUE_DDR3; 436 437 typedef union { 438 struct { 439 UINT8 RTTNom:3; 440 UINT8 RTTPark:3; 441 UINT8 RTTWr:2; 442 }Bits; 443 UINT8 Data; 444 }ODT_RTT_VALUE_DDR4; 445 446 typedef union { 447 struct { 448 UINT16 tarDimm:2; // target DIMM 449 UINT16 tarRank:2; // target Rank 450 UINT16 slot0:4; // Channel slot0 for DIMM 451 UINT16 slot1:4; // Channel slot1 for DIMM 452 UINT16 slot2:4; // Channel slot2 for DIMM 453 }Bits; 454 UINT16 Data; 455 }ODT_ACTIVE_INDEX; 456 457 struct ODT_VALUE_STRUCT_DDR3 { 458 UINT16 config; // ODT_VALUE_INDEX 459 UINT8 dramOdt[MAX_DIMM][MAX_RANK_DIMM]; // ODT_VALUE_RTT_DDR3 460 }; 461 462 struct ODT_VALUE_STRUCT_DDR4 { 463 UINT16 config; 464 UINT8 dramOdt[MAX_DIMM][MAX_RANK_DIMM]; 465 }; 466 467 struct ODT_ACTIVE_STRUCT { 468 UINT16 config; // ODT config index 469 UINT16 actBits[2]; // WR :Bits[3;0] = D0_R[3:0] Bits[7:4] = D1_R[3:0] Bits[11:8] = D2_R[3:0] 470 }; 471 472 // JEDEC manufacturer IDs from JEP-106 473 #define MFGID_AENEON 0x5705 474 #define MFGID_QIMONDA 0x5105 475 #define MFGID_NEC 0x1000 476 #define MFGID_IDT 0xB300 477 #define MFGID_TI 0x9700 478 #define MFGID_HYNIX 0xAD00 479 #define MFGID_MICRON 0x2C00 480 #define MFGID_INFINEON 0xC100 481 #define MFGID_SAMSUNG 0xCE00 482 #define MFGID_TEK 0x3D00 483 #define MFGID_KINGSTON 0x9801 484 #define MFGID_ELPIDA 0xFE02 485 #define MFGID_SMART 0x9401 486 #define MFGID_AGILENT 0xC802 487 #define MFGID_NANYA 0x0B03 488 #define MFGID_INPHI 0xB304 489 #define MFGID_MONTAGE 0x3206 490 #define MFGID_RAMAXEL 0x4304 491 492 // 493 // DDR3 frequencies 800 - 2667 494 // DDR4 frequencies 1333 - 3200 495 // 496 #define DDR_800 0 // tCK(ns)=2.5 497 #define DDR_1000 1 // tCK(ns)=2.0 498 #define DDR_1066 2 // tCK(ns)=1.875 499 #define DDR_1200 3 // tCK(ns)=1.667 500 #define DDR_1333 4 // tCK(ns)=1.5 501 #define DDR_1400 5 // tCK(ns)=1.429 502 #define DDR_1600 6 // tCK(ns)=1.25 503 #define DDR_1800 7 // tCK(ns)=1.11 504 #define DDR_1866 8 // tCK(ns)=1.07 505 #define DDR_2000 9 // tCK(ns)=1.0 506 #define DDR_2133 10 // tCK(ns)=0.9375 507 #define DDR_2200 11 // tCK(ns)=0.909 508 #define DDR_2400 12 // tCK(ns)=0.833 509 #define DDR_2600 13 // tCK(ns)=0.769 510 #define DDR_2666 14 // tCK(ns)=0.750 511 #define DDR_2800 15 // tCK(ns)=0.714 512 #define DDR_2933 16 // tCK(ns)=0.682 513 #define DDR_3000 17 // tCK(ns)=0.667 514 #define DDR_3200 18 // tCK(ns)=0.625 515 #define DDR_MAX (DDR_3200) 516 517 #define FREQUENCY_MTB_OFFSET 1000000 518 #define FREQUENCY_FTB_OFFSET 1000 519 520 // 521 #define DDR_800_TCK_MIN 25000 522 #define DDR_1000_TCK_MIN 20000 523 #define DDR_1067_TCK_MIN 18750 524 #define DDR_1200_TCK_MIN 16670 525 #define DDR_1333_TCK_MIN 15000 526 #define DDR_1400_TCK_MIN 14290 527 #define DDR_1600_TCK_MIN 12500 528 #define DDR_1800_TCK_MIN 11100 529 #define DDR_1867_TCK_MIN 10710 530 #define DDR_2000_TCK_MIN 10000 531 #define DDR_2133_TCK_MIN 9380 532 #define DDR_2200_TCK_MIN 9090 533 #define DDR_2400_TCK_MIN 8330 534 #define DDR_2600_TCK_MIN 7690 535 #define DDR_2667_TCK_MIN 7500 536 #define DDR_2800_TCK_MIN 7140 537 #define DDR_2933_TCK_MIN 6820 538 #define DDR_3000_TCK_MIN 6670 539 #define DDR_3200_TCK_MIN 6250 540 541 542 // 543 // Serial Presence Detect bytes (JEDEC revision 1.0) 544 // 545 #define SPD_SIZE 0 // Bytes used, Device size, CRC coverage 546 #define SPD_REVISION 1 // SPD Encoding Revision 547 #define SPD_KEY_BYTE 2 // DRAM Device Type 548 #define SPD_TYPE_DDR3 0x0B // DDR3 SDRAM 549 #define SPD_TYPE_DDR4 0x0C // DDR4 SDRAM 550 #define SPD_KEY_BYTE2 3 // Module Type and Thickness (RDIMM or UDIMM) 551 #define SPD_RDIMM 1 // Module type is RDIMM 552 #define SPD_UDIMM 2 // Module type is UDIMM 553 #define SPD_SODIMM 3 // Module type is SODIMM 554 #define SPD_MICRO_DIMM 4 // Module type is Micro-DIMM 555 #define SPD_LRDIMM_DDR4 4 // Module type is LRDIMM (DDR4) 556 #define SPD_MINI_RDIMM 5 // Module type is Mini-RDIMM 557 #define SPD_MINI_UDIMM 6 // Module type is Mini-UDIMM 558 #define SPD_MINI_CDIMM 7 // Module type is Mini-CDIMM 559 #define SPD_ECC_SO_UDIMM 9 // Module type is 72b-SO-UDIMM 560 #define SPD_ECC_SO_RDIMM 8 // Module type is 72b-SO-RDIMM 561 #define SPD_ECC_SO_CDIMM 10 // Module type is 72b-SO-CDIMM 562 #define SPD_LRDIMM 11 // Module type is LRDIMM 563 #define SPD_UDIMM_ECC 18 // Module type is UDIMM-ECC 564 #define SPD_SDRAM_BANKS 4 // SDRAM Density and number of internal banks 565 #define SPD_1Gb 2 // Total SDRAM Capacity 1 Gigabits 566 #define SPD_2Gb 3 // Total SDRAM Capacity 2 Gigabits 567 #define SPD_4Gb 4 // Total SDRAM Capacity 4 Gigabits 568 #define SPD_8Gb 5 // Total SDRAM Capacity 8 Gigabits 569 #define SPD_16Gb 6 // Total SDRAM Capacity 16 Gigabits 570 #define SPD_32Gb 7 // Total SDRAM Capacity 32 Gigabits 571 #define SPD_SDRAM_ADDR 5 // Number of Row and Column address bits 572 #define SPD_ROW_12 0 // 12 row bits 573 #define SPD_ROW_13 1 // 13 row bits 574 #define SPD_ROW_14 2 // 14 row bits 575 #define SPD_ROW_15 3 // 15 row bits 576 #define SPD_ROW_16 4 // 16 row bits 577 #define SPD_ROW_17 5 // 17 row bits 578 #define SPD_ROW_18 6 // 18 row bits 579 #define SPD_COL_9 0 // 9 colum bits 580 #define SPD_COL_10 1 // 10 colum bits 581 #define SPD_COL_11 2 // 11 colum bits 582 #define SPD_COL_12 3 // 12 colum bits 583 #define SPD_VDD_SUPPORT 6 // Vdd DIMM supports 584 #define SPD_VDD_150 0 // Module Supports 1.50V 585 #define SPD_VDD_135 BIT1 // Module Supports 1.35V 586 #define SPD_VDD_125 BIT2 // Module Supports 1.25V 587 #define SPD_MODULE_ORG_DDR3 7 // Number of Ranks and SDRAM device width 588 #define SPD_MODULE_ORG_DDR4 12 // DDR4 Module Organization 589 #define DEVICE_WIDTH_X4 0 // SDRAM device width = 4 bits 590 #define DEVICE_WIDTH_X8 1 // SDRAM device width = 8 bits 591 #define DEVICE_WIDTH_X16 2 // SDRAM device width = 16 bits 592 #define SPD_NUM_RANKS_1 0 593 #define SPD_NUM_RANKS_2 1 594 #define SPD_NUM_RANKS_4 3 595 #define SPD_NUM_RANKS_8 4 596 #define SPD_MEM_BUS_WID 8 // Width of SDRAM memory bus 597 #define SPD_FTB 9 // Timebase for fine grain timing calculations 598 #define SPD_MTB_DIVEND 10 // Medium Time Base Dividend 599 #define SPD_MTB_DIVISOR 11 // Medium Time Base Divisor 600 #define SPD_MIN_TCK 12 // Minimum cycle time (at max CL) 601 #define SPD_TCKMIN_800 20 // tCK(MTB)=20, tCK(ns)=2.5 602 #define SPD_TCKMIN_1067 15 // tCK(MTB)=15, tCK(ns)=1.875 603 #define SPD_TCKMIN_1333 12 // tCK(MTB)=12, tCK(ns)=1.5 604 #define SPD_TCKMIN_1600 10 // tCK(MTB)=10, tCK(ns)=1.25 605 #define SPD_TCKMIN_1867 9 // tCK(MTB)=9, tCK(ns)=1.07 606 #define SPD_TCKMIN_2133 8 // tCK(MTB)=8, tCK(ns)=0.9375 607 #define SPD_TCKMIN_2400 7 // tCK(MTB)=7, tCK(ns)=.833 608 #define SPD_CAS_LT_SUP_LSB 14 // CAS Latencies Supported, Least Significant Byte 609 #define SPD_CAS_LT_SUP_MSB 15 // CAS Latencies Supported, Most Significant Byte 610 #define SPD_MIN_TAA 16 // Minimum CAS Latency Time (tAAmin) 611 #define SPD_MIN_TWR 17 // Minimum Write Recovery Time 612 #define SPD_MIN_TRCD 18 // Minimum RAS to CAS delay 613 #define SPD_MIN_TRRD 19 // Minimum Row active to row active delay 614 #define SPD_MIN_TRP 20 // Minimum Row Precharge time 615 #define SPD_EXT_TRC_TRAS 21 // Upper nibbles for min tRAS and tRC 616 #define SPD_MIN_TRAS 22 // Minimum Active to Precharge time 617 #define SPD_MIN_TRC 23 // Minimum Active to Active/Refresh time 618 #define SPD_MIN_TRFC_LSB 24 // Minimum Refresh Recovery time least-significant byte 619 #define SPD_MIN_TRFC_MSB 25 // Minimum Refresh Recovery time most-significant byte 620 #define SPD_MIN_TWTR 26 // Minimum Internal Write to Read command delay 621 #define SPD_MIN_TRTP 27 // Minimum Internal Read to Precharge command delay 622 #define SPD_UN_TFAW 28 // Upper Nibble for tFAW 623 #define SPD_MIN_TFAW 29 // Minimum Four Activate Window Delay Time (tFAWmin) 624 #define SPD_OD_SUP 30 // SDRAM Output Drivers Supported 625 #define SPD_RFSH_OPT 31 // SDRAM Refresh Options 626 #define ETR BIT0 // Bit location for Extended Temp Range 627 #define ETRR BIT1 // Bit location for Extended Temp Refresh Rate 628 #define ASR BIT2 // Bit location for Automatic Self Refresh 629 #define ODTS BIT3 // Bit location for On-die Thermal Sensor 630 #define SPD_DIMM_TS 32 // Module Temperature Sensor 631 #define SPD_SDRAM_TYPE 33 // SDRAM device type 632 #define SPD_FTB_TCK 34 // Fine Offset for SDRAM tCK 633 #define SPD_FTB_TAA 35 // Fine Offset for SDRAM tAA 634 #define SPD_FTB_TRCD 36 // Fine Offset for SDRAM tRCD 635 #define SPD_FTB_TRP 37 // Fine Offset for SDRAM tRP 636 #define SPD_FTB_TRC 38 // Fine Offset for SDRAM tRC 637 #define SPD_OPT_FEAT 41 // SDRAM Optional Features 638 #define SPD_PTRR BIT7 // Indicates if the DIMM is pTRR compliant 639 640 // UDIMM specific bytes 641 // Applicable when Module Type (key byte 3) = 2, 3, 4, 6, or 8 642 643 #define SPD_ADDR_MAP_FECTD 63 // Address Mapping from Edge Connector to DRAM 644 645 // RDIMM specific bytes 646 // Applicable when Module Type (key byte 3) = 1, 5, or 9 647 648 #define SPD_RDIMM_ATTR 63 // RDIMM module attributes 649 #define SPD_DIMM_HS 64 // Module Heat Spreader Solution 650 #define SPD_REG_VEN_LSB 65 // Register Vendor ID LSB 651 #define SPD_REG_VEN_MSB 66 // Register Vendor ID MSB 652 #define SPD_REG_REV 67 // Register Revision 653 #define SPD_CNTL_0 69 // Register Control Word 0 & 1 654 #define SPD_CNTL_1 70 // Register Control Word 2 & 3 655 #define SPD_CNTL_2 71 // Register Control Word 4 & 5 656 #define SPD_CNTL_3 72 // Register Control Word 6 & 7 (reserved) 657 #define SPD_CNTL_4 73 // Register Control Word 8 & 9 (reserved) 658 #define SPD_CNTL_5 74 // Register Control Word 10 & 11 (reserved) 659 #define SPD_CNTL_6 75 // Register Control Word 12 & 13 (reserved) 660 #define SPD_CNTL_7 76 // Register Control Word 14 & 15 (reserved) 661 662 // LRDIMM specific bytes 663 // Applicable when Module Type (key byte 3) = 0xB 664 // Based on DDR3 SPD 1.0 Document Release 2.1 draft, dated May 27, 2011 665 666 #define SPD_LRDIMM_ATTR 63 // LRDIMM module attributes 667 #define SPD_LRBUF_REV 64 // LR Buffer Revision 668 #define SPD_LRBUF_VEN_LSB 65 // LR Buffer Vendor ID LSB 669 #define SPD_LRBUF_VEN_MSB 66 // LR Buffer Vendor ID MSB 670 #define SPD_LR_F0_RC2_3 67 // LR Buffer Function 0, Control Word 2 & 3 671 #define SPD_LR_F0_RC4_5 68 // LR Buffer Function 0, Control Word 4 & 5 672 #define SPD_LR_F1_RC8_11 69 // LR Buffer Function 1, Control Word 8 & 11 673 #define SPD_LR_F1_RC12_13 70 // LR Buffer Function 1, Control Word 12 & 13 674 #define SPD_LR_F1_RC14_15 71 // LR Buffer Function 1, Control Word 14 & 15 675 676 // Speed bin 0 = 800 & 1066 677 #define SPD_LR_SB0_MDQ_DS_ODT 72 // LR Buffer Function 3, Control Word 8 & 9 678 #define SPD_LR_SB0_DR01_QODT_ACT 73 // LR Buffer Function 3 & 4, Control Word 10 & 11 679 #define SPD_LR_SB0_DR23_QODT_ACT 74 // LR Buffer Function 5 & 6, Control Word 10 & 11 680 #define SPD_LR_SB0_DR45_QODT_ACT 75 // LR Buffer Function 7 & 8, Control Word 10 & 11 681 #define SPD_LR_SB0_DR67_QODT_ACT 76 // LR Buffer Function 9 & 10, Control Word 10 & 11 682 #define SPD_LR_SB0_MR1_2_RTT 77 // LR Buffer SMBus offsets 0xC0 - 0xC7 683 684 // Speed bin 1 = 1333 & 1600 685 #define SPD_LR_SB1_MDQ_DS_ODT 78 // LR Buffer Function 3, Control Word 8 & 9 686 #define SPD_LR_SB1_DR01_QODT_ACT 79 // LR Buffer Function 3 & 4, Control Word 10 & 11 687 #define SPD_LR_SB1_DR23_QODT_ACT 80 // LR Buffer Function 5 & 6, Control Word 10 & 11 688 #define SPD_LR_SB1_DR45_QODT_ACT 81 // LR Buffer Function 7 & 8, Control Word 10 & 11 689 #define SPD_LR_SB1_DR67_QODT_ACT 82 // LR Buffer Function 9 & 10, Control Word 10 & 11 690 #define SPD_LR_SB1_MR1_2_RTT 83 // LR Buffer SMBus offsets 0xC0 - 0xC7 691 692 // Speed bin 2 = 1866 & 2133 693 #define SPD_LR_SB2_MDQ_DS_ODT 84 // LR Buffer Function 3, Control Word 8 & 9 694 #define SPD_LR_SB2_DR01_QODT_ACT 85 // LR Buffer Function 3 & 4, Control Word 10 & 11 695 #define SPD_LR_SB2_DR23_QODT_ACT 86 // LR Buffer Function 5 & 6, Control Word 10 & 11 696 #define SPD_LR_SB2_DR45_QODT_ACT 87 // LR Buffer Function 7 & 8, Control Word 10 & 11 697 #define SPD_LR_SB2_DR67_QODT_ACT 88 // LR Buffer Function 9 & 10, Control Word 10 & 11 698 #define SPD_LR_SB2_MR1_2_RTT 89 // LR Buffer SMBus offsets 0xC0 - 0xC7 699 700 #define SPD_LR_150_MIN_MOD_DELAY 90 // LR DIMM minimum DQ Read propagation delay at 1.5V 701 #define SPD_LR_150_MAX_MOD_DELAY 91 // LR DIMM maximum DQ Read propagation delay at 1.5V 702 #define SPD_LR_135_MIN_MOD_DELAY 92 // LR DIMM minimum DQ Read propagation delay at 1.35V 703 #define SPD_LR_135_MAX_MOD_DELAY 93 // LR DIMM maximum DQ Read propagation delay at 1.35V 704 #define SPD_LR_12x_MIN_MOD_DELAY 94 // LR DIMM minimum DQ Read propagation delay at 1.2xV 705 #define SPD_LR_12x_MAX_MOD_DELAY 95 // LR DIMM maximum DQ Read propagation delay at 1.2xV 706 707 #define SPD_LR_PERS_BYTE_0 102 // LR DIMM Personality Byte 708 #define SPD_LR_PERS_BYTE_1 103 // LR DIMM Personality Byte 709 #define SPD_LR_PERS_BYTE_2 104 // LR DIMM Personality Byte 710 #define SPD_LR_PERS_BYTE_3 105 // LR DIMM Personality Byte 711 #define SPD_LR_PERS_BYTE_4 106 // LR DIMM Personality Byte 712 #define SPD_LR_PERS_BYTE_5 107 // LR DIMM Personality Byte 713 #define SPD_LR_PERS_BYTE_6 108 // LR DIMM Personality Byte 714 #define SPD_LR_PERS_BYTE_7 109 // LR DIMM Personality Byte 715 #define SPD_LR_PERS_BYTE_8 110 // LR DIMM Personality Byte 716 #define SPD_LR_PERS_BYTE_9 111 // LR DIMM Personality Byte 717 #define SPD_LR_PERS_BYTE_10 112 // LR DIMM Personality Byte 718 #define SPD_LR_PERS_BYTE_11 113 // LR DIMM Personality Byte 719 #define SPD_LR_PERS_BYTE_12 114 // LR DIMM Personality Byte 720 #define SPD_LR_PERS_BYTE_13 115 // LR DIMM Personality Byte 721 #define SPD_LR_PERS_BYTE_14 116 // LR DIMM Personality Byte 722 #define SPD_LR_PERS_BYTES_TOTAL 15 // LR DIMM Total number of Personality Bytes 723 724 // End module specific section 725 726 #define SPD_MMID_LSB 117 // Module Manufacturer ID Code, Least Significant Byte 727 #define SPD_MMID_MSB 118 // Module Manufacturer ID Code, Mostst Significant Byte 728 #define SPD_MM_LOC 119 // Module Manufacturing Location 729 #define SPD_MM_DATE 120 // Module Manufacturing Date 120-121 730 #define SPD_MODULE_SN 122 // Module Serial Number 122-125 731 #define SPD_CRC_LSB 126 // LSB of 16-bit CRC 732 #define SPD_CRC_MSB 127 // MSB of 16-bit CRC 733 734 #define SPD_MODULE_PN 128 // Module Part Number 128-145 735 #define SPD_MODULE_RC 146 // Module Revision Code 146-147 736 #define SPD_DRAM_MIDC_LSB 148 // DRAM Manufacturer ID Code, Least Significant Byte 737 #define SPD_DRAM_MIDC_MSB 149 // DRAM Manufacturer ID Code, Most Significant Byte 738 #ifdef MEM_NVDIMM_EN 739 #define SPD_NVDIMM_ID_N 174 // If NVDIMM value will be 'N' 740 #define SPD_NVDIMM_ID_V 175 // If NVDIMM value will be 'V' 741 #endif //MEM_NVDIMM_EN 742 #define SPD_BYTE_200 200 // Fixed value 0xBE 743 744 // 745 // DDR4 Specific Bytes 746 // 747 #define SPD_SDRAM_TYPE_DDR4 6 // SDRAM Device Type (DDR4) 748 #define SPD_OPT_FEAT_DDR4 7 // SDRAM Optional Features (DDR4) 749 #define SPD_MAC_MASK BIT0 | BIT1 | BIT2 // Mask for Maximum Active Count field 750 #define SPD_TRR_IMMUNE BIT3 // Indicates this DIMM does not require DRAM Maintenance 751 #define SPD_RFSH_OPT_DDR4 8 // SDRAM Refresh Options (DDR4) 752 #define SPD_VDD_DDR4 11 // Vdd DIMM supports (DDR4) 753 #define SPD_VDD_120 3 // Module operable and endurant 1.20V 754 #define SPD_MODULE_ORG_DDR4 12 // Number of Ranks and SDRAM device width (DDR4) 755 #define SPD_MEM_BUS_WID_DDR4 13 // Width of SDRAM memory bus 756 #define SPD_DIMM_TS_DDR4 14 // Module Thermal Sensor 757 #define SPD_TB_DDR4 17 // Timebase [3:2] MTB, [1:0] FTB 758 #define SPD_MIN_TCK_DDR4 18 // Minimum cycle time 759 #define SPD_TCKMIN_DDR4_1600 10 // tCK(MTB)=10, tCK(ns)=1.25 760 #define SPD_TCKMIN_DDR4_1866 9 // tCK(MTB)=9, tCK(ns)=1.071 761 #define SPD_TCKMIN_DDR4_2133 8 // tCK(MTB)=8, tCK(ns)=.938 762 #define SPD_TCKMIN_DDR4_2400 7 // tCK(MTB)=7, tCK(ns)=.833 763 #define SPD_MAX_TCK_DDR4 19 // Maximum cycle time 764 #define SPD_CAS_LT_SUP_1_DDR4 20 // CAS Latencies Supported, first byte 765 #define SPD_CAS_LT_SUP_2_DDR4 21 // CAS Latencies Supported, second byte 766 #define SPD_CAS_LT_SUP_3_DDR4 22 // CAS Latencies Supported, third byte 767 #define SPD_CAS_LT_SUP_4_DDR4 23 // CAS Latencies Supported, fourth byte 768 #define SPD_MIN_TAA_DDR4 24 // Minimum CAS Latency Time (tAAmin) 769 #define SPD_MIN_TRCD_DDR4 25 // Minimum RAS to CAS delay 770 #define SPD_MIN_TRP_DDR4 26 // Minimum Row Precharge time 771 #define SPD_EXT_TRC_TRAS_DDR4 27 // Upper nibbles for min tRAS and tRC 772 #define SPD_MIN_TRAS_DDR4 28 // Minimum Active to Precharge time 773 #define SPD_MIN_TRC_DDR4 29 // Minimum Active to Active/Refresh time 774 #define SPD_MIN_TRFC1_LSB_DDR4 30 // Minimum Refresh Recovery time least-significant byte 775 #define SPD_MIN_TRFC1_MSB_DDR4 31 // Minimum Refresh Recovery time most-significant byte 776 #define SPD_MIN_TRFC2_LSB_DDR4 32 // Minimum Refresh Recovery time least-significant byte 777 #define SPD_MIN_TRFC2_MSB_DDR4 33 // Minimum Refresh Recovery time most-significant byte 778 #define SPD_MIN_TRFC3_LSB_DDR4 34 // Minimum Refresh Recovery time least-significant byte 779 #define SPD_MIN_TRFC3_MSB_DDR4 35 // Minimum Refresh Recovery time most-significant byte 780 #define SPD_TFAW_UPPER_DDR4 36 // Upper nibble for tFAW 781 #define SPD_MIN_TFAW_DDR4 37 // Minimum For Active Window Delay Time (tFAW) 782 #define SPD_MIN_TRRDS_DDR4 38 // Minimum Active to Active Delay Time tRRD_S Different Bank Group 783 #define SPD_MIN_TRRDL_DDR4 39 // Minimum Active to Active Delay Time tRRD_L Same Bank Group 784 #define SPD_MIN_TCCDL_DDR4 40 // Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group 785 #define SPD_FTB_TCCDL_DDR4 117 // Fine offset for tCCD_L 786 #define SPD_FTB_TRRDL_DDR4 118 // Fine offset for tRRD_L 787 #define SPD_FTB_TRRDS_DDR4 119 // Fine offset for tRRD_S 788 #define SPD_FTB_TRC_DDR4 120 // Fine offset for TRC 789 #define SPD_FTB_TRP_DDR4 121 // Fine offset for TRP 790 #define SPD_FTB_TRCD_DDR4 122 // Fine offset for TRCD 791 #define SPD_FTB_TAA_DDR4 123 // Fine offset for TAA 792 #define SPD_FTB_MAX_TCK_DDR4 124 // Fine offset for max TCK 793 #define SPD_FTB_MIN_TCK_DDR4 125 // Fine offset for min TCK 794 #define SPD_MIRROR_UNBUFFERED 131 // Unbuffered:Address Mapping from Edge Connector to DRAM 795 #define SPD_MIRROR_REGISTERED 136 // Registered:Address Address Mapping from Register to DRAM 796 797 #define SPD_MMID_LSB_DDR4 320 // Module Manufacturer ID Code, Least Significant Byte 798 #define SPD_MMID_MSB_DDR4 321 // Module Manufacturer ID Code, Most Significant Byte 799 #define SPD_MM_LOC_DDR4 322 // Module Manufacturing Location 800 #define SPD_MM_DATE_DDR4 323 // Module Manufacturing Date 323-324 801 #define SPD_MODULE_SN_DDR4 325 // Module Serial Number 325-328 802 #define SPD_MODULE_PN_DDR4 329 // Module Part Number 329-348 803 #define SPD_MODULE_RC_DDR4 349 // Module Revision Code 804 #define SPD_DRAM_MIDC_LSB_DDR4 350 // DRAM Manufacturer ID Code, Least Significant Byte 805 #define SPD_DRAM_MIDC_MSB_DDR4 351 // DRAM Manufacturer ID Code, Most Significant Byte 806 #define SPD_DRAM_REV_DDR4 352 // DRAM Revision ID 807 #define SPD_CRC_LSB_DDR4 382 // LSB of 16-bit CRC 808 #define SPD_CRC_MSB_DDR4 383 // MSB of 16-bit CRC 809 810 // Begin DDR4 module specific section 811 #define SPD_MODULE_NH_DDR4 128 // Module Nominal Height 812 #define SPD_MODULE_MT_DDR4 129 // Module Maximum Thickness 813 #define SPD_REF_RAW_CARD_DDR4 130 // Reference Raw Card Used 814 815 // UDIMM specific bytes 816 // Applicable when Module Type (key byte 3) = 2 817 #define SPD_ADDR_MAP_FECTD_DDR4 131 // Address Mapping from Edge Connector to DRAM 818 819 // RDIMM specific bytes 820 // Applicable when Module Type (key byte 3) = 1 821 #define SPD_RDIMM_ATTR_DDR4 131 // RDIMM module attributes 822 #define SPD_DIMM_HS_DDR4 132 // Module Heat Spreader Solution 823 #define SPD_REG_VEN_LSB_DDR4 133 // Register Vendor ID LSB 824 #define SPD_REG_VEN_MSB_DDR4 134 // Register Vendor ID MSB 825 #define SPD_REG_REV_DDR4 135 // Register Revision 826 #define SPD_ADD_MAPPING_DDR4 136 // Address mapping from Reg to DRAM 827 #define SPD_REG_OD_CTL_DDR4 137 // Register Output Drive Strength for Control 828 #define SPD_REG_OD_CK_DDR4 138 // Register Output Drive Strength for Clock 829 830 // LRDIMM specific bytes 831 // Applicable when Module Type (key byte 3) = 0x4 832 #define SPD_LRDIMM_ATTR_DDR4 131 // LRDIMM module attributes 833 #define SPD_LRBUF_HS_DDR4 132 // LR Buffer Heat Spreader Solution 834 #define SPD_LRBUF_VEN_LSB_DDR4 133 // LR Buffer Vendor ID LSB 835 #define SPD_LRBUF_VEN_MSB_DDR4 134 // LR Buffer Vendor ID MSB 836 #define SPD_LRBUF_REV_DDR4 135 // LR Buffer Register Revision 837 #define SPD_LRBUF_DB_REV_DDR4 139 // LR Buffer Data Buffer Revision 838 #define SPD_LRBUF_DRAM_VREFDQ_R0_DDR4 140 // LR Buffer DRAM VrefDQ for Package Rank 0 839 #define SPD_LRBUF_DRAM_VREFDQ_R1_DDR4 141 // LR Buffer DRAM VrefDQ for Package Rank 1 840 #define SPD_LRBUF_DRAM_VREFDQ_R2_DDR4 142 // LR Buffer DRAM VrefDQ for Package Rank 2 841 #define SPD_LRBUF_DRAM_VREFDQ_R3_DDR4 143 // LR Buffer DRAM VrefDQ for Package Rank 3 842 #define SPD_LRBUF_DB_VREFDQ_DDR4 144 // LR Data Buffer VrefDQ for DRAM Interface 843 #define SPD_LRBUF_DB_DS_RTT_LE1866_DDR4 145 // LR Data Buffer MDQ Drive Strength and RTT for data rate <= 1866 844 #define SPD_LRBUF_DB_DS_RTT_GT1866_LE2400_DDR4 146 // LR Data Buffer MDQ Drive Strength and RTT for data rate > 1866 and <= 2400 845 #define SPD_LRBUF_DB_DS_RTT_GT2400_LE3200_DDR4 147 // LR Data Buffer MDQ Drive Strength and RTT for data rate > 2400 and <= 3200 846 #define SPD_LRBUF_DRAM_DS_DDR4 148 // LR Buffer DRAM Drive Strength (for data rates <= 1866, 1866 < data rate <= 2400, and 2400 < data rate <= 3200) 847 #define SPD_LRBUF_DRAM_ODT_WR_NOM_LE1866_DDR4 149 // LR Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 1866 848 #define SPD_LRBUF_DRAM_ODT_WR_NOM_GT1866_LE2400_DDR4 150 // LR Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate > 1866 and <= 2400 849 #define SPD_LRBUF_DRAM_ODT_WR_NOM_GT2400_LE3200_DDR4 151 // LR Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate > 2400 and <= 3200 850 #define SPD_LRBUF_DRAM_ODT_PARK_LE1866_DDR4 152 // LR Buffer DRAM ODT (RTT_PARK) for data rate <= 1866 851 #define SPD_LRBUF_DRAM_ODT_PARK_GT1866_LE2400_DDR4 153 // LR Buffer DRAM ODT (RTT_PARK) for data rate > 1866 and <= 2400 852 #define SPD_LRBUF_DRAM_ODT_PARK_GT2400_LE3200_DDR4 154 // LR Buffer DRAM ODT (RTT_PARK) for data rate > 2400 and <= 3200 853 854 // 855 // End DDR4 Specific Bytes 856 // 857 #define BANK0 0 858 #define BANK1 BIT0 859 #define BANK2 BIT1 860 #define BANK3 BIT0 + BIT1 861 #define BANK4 BIT2 862 #define BANK5 BIT2 + BIT0 863 #define BANK6 BIT2 + BIT1 864 #define BANK7 BIT2 + BIT1 + BIT0 865 866 #define RDIMM_RC00 0x00 867 #define RDIMM_RC01 0x01 868 #define RDIMM_RC02 0x02 869 #define RDIMM_RC03 0x03 870 #define RDIMM_RC04 0x04 871 #define RDIMM_RC05 0x05 872 #define RDIMM_RC08 0x08 873 #define RDIMM_RC09 0x09 874 #define RDIMM_RC0A 0x0A 875 #define RDIMM_RC0B 0x0B 876 #define RDIMM_RC0C 0x0C 877 #define RDIMM_RC0D 0x0D 878 #define RDIMM_RC0E 0x0E 879 #define RDIMM_RC0F 0x0F 880 #define RDIMM_RC1x 0x10 881 #define RDIMM_RC2x 0x20 882 #define RDIMM_RC3x 0x30 883 #define RDIMM_RC4x 0x40 884 #define RDIMM_RC5x 0x50 885 #define RDIMM_RC6x 0x60 886 #define RDIMM_RC7x 0x70 887 #define RDIMM_RC8x 0x80 888 #define RDIMM_RC9x 0x90 889 #define RDIMM_RCAx 0xA0 890 891 #define LRDIMM_BC00 0x00 892 #define LRDIMM_BC01 0x01 893 #define LRDIMM_BC02 0x02 894 #define LRDIMM_BC03 0x03 895 #define LRDIMM_BC04 0x04 896 #define LRDIMM_BC05 0x05 897 #define LRDIMM_BC06 0x06 898 #define LRDIMM_BC07 0x07 899 #define LRDIMM_BC08 0x08 900 #define LRDIMM_BC09 0x09 901 #define LRDIMM_BC0A 0x0A 902 #define LRDIMM_BC0B 0x0B 903 #define LRDIMM_BC0C 0x0C 904 #define LRDIMM_BC0E 0x0E 905 906 #define LRDIMM_BC0x 0x00 907 #define LRDIMM_BC1x 0x10 908 #define LRDIMM_BC2x 0x20 909 #define LRDIMM_BC3x 0x30 910 #define LRDIMM_BC4x 0x40 911 #define LRDIMM_BC5x 0x50 912 #define LRDIMM_BC6x 0x60 913 #define LRDIMM_BC7x 0x70 914 #define LRDIMM_BC8x 0x80 915 #define LRDIMM_BC9x 0x90 916 #define LRDIMM_BCAx 0xA0 917 #define LRDIMM_BCBx 0xB0 918 #define LRDIMM_BCCx 0xC0 919 #define LRDIMM_BCDx 0xD0 920 #define LRDIMM_BCEx 0xE0 921 #define LRDIMM_BCFx 0xF0 922 #define LRDIMM_F0 0x0 923 #define LRDIMM_F1 0x1 924 #define LRDIMM_F5 0x5 925 #define LRDIMM_F6 0x6 926 #define LRDIMM_F7 0x7 927 #define LRDIMM_F8 0x8 928 #define LRDIMM_F9 0x9 929 930 #endif /* _HW_MEM_INIT_LIB_H_ */ 931
