1 /* tc-m68hc11.c -- Assembler code for the Motorola 68HC11 & 68HC12. 2 Copyright (C) 1999-2016 Free Software Foundation, Inc. 3 Written by Stephane Carrez (stcarrez (at) nerim.fr) 4 XGATE and S12X added by James Murray (jsm (at) jsm-net.demon.co.uk) 5 6 This file is part of GAS, the GNU Assembler. 7 8 GAS is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GAS is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GAS; see the file COPYING. If not, write to 20 the Free Software Foundation, 51 Franklin Street - Fifth Floor, 21 Boston, MA 02110-1301, USA. */ 22 23 #include "as.h" 24 #include "safe-ctype.h" 25 #include "subsegs.h" 26 #include "opcode/m68hc11.h" 27 #include "dwarf2dbg.h" 28 #include "elf/m68hc11.h" 29 30 const char comment_chars[] = ";!"; 31 const char line_comment_chars[] = "#*"; 32 const char line_separator_chars[] = ""; 33 34 const char EXP_CHARS[] = "eE"; 35 const char FLT_CHARS[] = "dD"; 36 37 #define STATE_CONDITIONAL_BRANCH (1) 38 #define STATE_PC_RELATIVE (2) 39 #define STATE_INDEXED_OFFSET (3) 40 #define STATE_INDEXED_PCREL (4) 41 #define STATE_XBCC_BRANCH (5) 42 #define STATE_CONDITIONAL_BRANCH_6812 (6) 43 44 #define STATE_BYTE (0) 45 #define STATE_BITS5 (0) 46 #define STATE_WORD (1) 47 #define STATE_BITS9 (1) 48 #define STATE_LONG (2) 49 #define STATE_BITS16 (2) 50 #define STATE_UNDF (3) /* Symbol undefined in pass1 */ 51 52 /* This macro has no side-effects. */ 53 #define ENCODE_RELAX(what,length) (((what) << 2) + (length)) 54 #define RELAX_STATE(s) ((s) >> 2) 55 #define RELAX_LENGTH(s) ((s) & 3) 56 57 #define IS_OPCODE(C1,C2) (((C1) & 0x0FF) == ((C2) & 0x0FF)) 58 59 /* This table describes how you change sizes for the various types of variable 60 size expressions. This version only supports two kinds. */ 61 62 /* The fields are: 63 How far Forward this mode will reach. 64 How far Backward this mode will reach. 65 How many bytes this mode will add to the size of the frag. 66 Which mode to go to if the offset won't fit in this one. */ 67 68 relax_typeS md_relax_table[] = 69 { 70 {1, 1, 0, 0}, /* First entries aren't used. */ 71 {1, 1, 0, 0}, /* For no good reason except. */ 72 {1, 1, 0, 0}, /* that the VAX doesn't either. */ 73 {1, 1, 0, 0}, 74 75 /* Relax for bcc <L>. 76 These insns are translated into b!cc +3 jmp L. */ 77 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_WORD)}, 78 {0, 0, 3, 0}, 79 {1, 1, 0, 0}, 80 {1, 1, 0, 0}, 81 82 /* Relax for bsr <L> and bra <L>. 83 These insns are translated into jsr and jmp. */ 84 {(127), (-128), 0, ENCODE_RELAX (STATE_PC_RELATIVE, STATE_WORD)}, 85 {0, 0, 1, 0}, 86 {1, 1, 0, 0}, 87 {1, 1, 0, 0}, 88 89 /* Relax for indexed offset: 5-bits, 9-bits, 16-bits. */ 90 {(15), (-16), 0, ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS9)}, 91 {(255), (-256), 1, ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS16)}, 92 {0, 0, 2, 0}, 93 {1, 1, 0, 0}, 94 95 /* Relax for PC relative offset: 5-bits, 9-bits, 16-bits. 96 For the 9-bit case, there will be a -1 correction to take into 97 account the new byte that's why the range is -255..256. */ 98 {(15), (-16), 0, ENCODE_RELAX (STATE_INDEXED_PCREL, STATE_BITS9)}, 99 {(256), (-255), 1, ENCODE_RELAX (STATE_INDEXED_PCREL, STATE_BITS16)}, 100 {0, 0, 2, 0}, 101 {1, 1, 0, 0}, 102 103 /* Relax for dbeq/ibeq/tbeq r,<L>: 104 These insns are translated into db!cc +3 jmp L. */ 105 {(255), (-256), 0, ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_WORD)}, 106 {0, 0, 3, 0}, 107 {1, 1, 0, 0}, 108 {1, 1, 0, 0}, 109 110 /* Relax for bcc <L> on 68HC12. 111 These insns are translated into lbcc <L>. */ 112 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_WORD)}, 113 {0, 0, 2, 0}, 114 {1, 1, 0, 0}, 115 {1, 1, 0, 0}, 116 117 }; 118 119 /* 68HC11 and 68HC12 registers. They are numbered according to the 68HC12. */ 120 typedef enum register_id 121 { 122 REG_NONE = -1, 123 REG_A = 0, 124 REG_B = 1, 125 REG_CCR = 2, 126 REG_D = 4, 127 REG_X = 5, 128 REG_Y = 6, 129 REG_SP = 7, 130 REG_PC = 8, 131 REG_R0 = 0, 132 REG_R1 = 1, 133 REG_R2 = 2, 134 REG_R3 = 3, 135 REG_R4 = 4, 136 REG_R5 = 5, 137 REG_R6 = 6, 138 REG_R7 = 7, 139 REG_SP_XG = 8, 140 REG_PC_XG = 9, 141 REG_CCR_XG = 10 142 } register_id; 143 144 typedef struct operand 145 { 146 expressionS exp; 147 register_id reg1; 148 register_id reg2; 149 int mode; 150 } operand; 151 152 struct m68hc11_opcode_def 153 { 154 long format; 155 int min_operands; 156 int max_operands; 157 int nb_modes; 158 int used; 159 struct m68hc11_opcode *opcode; 160 }; 161 162 static struct m68hc11_opcode_def *m68hc11_opcode_defs = 0; 163 static int m68hc11_nb_opcode_defs = 0; 164 165 typedef struct alias 166 { 167 const char *name; 168 const char *alias; 169 } alias; 170 171 static alias alias_opcodes[] = 172 { 173 {"cpd", "cmpd"}, 174 {"cpx", "cmpx"}, 175 {"cpy", "cmpy"}, 176 {0, 0} 177 }; 178 179 struct m9s12xg_opcode_def 180 { 181 long format; 182 int min_operands; 183 int max_operands; 184 int nb_modes; 185 int used; 186 struct m9s12xg_opcode *opcode; 187 }; 188 189 /* Local functions. */ 190 static register_id reg_name_search (char *); 191 static register_id register_name (void); 192 static int cmp_opcode (struct m68hc11_opcode *, struct m68hc11_opcode *); 193 static char *print_opcode_format (struct m68hc11_opcode *, int); 194 static char *skip_whites (char *); 195 static int check_range (long, int); 196 static void print_opcode_list (void); 197 static void get_default_target (void); 198 static void print_insn_format (char *); 199 static int get_operand (operand *, int, long); 200 static void fixup8 (expressionS *, int, int); 201 static void fixup16 (expressionS *, int, int); 202 static void fixup24 (expressionS *, int, int); 203 static void fixup8_xg (expressionS *, int, int); 204 static unsigned char convert_branch (unsigned char); 205 static char *m68hc11_new_insn (int); 206 static void build_dbranch_insn (struct m68hc11_opcode *, 207 operand *, int, int); 208 static int build_indexed_byte (operand *, int, int); 209 static int build_reg_mode (operand *, int); 210 211 static struct m68hc11_opcode *find (struct m68hc11_opcode_def *, 212 operand *, int); 213 static struct m68hc11_opcode *find_opcode (struct m68hc11_opcode_def *, 214 operand *, int *); 215 static void build_jump_insn (struct m68hc11_opcode *, operand *, int, int); 216 static void build_insn_xg (struct m68hc11_opcode *, operand *, int); 217 static void build_insn (struct m68hc11_opcode *, operand *, int); 218 static int relaxable_symbol (symbolS *); 219 220 /* Pseudo op to indicate a relax group. */ 221 static void s_m68hc11_relax (int); 222 223 /* Pseudo op to control the ELF flags. */ 224 static void s_m68hc11_mode (int); 225 226 /* Process directives specified via pseudo ops. */ 227 static void s_m68hc11_parse_pseudo_instruction (int); 228 229 /* Mark the symbols with STO_M68HC12_FAR to indicate the functions 230 are using 'rtc' for returning. It is necessary to use 'call' 231 to invoke them. This is also used by the debugger to correctly 232 find the stack frame. */ 233 static void s_m68hc11_mark_symbol (int); 234 235 /* Controls whether relative branches can be turned into long branches. 236 When the relative offset is too large, the insn are changed: 237 bra -> jmp 238 bsr -> jsr 239 bcc -> b!cc +3 240 jmp L 241 dbcc -> db!cc +3 242 jmp L 243 244 Setting the flag forbidds this. */ 245 static short flag_fixed_branches = 0; 246 247 /* Force to use long jumps (absolute) instead of relative branches. */ 248 static short flag_force_long_jumps = 0; 249 250 /* Change the direct addressing mode into an absolute addressing mode 251 when the insn does not support direct addressing. 252 For example, "clr *ZD0" is normally not possible and is changed 253 into "clr ZDO". */ 254 static short flag_strict_direct_addressing = 1; 255 256 /* When an opcode has invalid operand, print out the syntax of the opcode 257 to stderr. */ 258 static short flag_print_insn_syntax = 0; 259 260 /* Dumps the list of instructions with syntax and then exit: 261 1 -> Only dumps the list (sorted by name) 262 2 -> Generate an example (or test) that can be compiled. */ 263 static short flag_print_opcodes = 0; 264 265 /* Opcode hash table. */ 266 static struct hash_control *m68hc11_hash; 267 268 /* Current cpu (either cpu6811 or cpu6812). This is determined automagically 269 by 'get_default_target' by looking at default BFD vector. This is overridden 270 with the -m<cpu> option. */ 271 static int current_architecture = 0; 272 273 /* Default cpu determined by 'get_default_target'. */ 274 static const char *default_cpu; 275 276 /* Number of opcodes in the sorted table (filtered by current cpu). */ 277 static int num_opcodes; 278 279 /* The opcodes sorted by name and filtered by current cpu. */ 280 static struct m68hc11_opcode *m68hc11_sorted_opcodes; 281 282 /* ELF flags to set in the output file header. */ 283 static int elf_flags = E_M68HC11_F64; 284 285 /* These are the machine dependent pseudo-ops. These are included so 286 the assembler can work on the output from the SUN C compiler, which 287 generates these. */ 288 289 /* This table describes all the machine specific pseudo-ops the assembler 290 has to support. The fields are: 291 pseudo-op name without dot 292 function to call to execute this pseudo-op 293 Integer arg to pass to the function. */ 294 const pseudo_typeS md_pseudo_table[] = 295 { 296 /* The following pseudo-ops are supported for MRI compatibility. */ 297 {"fcb", cons, 1}, 298 {"fdb", cons, 2}, 299 {"fqb", cons, 4}, 300 {"fcc", stringer, 8 + 1}, 301 {"rmb", s_space, 0}, 302 303 /* Motorola ALIS. */ 304 {"xrefb", s_ignore, 0}, /* Same as xref */ 305 306 /* Gcc driven relaxation. */ 307 {"relax", s_m68hc11_relax, 0}, 308 309 /* .mode instruction (ala SH). */ 310 {"mode", s_m68hc11_mode, 0}, 311 312 /* .far instruction. */ 313 {"far", s_m68hc11_mark_symbol, STO_M68HC12_FAR}, 314 315 /* .interrupt instruction. */ 316 {"interrupt", s_m68hc11_mark_symbol, STO_M68HC12_INTERRUPT}, 317 318 /* .nobankwarning instruction. */ 319 {"nobankwarning", s_m68hc11_parse_pseudo_instruction, E_M68HC11_NO_BANK_WARNING}, 320 321 {0, 0, 0} 322 }; 323 324 /* Options and initialization. */ 326 327 const char *md_shortopts = "Sm:"; 328 329 struct option md_longopts[] = 330 { 331 #define OPTION_FORCE_LONG_BRANCH (OPTION_MD_BASE) 332 {"force-long-branches", no_argument, NULL, OPTION_FORCE_LONG_BRANCH}, 333 {"force-long-branchs", no_argument, NULL, OPTION_FORCE_LONG_BRANCH}, /* Misspelt version kept for backwards compatibility. */ 334 335 #define OPTION_SHORT_BRANCHES (OPTION_MD_BASE + 1) 336 {"short-branches", no_argument, NULL, OPTION_SHORT_BRANCHES}, 337 {"short-branchs", no_argument, NULL, OPTION_SHORT_BRANCHES}, /* Misspelt version kept for backwards compatibility. */ 338 339 #define OPTION_STRICT_DIRECT_MODE (OPTION_MD_BASE + 2) 340 {"strict-direct-mode", no_argument, NULL, OPTION_STRICT_DIRECT_MODE}, 341 342 #define OPTION_PRINT_INSN_SYNTAX (OPTION_MD_BASE + 3) 343 {"print-insn-syntax", no_argument, NULL, OPTION_PRINT_INSN_SYNTAX}, 344 345 #define OPTION_PRINT_OPCODES (OPTION_MD_BASE + 4) 346 {"print-opcodes", no_argument, NULL, OPTION_PRINT_OPCODES}, 347 348 #define OPTION_GENERATE_EXAMPLE (OPTION_MD_BASE + 5) 349 {"generate-example", no_argument, NULL, OPTION_GENERATE_EXAMPLE}, 350 351 #define OPTION_MSHORT (OPTION_MD_BASE + 6) 352 {"mshort", no_argument, NULL, OPTION_MSHORT}, 353 354 #define OPTION_MLONG (OPTION_MD_BASE + 7) 355 {"mlong", no_argument, NULL, OPTION_MLONG}, 356 357 #define OPTION_MSHORT_DOUBLE (OPTION_MD_BASE + 8) 358 {"mshort-double", no_argument, NULL, OPTION_MSHORT_DOUBLE}, 359 360 #define OPTION_MLONG_DOUBLE (OPTION_MD_BASE + 9) 361 {"mlong-double", no_argument, NULL, OPTION_MLONG_DOUBLE}, 362 363 #define OPTION_XGATE_RAMOFFSET (OPTION_MD_BASE + 10) 364 {"xgate-ramoffset", no_argument, NULL, OPTION_XGATE_RAMOFFSET}, 365 366 {NULL, no_argument, NULL, 0} 367 }; 368 size_t md_longopts_size = sizeof (md_longopts); 369 370 /* Get the target cpu for the assembler. This is based on the configure 371 options and on the -m68hc11/-m68hc12 option. If no option is specified, 372 we must get the default. */ 373 const char * 374 m68hc11_arch_format (void) 375 { 376 get_default_target (); 377 if (current_architecture & cpu6811) 378 return "elf32-m68hc11"; 379 else 380 return "elf32-m68hc12"; 381 } 382 383 enum bfd_architecture 384 m68hc11_arch (void) 385 { 386 get_default_target (); 387 if (current_architecture & cpu6811) 388 return bfd_arch_m68hc11; 389 else 390 return bfd_arch_m68hc12; 391 } 392 393 int 394 m68hc11_mach (void) 395 { 396 return 0; 397 } 398 399 /* Listing header selected according to cpu. */ 400 const char * 401 m68hc11_listing_header (void) 402 { 403 if (current_architecture & cpu6811) 404 return "M68HC11 GAS "; 405 else if (current_architecture & cpuxgate) 406 return "XGATE GAS "; 407 else if (current_architecture & cpu9s12x) 408 return "S12X GAS "; 409 else 410 return "M68HC12 GAS "; 411 } 412 413 void 414 md_show_usage (FILE *stream) 415 { 416 get_default_target (); 417 fprintf (stream, _("\ 418 Motorola 68HC11/68HC12/68HCS12 options:\n\ 419 -m68hc11 | -m68hc12 |\n\ 420 -m68hcs12 | -mm9s12x |\n\ 421 -mm9s12xg specify the processor [default %s]\n\ 422 -mshort use 16-bit int ABI (default)\n\ 423 -mlong use 32-bit int ABI\n\ 424 -mshort-double use 32-bit double ABI\n\ 425 -mlong-double use 64-bit double ABI (default)\n\ 426 --force-long-branches always turn relative branches into absolute ones\n\ 427 -S,--short-branches do not turn relative branches into absolute ones\n\ 428 when the offset is out of range\n\ 429 --strict-direct-mode do not turn the direct mode into extended mode\n\ 430 when the instruction does not support direct mode\n\ 431 --print-insn-syntax print the syntax of instruction in case of error\n\ 432 --print-opcodes print the list of instructions with syntax\n\ 433 --xgate-ramoffset offset ram addresses by 0xc000\n\ 434 --generate-example generate an example of each instruction\n\ 435 (used for testing)\n"), default_cpu); 436 437 } 438 439 /* Try to identify the default target based on the BFD library. */ 440 static void 441 get_default_target (void) 442 { 443 const bfd_target *target; 444 bfd abfd; 445 446 if (current_architecture != 0) 447 return; 448 449 default_cpu = "unknown"; 450 target = bfd_find_target (0, &abfd); 451 if (target && target->name) 452 { 453 if (strcmp (target->name, "elf32-m68hc12") == 0) 454 { 455 current_architecture = cpu6812; 456 default_cpu = "m68hc12"; 457 } 458 else if (strcmp (target->name, "elf32-m68hc11") == 0) 459 { 460 current_architecture = cpu6811; 461 default_cpu = "m68hc11"; 462 } 463 else 464 { 465 as_bad (_("Default target `%s' is not supported."), target->name); 466 } 467 } 468 } 469 470 void 471 m68hc11_print_statistics (FILE *file) 472 { 473 int i; 474 struct m68hc11_opcode_def *opc; 475 476 hash_print_statistics (file, "opcode table", m68hc11_hash); 477 478 opc = m68hc11_opcode_defs; 479 if (opc == 0 || m68hc11_nb_opcode_defs == 0) 480 return; 481 482 /* Dump the opcode statistics table. */ 483 fprintf (file, _("Name # Modes Min ops Max ops Modes mask # Used\n")); 484 for (i = 0; i < m68hc11_nb_opcode_defs; i++, opc++) 485 { 486 fprintf (file, "%-7.7s %5d %7d %7d 0x%08lx %7d\n", 487 opc->opcode->name, 488 opc->nb_modes, 489 opc->min_operands, opc->max_operands, opc->format, opc->used); 490 } 491 } 492 493 int 494 md_parse_option (int c, const char *arg) 495 { 496 get_default_target (); 497 switch (c) 498 { 499 /* -S means keep external to 2 bit offset rather than 16 bit one. */ 500 case OPTION_SHORT_BRANCHES: 501 case 'S': 502 flag_fixed_branches = 1; 503 break; 504 505 case OPTION_FORCE_LONG_BRANCH: 506 flag_force_long_jumps = 1; 507 break; 508 509 case OPTION_PRINT_INSN_SYNTAX: 510 flag_print_insn_syntax = 1; 511 break; 512 513 case OPTION_PRINT_OPCODES: 514 flag_print_opcodes = 1; 515 break; 516 517 case OPTION_STRICT_DIRECT_MODE: 518 flag_strict_direct_addressing = 0; 519 break; 520 521 case OPTION_GENERATE_EXAMPLE: 522 flag_print_opcodes = 2; 523 break; 524 525 case OPTION_MSHORT: 526 elf_flags &= ~E_M68HC11_I32; 527 break; 528 529 case OPTION_MLONG: 530 elf_flags |= E_M68HC11_I32; 531 break; 532 533 case OPTION_MSHORT_DOUBLE: 534 elf_flags &= ~E_M68HC11_F64; 535 break; 536 537 case OPTION_MLONG_DOUBLE: 538 elf_flags |= E_M68HC11_F64; 539 break; 540 541 case OPTION_XGATE_RAMOFFSET: 542 elf_flags |= E_M68HC11_XGATE_RAMOFFSET; 543 break; 544 545 case 'm': 546 if ((strcasecmp (arg, "68hc11") == 0) 547 || (strcasecmp (arg, "m68hc11") == 0)) 548 current_architecture = cpu6811; 549 else if ((strcasecmp (arg, "68hc12") == 0) 550 || (strcasecmp (arg, "m68hc12") == 0)) 551 current_architecture = cpu6812; 552 else if ((strcasecmp (arg, "68hcs12") == 0) 553 || (strcasecmp (arg, "m68hcs12") == 0)) 554 current_architecture = cpu6812 | cpu6812s; 555 else if (strcasecmp (arg, "m9s12x") == 0) 556 current_architecture = cpu6812 | cpu6812s | cpu9s12x; 557 else if ((strcasecmp (arg, "m9s12xg") == 0) 558 || (strcasecmp (arg, "xgate") == 0)) 559 /* xgate for backwards compatability */ 560 current_architecture = cpuxgate; 561 else 562 as_bad (_("Option `%s' is not recognized."), arg); 563 break; 564 565 default: 566 return 0; 567 } 568 569 return 1; 570 } 571 572 symbolS * 574 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 575 { 576 return 0; 577 } 578 579 const char * 580 md_atof (int type, char *litP, int *sizeP) 581 { 582 return ieee_md_atof (type, litP, sizeP, TRUE); 583 } 584 585 valueT 586 md_section_align (asection *seg, valueT addr) 587 { 588 int align = bfd_get_section_alignment (stdoutput, seg); 589 return ((addr + (1 << align) - 1) & -(1 << align)); 590 } 591 592 static int 593 cmp_opcode (struct m68hc11_opcode *op1, struct m68hc11_opcode *op2) 594 { 595 return strcmp (op1->name, op2->name); 596 } 597 598 #define IS_CALL_SYMBOL(MODE) \ 599 (((MODE) & (M6812_OP_PAGE|M6811_OP_IND16)) \ 600 == ((M6812_OP_PAGE|M6811_OP_IND16))) 601 602 /* Initialize the assembler. Create the opcode hash table 603 (sorted on the names) with the M6811 opcode table 604 (from opcode library). */ 605 void 606 md_begin (void) 607 { 608 const char *prev_name = ""; 609 struct m68hc11_opcode *opcodes; 610 struct m68hc11_opcode_def *opc = 0; 611 int i, j; 612 613 get_default_target (); 614 615 m68hc11_hash = hash_new (); 616 617 /* Get a writable copy of the opcode table and sort it on the names. */ 618 opcodes = XNEWVEC (struct m68hc11_opcode, m68hc11_num_opcodes); 619 m68hc11_sorted_opcodes = opcodes; 620 num_opcodes = 0; 621 for (i = 0; i < m68hc11_num_opcodes; i++) 622 { 623 if (m68hc11_opcodes[i].arch & current_architecture) 624 { 625 opcodes[num_opcodes] = m68hc11_opcodes[i]; 626 if (opcodes[num_opcodes].name[0] == 'b' 627 && opcodes[num_opcodes].format & M6811_OP_JUMP_REL 628 && !(opcodes[num_opcodes].format & M6811_OP_BITMASK)) 629 { 630 num_opcodes++; 631 opcodes[num_opcodes] = m68hc11_opcodes[i]; 632 } 633 num_opcodes++; 634 for (j = 0; alias_opcodes[j].name != 0; j++) 635 if (strcmp (m68hc11_opcodes[i].name, alias_opcodes[j].name) == 0) 636 { 637 opcodes[num_opcodes] = m68hc11_opcodes[i]; 638 opcodes[num_opcodes].name = alias_opcodes[j].alias; 639 num_opcodes++; 640 break; 641 } 642 } 643 } 644 qsort (opcodes, num_opcodes, sizeof (struct m68hc11_opcode), 645 (int (*) (const void*, const void*)) cmp_opcode); 646 647 opc = XNEWVEC (struct m68hc11_opcode_def, num_opcodes); 648 m68hc11_opcode_defs = opc--; 649 650 /* Insert unique names into hash table. The M6811 instruction set 651 has several identical opcode names that have different opcodes based 652 on the operands. This hash table then provides a quick index to 653 the first opcode with a particular name in the opcode table. */ 654 for (i = 0; i < num_opcodes; i++, opcodes++) 655 { 656 int expect; 657 658 if (strcmp (prev_name, opcodes->name)) 659 { 660 prev_name = (char *) opcodes->name; 661 662 opc++; 663 opc->format = 0; 664 opc->min_operands = 100; 665 opc->max_operands = 0; 666 opc->nb_modes = 0; 667 opc->opcode = opcodes; 668 opc->used = 0; 669 hash_insert (m68hc11_hash, opcodes->name, opc); 670 } 671 opc->nb_modes++; 672 opc->format |= opcodes->format; 673 674 /* See how many operands this opcode needs. */ 675 expect = 0; 676 if (opcodes->arch == cpuxgate) 677 { 678 if (opcodes->format & (M68XG_OP_IMM3 | M68XG_OP_R | M68XG_OP_REL9 679 | M68XG_OP_REL10 )) 680 expect = 1; 681 else if (opcodes->format & (M68XG_OP_R_R | M68XG_OP_R_IMM4 682 | M68XG_OP_R_IMM8 | M68XG_OP_R_IMM8)) 683 expect = 2; 684 else if (opcodes->format & (M68XG_OP_R_R_R | M68XG_OP_R_R_OFFS5 685 | M68XG_OP_RD_RB_RI | M68XG_OP_RD_RB_RIp 686 | M68XG_OP_RD_RB_mRI)) 687 expect = 3; 688 } 689 else 690 { 691 if (opcodes->format & M6811_OP_MASK) 692 expect++; 693 if (opcodes->format & M6811_OP_BITMASK) 694 expect++; 695 if (opcodes->format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) 696 expect++; 697 if (opcodes->format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2)) 698 expect++; 699 /* Special case for call instruction. */ 700 if ((opcodes->format & M6812_OP_PAGE) 701 && !(opcodes->format & M6811_OP_IND16)) 702 expect++; 703 } 704 705 if (expect < opc->min_operands) 706 opc->min_operands = expect; 707 if (IS_CALL_SYMBOL (opcodes->format)) 708 expect++; 709 if (expect > opc->max_operands) 710 opc->max_operands = expect; 711 } 712 opc++; 713 m68hc11_nb_opcode_defs = opc - m68hc11_opcode_defs; 714 715 if (flag_print_opcodes) 716 { 717 print_opcode_list (); 718 exit (EXIT_SUCCESS); 719 } 720 } 721 722 void 723 m68hc11_init_after_args (void) 724 { 725 } 726 727 /* Builtin help. */ 729 730 /* Return a string that represents the operand format for the instruction. 731 When example is true, this generates an example of operand. This is used 732 to give an example and also to generate a test. */ 733 734 static char * 735 print_opcode_format (struct m68hc11_opcode *opcode, int example) 736 { 737 static char buf[128]; 738 int format = opcode->format; 739 char *p; 740 741 p = buf; 742 buf[0] = 0; 743 744 if (current_architecture == cpuxgate) 745 { 746 if (format & M68XG_OP_IMM3) 747 { 748 if (example) 749 sprintf (p, "#%d", rand () & 0x007); 750 else 751 strcpy (p, _("imm3")); 752 p = &p[strlen (p)]; 753 } 754 else if (format & M68XG_OP_R) 755 { 756 if (example) 757 sprintf (p, "R%d", rand () & 0x07); 758 else 759 strcpy (p, _("RD")); 760 p = &p[strlen (p)]; 761 } 762 else if (format & M68XG_OP_R_R) 763 { 764 if (example) 765 sprintf (p, "R%d,R%d", rand () & 0x07, rand () & 0x07); 766 else 767 strcpy (p, _("RD,RS")); 768 p = &p[strlen (p)]; 769 } 770 else if (format & M68XG_OP_R_IMM4) 771 { 772 if (example) 773 sprintf (p, "R%d,#%d", rand () & 0x07, rand () & 0x0f); 774 else 775 strcpy (p, _("RI, #imm4")); 776 p = &p[strlen (p)]; 777 } 778 else if (format & M68XG_OP_R_R_R) 779 { 780 if (example) 781 sprintf (p, "R%d,R%d,R%d", rand () & 0x07, rand () & 0x07, rand () & 0x07); 782 else 783 strcpy (p, "RD,RS1,RS2"); 784 p = &p[strlen (p)]; 785 } 786 else if (format & M68XG_OP_REL9) 787 { 788 if (example) 789 sprintf (p, "%d", rand () & 0x1FF); 790 else 791 strcpy (p, "<rel9>"); 792 p = &p[strlen (p)]; 793 } 794 else if (format & M68XG_OP_REL10) 795 { 796 if (example) 797 sprintf (p, "%d", rand () & 0x3FF); 798 else 799 strcpy (p, "<rel10>"); 800 p = &p[strlen (p)]; 801 } 802 else if (format & M68XG_OP_R_R_OFFS5) 803 { 804 if (example) 805 sprintf (p, "R%d, (R%d, #0x%x)", rand () & 0x07, rand () & 0x07, rand () & 0x1f); 806 else 807 strcpy (p, _("RD, (RI,#offs5)")); 808 p = &p[strlen (p)]; 809 } 810 else if (format & M68XG_OP_RD_RB_RI) 811 { 812 if (example) 813 sprintf (p, "R%d, (R%d, R%d)", rand () & 0x07, rand () & 0x07, rand () & 0x07); 814 else 815 strcpy (p, "RD, (RB, RI)"); 816 p = &p[strlen (p)]; 817 } 818 else if (format & M68XG_OP_RD_RB_RIp) 819 { 820 if (example) 821 sprintf (p, "R%d, (R%d, R%d+)", rand () & 0x07, rand () & 0x07, rand () & 0x07); 822 else 823 strcpy (p, "RD, (RB, RI+)"); 824 p = &p[strlen (p)]; 825 } 826 else if (format & M68XG_OP_RD_RB_mRI) 827 { 828 if (example) 829 sprintf (p, "R%d, (R%d, -R%d)", rand () & 0x07, rand () & 0x07, rand () & 0x07); 830 else 831 strcpy (p, "RD, (RB, -RI)"); 832 p = &p[strlen (p)]; 833 } 834 else if (format & M68XG_OP_R_IMM8) 835 { 836 if (example) 837 sprintf (p, "R%d, #0x%x", rand () & 0x07, rand () & 0xff); 838 else 839 strcpy (p, "RD, #imm8"); 840 p = &p[strlen (p)]; 841 } 842 else if (format & M68XG_OP_R_IMM16) 843 { 844 if (example) 845 sprintf (p, "R%d, #0x%x", rand () & 0x07, rand () & 0xffff); 846 else 847 strcpy (p, "RD, #imm16"); 848 p = &p[strlen (p)]; 849 } 850 } 851 else 852 { 853 854 if (format & M6811_OP_IMM8) 855 { 856 if (example) 857 sprintf (p, "#%d", rand () & 0x0FF); 858 else 859 strcpy (p, _("#<imm8>")); 860 p = &p[strlen (p)]; 861 } 862 863 if (format & M6811_OP_IMM16) 864 { 865 if (example) 866 sprintf (p, "#%d", rand () & 0x0FFFF); 867 else 868 strcpy (p, _("#<imm16>")); 869 p = &p[strlen (p)]; 870 } 871 872 if (format & M6811_OP_IX) 873 { 874 if (example) 875 sprintf (p, "%d,X", rand () & 0x0FF); 876 else 877 strcpy (p, _("<imm8>,X")); 878 p = &p[strlen (p)]; 879 } 880 881 if (format & M6811_OP_IY) 882 { 883 if (example) 884 sprintf (p, "%d,X", rand () & 0x0FF); 885 else 886 strcpy (p, _("<imm8>,X")); 887 p = &p[strlen (p)]; 888 } 889 890 if (format & M6812_OP_IDX) 891 { 892 if (example) 893 sprintf (p, "%d,X", rand () & 0x0FF); 894 else 895 strcpy (p, "n,r"); 896 p = &p[strlen (p)]; 897 } 898 899 if (format & M6812_OP_PAGE) 900 { 901 if (example) 902 sprintf (p, ", %d", rand () & 0x0FF); 903 else 904 strcpy (p, ", <page>"); 905 p = &p[strlen (p)]; 906 } 907 908 if (format & M6811_OP_DIRECT) 909 { 910 if (example) 911 sprintf (p, "*Z%d", rand () & 0x0FF); 912 else 913 strcpy (p, _("*<abs8>")); 914 p = &p[strlen (p)]; 915 } 916 917 if (format & M6811_OP_BITMASK) 918 { 919 if (buf[0]) 920 *p++ = ' '; 921 922 if (example) 923 sprintf (p, "#$%02x", rand () & 0x0FF); 924 else 925 strcpy (p, _("#<mask>")); 926 927 p = &p[strlen (p)]; 928 if (format & M6811_OP_JUMP_REL) 929 *p++ = ' '; 930 } 931 932 if (format & M6811_OP_IND16) 933 { 934 if (example) 935 sprintf (p, _("symbol%d"), rand () & 0x0FF); 936 else 937 strcpy (p, _("<abs>")); 938 939 p = &p[strlen (p)]; 940 } 941 942 if (format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) 943 { 944 if (example) 945 { 946 if (format & M6811_OP_BITMASK) 947 { 948 sprintf (p, ".+%d", rand () & 0x7F); 949 } 950 else 951 { 952 sprintf (p, "L%d", rand () & 0x0FF); 953 } 954 } 955 else 956 strcpy (p, _("<label>")); 957 } 958 } 959 return buf; 960 } 961 962 /* Prints the list of instructions with the possible operands. */ 963 static void 964 print_opcode_list (void) 965 { 966 int i; 967 const char *prev_name = ""; 968 struct m68hc11_opcode *opcodes; 969 int example = flag_print_opcodes == 2; 970 971 if (example) 972 printf (_("# Example of `%s' instructions\n\t.sect .text\n_start:\n"), 973 default_cpu); 974 975 opcodes = m68hc11_sorted_opcodes; 976 977 /* Walk the list sorted on names (by md_begin). We only report 978 one instruction per line, and we collect the different operand 979 formats. */ 980 for (i = 0; i < num_opcodes; i++, opcodes++) 981 { 982 char *fmt = print_opcode_format (opcodes, example); 983 984 if (example) 985 { 986 printf ("L%d:\t", i); 987 printf ("%s %s\n", opcodes->name, fmt); 988 } 989 else 990 { 991 if (strcmp (prev_name, opcodes->name)) 992 { 993 if (i > 0) 994 printf ("\n"); 995 996 printf ("%-5.5s ", opcodes->name); 997 prev_name = (char *) opcodes->name; 998 } 999 if (fmt[0]) 1000 printf (" [%s]", fmt); 1001 } 1002 } 1003 printf ("\n"); 1004 } 1005 1006 /* Print the instruction format. This operation is called when some 1007 instruction is not correct. Instruction format is printed as an 1008 error message. */ 1009 static void 1010 print_insn_format (char *name) 1011 { 1012 struct m68hc11_opcode_def *opc; 1013 struct m68hc11_opcode *opcode; 1014 char buf[128]; 1015 1016 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, name); 1017 if (opc == NULL) 1018 { 1019 as_bad (_("Instruction `%s' is not recognized."), name); 1020 return; 1021 } 1022 opcode = opc->opcode; 1023 1024 as_bad (_("Instruction formats for `%s':"), name); 1025 do 1026 { 1027 char *fmt; 1028 1029 fmt = print_opcode_format (opcode, 0); 1030 sprintf (buf, "\t%-5.5s %s", opcode->name, fmt); 1031 1032 as_bad ("%s", buf); 1033 opcode++; 1034 } 1035 while (strcmp (opcode->name, name) == 0); 1036 } 1037 1038 /* Analysis of 68HC11 and 68HC12 operands. */ 1040 1041 /* reg_name_search() finds the register number given its name. 1042 Returns the register number or REG_NONE on failure. */ 1043 static register_id 1044 reg_name_search (char *name) 1045 { 1046 if (strcasecmp (name, "x") == 0 || strcasecmp (name, "ix") == 0) 1047 return REG_X; 1048 if (strcasecmp (name, "y") == 0 || strcasecmp (name, "iy") == 0) 1049 return REG_Y; 1050 if (strcasecmp (name, "a") == 0) 1051 return REG_A; 1052 if (strcasecmp (name, "b") == 0) 1053 return REG_B; 1054 if (strcasecmp (name, "d") == 0) 1055 return REG_D; 1056 if (strcasecmp (name, "sp") == 0) 1057 return REG_SP; 1058 if (strcasecmp (name, "pc") == 0) 1059 return REG_PC; 1060 if (strcasecmp (name, "ccr") == 0) 1061 return REG_CCR; 1062 /* XGATE */ 1063 if (strcasecmp (name, "r0") == 0) 1064 return REG_R0; 1065 if (strcasecmp (name, "r1") == 0) 1066 return REG_R1; 1067 if (strcasecmp (name, "r2") == 0) 1068 return REG_R2; 1069 if (strcasecmp (name, "r3") == 0) 1070 return REG_R3; 1071 if (strcasecmp (name, "r4") == 0) 1072 return REG_R4; 1073 if (strcasecmp (name, "r5") == 0) 1074 return REG_R5; 1075 if (strcasecmp (name, "r6") == 0) 1076 return REG_R6; 1077 if (strcasecmp (name, "r7") == 0) 1078 return REG_R7; 1079 if (strcasecmp (name, "sp") == 0) 1080 return REG_SP_XG; 1081 if (strcasecmp (name, "pc") == 0) 1082 return REG_PC_XG; 1083 if (strcasecmp (name, "ccr") == 0) 1084 return REG_CCR_XG; 1085 return REG_NONE; 1086 } 1087 1088 static char * 1089 skip_whites (char *p) 1090 { 1091 while (*p == ' ' || *p == '\t') 1092 p++; 1093 1094 return p; 1095 } 1096 1097 /* Check the string at input_line_pointer 1098 to see if it is a valid register name. */ 1099 static register_id 1100 register_name (void) 1101 { 1102 register_id reg_number; 1103 char c, *p = input_line_pointer; 1104 1105 if (!is_name_beginner (*p++)) 1106 return REG_NONE; 1107 1108 while (is_part_of_name (*p++)) 1109 continue; 1110 1111 c = *--p; 1112 if (c) 1113 *p++ = 0; 1114 1115 /* Look to see if it's in the register table. */ 1116 reg_number = reg_name_search (input_line_pointer); 1117 if (reg_number != REG_NONE) 1118 { 1119 if (c) 1120 *--p = c; 1121 1122 input_line_pointer = p; 1123 return reg_number; 1124 } 1125 if (c) 1126 *--p = c; 1127 1128 return reg_number; 1129 } 1130 #define M6811_OP_CALL_ADDR 0x00800000 1131 #define M6811_OP_PAGE_ADDR 0x04000000 1132 1133 /* Parse a string of operands and return an array of expressions. 1134 1135 Operand mode[0] mode[1] exp[0] exp[1] 1136 #n M6811_OP_IMM16 - O_* 1137 *<exp> M6811_OP_DIRECT - O_* 1138 .{+-}<exp> M6811_OP_JUMP_REL - O_* 1139 <exp> M6811_OP_IND16 - O_* 1140 ,r N,r M6812_OP_IDX M6812_OP_REG O_constant O_register 1141 n,-r M6812_PRE_DEC M6812_OP_REG O_constant O_register 1142 n,+r M6812_PRE_INC " " 1143 n,r- M6812_POST_DEC " " 1144 n,r+ M6812_POST_INC " " 1145 A,r B,r D,r M6811_OP_REG M6812_OP_REG O_register O_register 1146 [D,r] M6811_OP_D_IDX M6812_OP_REG O_register O_register 1147 [n,r] M6811_OP_D_IDX_2 M6812_OP_REG O_constant O_register */ 1148 static int 1149 get_operand (operand *oper, int which, long opmode) 1150 { 1151 char *p = input_line_pointer; 1152 int mode; 1153 register_id reg; 1154 1155 oper->exp.X_op = O_absent; 1156 oper->reg1 = REG_NONE; 1157 oper->reg2 = REG_NONE; 1158 mode = M6811_OP_NONE; 1159 1160 p = skip_whites (p); 1161 1162 if (*p == 0 || *p == '\n' || *p == '\r') 1163 { 1164 input_line_pointer = p; 1165 return 0; 1166 } 1167 1168 if (*p == '*' && (opmode & (M6811_OP_DIRECT | M6811_OP_IND16))) 1169 { 1170 mode = M6811_OP_DIRECT; 1171 p++; 1172 } 1173 else if (*p == '#') 1174 { 1175 if (!(opmode & (M6811_OP_IMM8 | M6811_OP_IMM16 | M6811_OP_BITMASK))) 1176 { 1177 as_bad (_("Immediate operand is not allowed for operand %d."), 1178 which); 1179 return -1; 1180 } 1181 1182 mode = M6811_OP_IMM16; 1183 p++; 1184 if (strncmp (p, "%hi", 3) == 0) 1185 { 1186 p += 3; 1187 mode |= M6811_OP_HIGH_ADDR; 1188 } 1189 else if (strncmp (p, "%lo", 3) == 0) 1190 { 1191 p += 3; 1192 mode |= M6811_OP_LOW_ADDR; 1193 } 1194 /* %page modifier is used to obtain only the page number 1195 of the address of a function. */ 1196 else if (strncmp (p, "%page", 5) == 0) 1197 { 1198 p += 5; 1199 mode |= M6811_OP_PAGE_ADDR; 1200 } 1201 1202 /* %addr modifier is used to obtain the physical address part 1203 of the function (16-bit). For 68HC12 the function will be 1204 mapped in the 16K window at 0x8000 and the value will be 1205 within that window (although the function address may not fit 1206 in 16-bit). See bfd/elf32-m68hc12.c for the translation. */ 1207 else if (strncmp (p, "%addr", 5) == 0) 1208 { 1209 p += 5; 1210 mode |= M6811_OP_CALL_ADDR; 1211 } 1212 } 1213 else if (*p == '.' && (p[1] == '+' || p[1] == '-')) 1214 { 1215 p++; 1216 mode = M6811_OP_JUMP_REL; 1217 } 1218 else if (*p == '[') 1219 { 1220 if (current_architecture & cpu6811) 1221 as_bad (_("Indirect indexed addressing is not valid for 68HC11.")); 1222 1223 p++; 1224 mode = M6812_OP_D_IDX; 1225 p = skip_whites (p); 1226 } 1227 else if (*p == ',') /* Special handling of ,x and ,y. */ 1228 { 1229 p++; 1230 input_line_pointer = p; 1231 1232 reg = register_name (); 1233 if (reg != REG_NONE) 1234 { 1235 oper->reg1 = reg; 1236 oper->exp.X_op = O_constant; 1237 oper->exp.X_add_number = 0; 1238 oper->mode = M6812_OP_IDX; 1239 return 1; 1240 } 1241 as_bad (_("Spurious `,' or bad indirect register addressing mode.")); 1242 return -1; 1243 } 1244 /* Handle 68HC12 page specification in 'call foo,%page(bar)'. */ 1245 else if ((opmode & M6812_OP_PAGE) && strncmp (p, "%page", 5) == 0) 1246 { 1247 p += 5; 1248 mode = M6811_OP_PAGE_ADDR | M6812_OP_PAGE | M6811_OP_IND16; 1249 } 1250 input_line_pointer = p; 1251 1252 if (mode == M6811_OP_NONE || mode == M6812_OP_D_IDX) 1253 reg = register_name (); 1254 else 1255 reg = REG_NONE; 1256 1257 if (reg != REG_NONE) 1258 { 1259 p = skip_whites (input_line_pointer); 1260 if (*p == ']' && mode == M6812_OP_D_IDX) 1261 { 1262 as_bad 1263 (_("Missing second register or offset for indexed-indirect mode.")); 1264 return -1; 1265 } 1266 1267 oper->reg1 = reg; 1268 oper->mode = mode | M6812_OP_REG; 1269 if (*p != ',') 1270 { 1271 if (mode == M6812_OP_D_IDX) 1272 { 1273 as_bad (_("Missing second register for indexed-indirect mode.")); 1274 return -1; 1275 } 1276 return 1; 1277 } 1278 1279 p++; 1280 input_line_pointer = p; 1281 reg = register_name (); 1282 if (reg != REG_NONE) 1283 { 1284 p = skip_whites (input_line_pointer); 1285 if (mode == M6812_OP_D_IDX) 1286 { 1287 if (*p != ']') 1288 { 1289 as_bad (_("Missing `]' to close indexed-indirect mode.")); 1290 return -1; 1291 } 1292 p++; 1293 oper->mode = M6812_OP_D_IDX; 1294 } 1295 input_line_pointer = p; 1296 1297 oper->reg2 = reg; 1298 return 1; 1299 } 1300 return 1; 1301 } 1302 1303 /* In MRI mode, isolate the operand because we can't distinguish 1304 operands from comments. */ 1305 if (flag_mri) 1306 { 1307 char c = 0; 1308 1309 p = skip_whites (p); 1310 while (*p && *p != ' ' && *p != '\t') 1311 p++; 1312 1313 if (*p) 1314 { 1315 c = *p; 1316 *p = 0; 1317 } 1318 1319 /* Parse as an expression. */ 1320 expression (&oper->exp); 1321 1322 if (c) 1323 { 1324 *p = c; 1325 } 1326 } 1327 else 1328 { 1329 expression (&oper->exp); 1330 } 1331 1332 if (oper->exp.X_op == O_illegal) 1333 { 1334 as_bad (_("Illegal operand.")); 1335 return -1; 1336 } 1337 else if (oper->exp.X_op == O_absent) 1338 { 1339 as_bad (_("Missing operand.")); 1340 return -1; 1341 } 1342 1343 p = input_line_pointer; 1344 1345 if (mode == M6811_OP_NONE || mode == M6811_OP_DIRECT 1346 || mode == M6812_OP_D_IDX) 1347 { 1348 p = skip_whites (input_line_pointer); 1349 1350 if (*p == ',') 1351 { 1352 int possible_mode = M6811_OP_NONE; 1353 char *old_input_line; 1354 1355 old_input_line = p; 1356 p++; 1357 1358 /* 68HC12 pre increment or decrement. */ 1359 if (mode == M6811_OP_NONE) 1360 { 1361 if (*p == '-') 1362 { 1363 possible_mode = M6812_PRE_DEC; 1364 p++; 1365 } 1366 else if (*p == '+') 1367 { 1368 possible_mode = M6812_PRE_INC; 1369 p++; 1370 } 1371 p = skip_whites (p); 1372 } 1373 input_line_pointer = p; 1374 reg = register_name (); 1375 1376 /* Backtrack if we have a valid constant expression and 1377 it does not correspond to the offset of the 68HC12 indexed 1378 addressing mode (as in N,x). */ 1379 if (reg == REG_NONE && mode == M6811_OP_NONE 1380 && possible_mode != M6811_OP_NONE) 1381 { 1382 oper->mode = M6811_OP_IND16 | M6811_OP_JUMP_REL; 1383 input_line_pointer = skip_whites (old_input_line); 1384 return 1; 1385 } 1386 1387 if (possible_mode != M6811_OP_NONE) 1388 mode = possible_mode; 1389 1390 if ((current_architecture & cpu6811) 1391 && possible_mode != M6811_OP_NONE) 1392 as_bad (_("Pre-increment mode is not valid for 68HC11")); 1393 /* Backtrack. */ 1394 if (which == 0 && opmode & M6812_OP_IDX_P2 1395 && reg != REG_X && reg != REG_Y 1396 && reg != REG_PC && reg != REG_SP) 1397 { 1398 reg = REG_NONE; 1399 input_line_pointer = p; 1400 } 1401 1402 if (reg == REG_NONE && mode != M6811_OP_DIRECT 1403 && !(mode == M6811_OP_NONE && opmode & M6811_OP_IND16)) 1404 { 1405 as_bad (_("Wrong register in register indirect mode.")); 1406 return -1; 1407 } 1408 if (mode == M6812_OP_D_IDX) 1409 { 1410 p = skip_whites (input_line_pointer); 1411 if (*p++ != ']') 1412 { 1413 as_bad (_("Missing `]' to close register indirect operand.")); 1414 return -1; 1415 } 1416 input_line_pointer = p; 1417 oper->reg1 = reg; 1418 oper->mode = M6812_OP_D_IDX_2; 1419 return 1; 1420 } 1421 if (reg != REG_NONE) 1422 { 1423 oper->reg1 = reg; 1424 if (mode == M6811_OP_NONE) 1425 { 1426 p = input_line_pointer; 1427 if (*p == '-') 1428 { 1429 mode = M6812_POST_DEC; 1430 p++; 1431 if (current_architecture & cpu6811) 1432 as_bad 1433 (_("Post-decrement mode is not valid for 68HC11.")); 1434 } 1435 else if (*p == '+') 1436 { 1437 mode = M6812_POST_INC; 1438 p++; 1439 if (current_architecture & cpu6811) 1440 as_bad 1441 (_("Post-increment mode is not valid for 68HC11.")); 1442 } 1443 else 1444 mode = M6812_OP_IDX; 1445 1446 input_line_pointer = p; 1447 } 1448 else 1449 mode |= M6812_OP_IDX; 1450 1451 oper->mode = mode; 1452 return 1; 1453 } 1454 input_line_pointer = old_input_line; 1455 } 1456 1457 if (mode == M6812_OP_D_IDX_2) 1458 { 1459 as_bad (_("Invalid indexed indirect mode.")); 1460 return -1; 1461 } 1462 } 1463 1464 /* If the mode is not known until now, this is either a label 1465 or an indirect address. */ 1466 if (mode == M6811_OP_NONE) 1467 mode = M6811_OP_IND16 | M6811_OP_JUMP_REL; 1468 1469 p = input_line_pointer; 1470 while (*p == ' ' || *p == '\t') 1471 p++; 1472 input_line_pointer = p; 1473 oper->mode = mode; 1474 1475 return 1; 1476 } 1477 1478 #define M6812_AUTO_INC_DEC (M6812_PRE_INC | M6812_PRE_DEC \ 1479 | M6812_POST_INC | M6812_POST_DEC) 1480 1481 /* Checks that the number 'num' fits for a given mode. */ 1482 static int 1483 check_range (long num, int mode) 1484 { 1485 if (current_architecture == cpuxgate) 1486 { 1487 switch (mode) 1488 { 1489 case M68XG_OP_IMM3: 1490 return (num >= 0 && num <= 7) ? 1 : 0; 1491 1492 case M68XG_OP_R_IMM4: 1493 return (num >= 0 && num <= 15) ? 1 : 0; 1494 1495 case M68XG_OP_R_R_OFFS5: 1496 return (num >= 0 && num <= 31) ? 1 : 0; 1497 1498 case M68XG_OP_R_IMM8: 1499 return (num >= 0 && num <= 255) ? 1 : 0; 1500 1501 case M68XG_OP_R_IMM16: 1502 return (num >= 0 && num <= 65535) ? 1 : 0; 1503 1504 case M68XG_OP_B_MARKER: 1505 return (num >= -512 && num <= 511) ? 1 : 0; 1506 1507 case M68XG_OP_BRA_MARKER: 1508 return (num >= -1024 && num <= 1023) ? 1 : 0; 1509 1510 default: 1511 return 0; 1512 } 1513 } 1514 else 1515 { 1516 /* Auto increment and decrement are ok for [-8..8] without 0. */ 1517 if (mode & M6812_AUTO_INC_DEC) 1518 return (num != 0 && num <= 8 && num >= -8); 1519 1520 /* The 68HC12 supports 5, 9 and 16-bit offsets. */ 1521 if (mode & (M6812_INDEXED_IND | M6812_INDEXED | M6812_OP_IDX)) 1522 mode = M6811_OP_IND16; 1523 1524 if (mode & M6812_OP_JUMP_REL16) 1525 mode = M6811_OP_IND16; 1526 1527 mode &= ~M6811_OP_BRANCH; 1528 switch (mode) 1529 { 1530 case M6811_OP_IX: 1531 case M6811_OP_IY: 1532 case M6811_OP_DIRECT: 1533 return (num >= 0 && num <= 255) ? 1 : 0; 1534 1535 case M6811_OP_BITMASK: 1536 case M6811_OP_IMM8: 1537 case M6812_OP_PAGE: 1538 return (((num & 0xFFFFFF00) == 0) || ((num & 0xFFFFFF00) == 0xFFFFFF00)) 1539 ? 1 : 0; 1540 1541 case M6811_OP_JUMP_REL: 1542 return (num >= -128 && num <= 127) ? 1 : 0; 1543 1544 case M6811_OP_IND16: 1545 case M6811_OP_IND16 | M6812_OP_PAGE: 1546 case M6811_OP_IMM16: 1547 return (((num & 0xFFFF0000) == 0) || ((num & 0xFFFF0000) == 0xFFFF0000)) 1548 ? 1 : 0; 1549 1550 case M6812_OP_IBCC_MARKER: 1551 case M6812_OP_TBCC_MARKER: 1552 case M6812_OP_DBCC_MARKER: 1553 return (num >= -256 && num <= 255) ? 1 : 0; 1554 1555 case M6812_OP_TRAP_ID: 1556 return ((num >= 0x30 && num <= 0x39) 1557 || (num >= 0x40 && num <= 0x0ff)) ? 1 : 0; 1558 1559 default: 1560 return 0; 1561 } 1562 } 1563 } 1564 1565 /* Gas fixup generation. */ 1567 1568 /* Put a 1 byte expression described by 'oper'. If this expression contains 1569 unresolved symbols, generate an 8-bit fixup. */ 1570 static void 1571 fixup8 (expressionS *oper, int mode, int opmode) 1572 { 1573 char *f; 1574 1575 f = frag_more (1); 1576 1577 if (oper->X_op == O_constant) 1578 { 1579 if (mode & M6812_OP_TRAP_ID 1580 && !check_range (oper->X_add_number, M6812_OP_TRAP_ID)) 1581 { 1582 static char trap_id_warn_once = 0; 1583 1584 as_bad (_("Trap id `%ld' is out of range."), oper->X_add_number); 1585 if (trap_id_warn_once == 0) 1586 { 1587 trap_id_warn_once = 1; 1588 as_bad (_("Trap id must be within [0x30..0x39] or [0x40..0xff].")); 1589 } 1590 } 1591 1592 if (!(mode & M6812_OP_TRAP_ID) 1593 && !check_range (oper->X_add_number, mode)) 1594 { 1595 as_bad (_("Operand out of 8-bit range: `%ld'."), oper->X_add_number); 1596 } 1597 number_to_chars_bigendian (f, oper->X_add_number & 0x0FF, 1); 1598 } 1599 else if (oper->X_op != O_register) 1600 { 1601 if (mode & M6812_OP_TRAP_ID) 1602 as_bad (_("The trap id must be a constant.")); 1603 1604 if (mode == M6811_OP_JUMP_REL) 1605 { 1606 fix_new_exp (frag_now, f - frag_now->fr_literal, 1, 1607 oper, TRUE, BFD_RELOC_8_PCREL); 1608 } 1609 else 1610 { 1611 fixS *fixp; 1612 bfd_reloc_code_real_type reloc; 1613 1614 /* Now create an 8-bit fixup. If there was some %hi, %lo 1615 or %page modifier, generate the reloc accordingly. */ 1616 if (opmode & M6811_OP_HIGH_ADDR) 1617 reloc = BFD_RELOC_M68HC11_HI8; 1618 else if (opmode & M6811_OP_LOW_ADDR) 1619 reloc = BFD_RELOC_M68HC11_LO8; 1620 else if (opmode & M6811_OP_PAGE_ADDR) 1621 reloc = BFD_RELOC_M68HC11_PAGE; 1622 else 1623 reloc = BFD_RELOC_8; 1624 1625 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1, 1626 oper, FALSE, reloc); 1627 if (reloc != BFD_RELOC_8) 1628 fixp->fx_no_overflow = 1; 1629 } 1630 number_to_chars_bigendian (f, 0, 1); 1631 } 1632 else 1633 { 1634 as_fatal (_("Operand `%x' not recognized in fixup8."), oper->X_op); 1635 } 1636 } 1637 1638 /* Put a 2 byte expression described by 'oper'. If this expression contains 1639 unresolved symbols, generate a 16-bit fixup. */ 1640 static void 1641 fixup16 (expressionS *oper, int mode, int opmode ATTRIBUTE_UNUSED) 1642 { 1643 char *f; 1644 1645 f = frag_more (2); 1646 1647 if (oper->X_op == O_constant) 1648 { 1649 if (!check_range (oper->X_add_number, mode)) 1650 { 1651 as_bad (_("Operand out of 16-bit range: `%ld'."), 1652 oper->X_add_number); 1653 } 1654 number_to_chars_bigendian (f, oper->X_add_number & 0x0FFFF, 2); 1655 } 1656 else if (oper->X_op != O_register) 1657 { 1658 fixS *fixp; 1659 bfd_reloc_code_real_type reloc; 1660 1661 if ((opmode & M6811_OP_CALL_ADDR) && (mode & M6811_OP_IMM16)) 1662 reloc = BFD_RELOC_M68HC11_LO16; 1663 else if (mode & M6812_OP_JUMP_REL16) 1664 reloc = BFD_RELOC_16_PCREL; 1665 else if (mode & M6812_OP_PAGE) 1666 reloc = BFD_RELOC_M68HC11_LO16; 1667 else 1668 reloc = BFD_RELOC_16; 1669 1670 /* Now create a 16-bit fixup. */ 1671 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 2, 1672 oper, 1673 reloc == BFD_RELOC_16_PCREL, 1674 reloc); 1675 number_to_chars_bigendian (f, 0, 2); 1676 1677 if (reloc == BFD_RELOC_M68HC11_LO16) 1678 fixp->fx_no_overflow = 1; 1679 } 1680 else 1681 { 1682 as_fatal (_("Operand `%x' not recognized in fixup16."), oper->X_op); 1683 } 1684 } 1685 1686 /* Put a 3 byte expression described by 'oper'. If this expression contains 1687 unresolved symbols, generate a 24-bit fixup. */ 1688 static void 1689 fixup24 (expressionS *oper, int mode, int opmode ATTRIBUTE_UNUSED) 1690 { 1691 char *f; 1692 1693 f = frag_more (3); 1694 1695 if (oper->X_op == O_constant) 1696 { 1697 if (!check_range (oper->X_add_number, mode)) 1698 { 1699 as_bad (_("Operand out of 16-bit range: `%ld'."), 1700 oper->X_add_number); 1701 } 1702 number_to_chars_bigendian (f, oper->X_add_number & 0x0FFFFFF, 3); 1703 } 1704 else if (oper->X_op != O_register) 1705 { 1706 /* Now create a 24-bit fixup. */ 1707 fix_new_exp (frag_now, f - frag_now->fr_literal, 3, 1708 oper, FALSE, BFD_RELOC_M68HC11_24); 1709 number_to_chars_bigendian (f, 0, 3); 1710 } 1711 else 1712 { 1713 as_fatal (_("Operand `%x' not recognized in fixup16."), oper->X_op); 1714 } 1715 } 1716 1717 /* XGATE Put a 1 byte expression described by 'oper'. If this expression 1718 containts unresolved symbols, generate an 8-bit fixup. */ 1719 static void 1720 fixup8_xg (expressionS *oper, int mode, int opmode) 1721 { 1722 char *f; 1723 1724 f = frag_more (1); 1725 1726 if (oper->X_op == O_constant) 1727 { 1728 fixS *fixp; 1729 bfd_reloc_code_real_type reloc; 1730 1731 if ((opmode & M6811_OP_HIGH_ADDR) || (opmode & M6811_OP_LOW_ADDR)) 1732 { 1733 if (opmode & M6811_OP_HIGH_ADDR) 1734 reloc = BFD_RELOC_M68HC11_HI8; 1735 else 1736 reloc = BFD_RELOC_M68HC11_LO8; 1737 1738 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1, 1739 oper, FALSE, reloc); 1740 fixp->fx_no_overflow = 1; 1741 number_to_chars_bigendian (f, 0, 1); 1742 } 1743 else 1744 { 1745 if (!(check_range (oper->X_add_number, mode))) 1746 as_bad (_("Operand out of 8-bit range: `%ld'."), 1747 oper->X_add_number); 1748 number_to_chars_bigendian (f, oper->X_add_number & 0x0FF, 1); 1749 } 1750 } 1751 else if (oper->X_op != O_register) 1752 { 1753 if (mode == M68XG_OP_REL9) 1754 { 1755 /* Future improvement: 1756 This fixup/reloc isn't adding on constants to symbols. */ 1757 fix_new_exp (frag_now, f - frag_now->fr_literal -1, 2, 1758 oper, TRUE, BFD_RELOC_M68HC12_9_PCREL); 1759 } 1760 else if (mode == M68XG_OP_REL10) 1761 { 1762 /* Future improvement: 1763 This fixup/reloc isn't adding on constants to symbols. */ 1764 fix_new_exp (frag_now, f - frag_now->fr_literal -1, 2, 1765 oper, TRUE, BFD_RELOC_M68HC12_10_PCREL); 1766 } 1767 else 1768 { 1769 fixS *fixp; 1770 bfd_reloc_code_real_type reloc; 1771 1772 /* Now create an 8-bit fixup. If there was some %hi, %lo 1773 modifier, generate the reloc accordingly. */ 1774 if (opmode & M6811_OP_HIGH_ADDR) 1775 reloc = BFD_RELOC_M68HC11_HI8; 1776 else if (opmode & M6811_OP_LOW_ADDR) 1777 reloc = BFD_RELOC_M68HC11_LO8; 1778 else 1779 reloc = BFD_RELOC_8; 1780 1781 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1, 1782 oper, FALSE, reloc); 1783 if (reloc != BFD_RELOC_8) 1784 fixp->fx_no_overflow = 1; 1785 } 1786 number_to_chars_bigendian (f, 0, 1); 1787 } 1788 else 1789 as_fatal (_("Operand `%x' not recognized in fixup8."), oper->X_op); 1790 } 1791 1792 /* 68HC11 and 68HC12 code generation. */ 1794 1795 /* Translate the short branch/bsr instruction into a long branch. */ 1796 1797 static unsigned char 1798 convert_branch (unsigned char code) 1799 { 1800 if (IS_OPCODE (code, M6812_BSR)) 1801 return M6812_JSR; 1802 else if (IS_OPCODE (code, M6811_BSR)) 1803 return M6811_JSR; 1804 else if (IS_OPCODE (code, M6811_BRA)) 1805 return (current_architecture & cpu6812) ? M6812_JMP : M6811_JMP; 1806 else 1807 as_fatal (_("Unexpected branch conversion with `%x'"), code); 1808 1809 /* Keep gcc happy. */ 1810 return M6811_JSR; 1811 } 1812 1813 /* Start a new insn that contains at least 'size' bytes. Record the 1814 line information of that insn in the dwarf2 debug sections. */ 1815 static char * 1816 m68hc11_new_insn (int size) 1817 { 1818 char *f; 1819 1820 f = frag_more (size); 1821 1822 dwarf2_emit_insn (size); 1823 1824 return f; 1825 } 1826 1827 /* Builds a jump instruction (bra, bcc, bsr). */ 1828 static void 1829 build_jump_insn (struct m68hc11_opcode *opcode, operand operands[], 1830 int nb_operands, int jmp_mode) 1831 { 1832 unsigned char code; 1833 char *f; 1834 unsigned long n; 1835 1836 /* The relative branch conversion is not supported for 1837 brclr and brset. */ 1838 gas_assert ((opcode->format & M6811_OP_BITMASK) == 0); 1839 gas_assert (nb_operands == 1); 1840 gas_assert (operands[0].reg1 == REG_NONE && operands[0].reg2 == REG_NONE); 1841 1842 code = opcode->opcode; 1843 1844 n = operands[0].exp.X_add_number; 1845 1846 /* Turn into a long branch: 1847 - when force long branch option (and not for jbcc pseudos), 1848 - when jbcc and the constant is out of -128..127 range, 1849 - when branch optimization is allowed and branch out of range. */ 1850 if ((jmp_mode == 0 && flag_force_long_jumps) 1851 || (operands[0].exp.X_op == O_constant 1852 && (!check_range (n, opcode->format) && 1853 (jmp_mode == 1 || flag_fixed_branches == 0)))) 1854 { 1855 fix_new (frag_now, frag_now_fix (), 0, 1856 &abs_symbol, 0, 1, BFD_RELOC_M68HC11_RL_JUMP); 1857 1858 if (code == M6811_BSR || code == M6811_BRA || code == M6812_BSR) 1859 { 1860 code = convert_branch (code); 1861 1862 f = m68hc11_new_insn (1); 1863 number_to_chars_bigendian (f, code, 1); 1864 } 1865 else if (current_architecture & cpu6812) 1866 { 1867 /* 68HC12: translate the bcc into a lbcc. */ 1868 f = m68hc11_new_insn (2); 1869 number_to_chars_bigendian (f, M6811_OPCODE_PAGE2, 1); 1870 number_to_chars_bigendian (f + 1, code, 1); 1871 fixup16 (&operands[0].exp, M6812_OP_JUMP_REL16, 1872 M6812_OP_JUMP_REL16); 1873 return; 1874 } 1875 else 1876 { 1877 /* 68HC11: translate the bcc into b!cc +3; jmp <L>. */ 1878 f = m68hc11_new_insn (3); 1879 code ^= 1; 1880 number_to_chars_bigendian (f, code, 1); 1881 number_to_chars_bigendian (f + 1, 3, 1); 1882 number_to_chars_bigendian (f + 2, M6811_JMP, 1); 1883 } 1884 fixup16 (&operands[0].exp, M6811_OP_IND16, M6811_OP_IND16); 1885 return; 1886 } 1887 1888 /* Branch with a constant that must fit in 8-bits. */ 1889 if (operands[0].exp.X_op == O_constant) 1890 { 1891 if (!check_range (n, opcode->format)) 1892 { 1893 as_bad (_("Operand out of range for a relative branch: `%ld'"), 1894 n); 1895 } 1896 else if (opcode->format & M6812_OP_JUMP_REL16) 1897 { 1898 f = m68hc11_new_insn (4); 1899 number_to_chars_bigendian (f, M6811_OPCODE_PAGE2, 1); 1900 number_to_chars_bigendian (f + 1, code, 1); 1901 number_to_chars_bigendian (f + 2, n & 0x0ffff, 2); 1902 } 1903 else 1904 { 1905 f = m68hc11_new_insn (2); 1906 number_to_chars_bigendian (f, code, 1); 1907 number_to_chars_bigendian (f + 1, n & 0x0FF, 1); 1908 } 1909 } 1910 else if (opcode->format & M6812_OP_JUMP_REL16) 1911 { 1912 fix_new (frag_now, frag_now_fix (), 0, 1913 &abs_symbol, 0, 1, BFD_RELOC_M68HC11_RL_JUMP); 1914 1915 f = m68hc11_new_insn (2); 1916 number_to_chars_bigendian (f, M6811_OPCODE_PAGE2, 1); 1917 number_to_chars_bigendian (f + 1, code, 1); 1918 fixup16 (&operands[0].exp, M6812_OP_JUMP_REL16, M6812_OP_JUMP_REL16); 1919 } 1920 else 1921 { 1922 char *op; 1923 1924 fix_new (frag_now, frag_now_fix (), 0, 1925 &abs_symbol, 0, 1, BFD_RELOC_M68HC11_RL_JUMP); 1926 1927 /* Branch offset must fit in 8-bits, don't do some relax. */ 1928 if (jmp_mode == 0 && flag_fixed_branches) 1929 { 1930 op = m68hc11_new_insn (1); 1931 number_to_chars_bigendian (op, code, 1); 1932 fixup8 (&operands[0].exp, M6811_OP_JUMP_REL, M6811_OP_JUMP_REL); 1933 } 1934 1935 /* bra/bsr made be changed into jmp/jsr. */ 1936 else if (code == M6811_BSR || code == M6811_BRA || code == M6812_BSR) 1937 { 1938 /* Allocate worst case storage. */ 1939 op = m68hc11_new_insn (3); 1940 number_to_chars_bigendian (op, code, 1); 1941 number_to_chars_bigendian (op + 1, 0, 1); 1942 frag_variant (rs_machine_dependent, 1, 1, 1943 ENCODE_RELAX (STATE_PC_RELATIVE, STATE_UNDF), 1944 operands[0].exp.X_add_symbol, (offsetT) n, 1945 op); 1946 } 1947 else if (current_architecture & cpu6812) 1948 { 1949 op = m68hc11_new_insn (2); 1950 number_to_chars_bigendian (op, code, 1); 1951 number_to_chars_bigendian (op + 1, 0, 1); 1952 frag_var (rs_machine_dependent, 2, 2, 1953 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_UNDF), 1954 operands[0].exp.X_add_symbol, (offsetT) n, op); 1955 } 1956 else 1957 { 1958 op = m68hc11_new_insn (2); 1959 number_to_chars_bigendian (op, code, 1); 1960 number_to_chars_bigendian (op + 1, 0, 1); 1961 frag_var (rs_machine_dependent, 3, 3, 1962 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_UNDF), 1963 operands[0].exp.X_add_symbol, (offsetT) n, op); 1964 } 1965 } 1966 } 1967 1968 /* Builds a dbne/dbeq/tbne/tbeq instruction. */ 1969 static void 1970 build_dbranch_insn (struct m68hc11_opcode *opcode, operand operands[], 1971 int nb_operands, int jmp_mode) 1972 { 1973 unsigned char code; 1974 char *f; 1975 unsigned long n; 1976 1977 /* The relative branch conversion is not supported for 1978 brclr and brset. */ 1979 gas_assert ((opcode->format & M6811_OP_BITMASK) == 0); 1980 gas_assert (nb_operands == 2); 1981 gas_assert (operands[0].reg1 != REG_NONE); 1982 1983 code = opcode->opcode & 0x0FF; 1984 1985 f = m68hc11_new_insn (1); 1986 number_to_chars_bigendian (f, code, 1); 1987 1988 n = operands[1].exp.X_add_number; 1989 code = operands[0].reg1; 1990 1991 if (operands[0].reg1 == REG_NONE || operands[0].reg1 == REG_CCR 1992 || operands[0].reg1 == REG_PC) 1993 as_bad (_("Invalid register for dbcc/tbcc instruction.")); 1994 1995 if (opcode->format & M6812_OP_IBCC_MARKER) 1996 code |= 0x80; 1997 else if (opcode->format & M6812_OP_TBCC_MARKER) 1998 code |= 0x40; 1999 2000 if (!(opcode->format & M6812_OP_EQ_MARKER)) 2001 code |= 0x20; 2002 2003 /* Turn into a long branch: 2004 - when force long branch option (and not for jbcc pseudos), 2005 - when jdbcc and the constant is out of -256..255 range, 2006 - when branch optimization is allowed and branch out of range. */ 2007 if ((jmp_mode == 0 && flag_force_long_jumps) 2008 || (operands[1].exp.X_op == O_constant 2009 && (!check_range (n, M6812_OP_IBCC_MARKER) && 2010 (jmp_mode == 1 || flag_fixed_branches == 0)))) 2011 { 2012 f = frag_more (2); 2013 code ^= 0x20; 2014 number_to_chars_bigendian (f, code, 1); 2015 number_to_chars_bigendian (f + 1, M6812_JMP, 1); 2016 fixup16 (&operands[0].exp, M6811_OP_IND16, M6811_OP_IND16); 2017 return; 2018 } 2019 2020 /* Branch with a constant that must fit in 9-bits. */ 2021 if (operands[1].exp.X_op == O_constant) 2022 { 2023 if (!check_range (n, M6812_OP_IBCC_MARKER)) 2024 { 2025 as_bad (_("Operand out of range for a relative branch: `%ld'"), 2026 n); 2027 } 2028 else 2029 { 2030 if ((long) n < 0) 2031 code |= 0x10; 2032 2033 f = frag_more (2); 2034 number_to_chars_bigendian (f, code, 1); 2035 number_to_chars_bigendian (f + 1, n & 0x0FF, 1); 2036 } 2037 } 2038 else 2039 { 2040 /* Branch offset must fit in 8-bits, don't do some relax. */ 2041 if (jmp_mode == 0 && flag_fixed_branches) 2042 { 2043 fixup8 (&operands[0].exp, M6811_OP_JUMP_REL, M6811_OP_JUMP_REL); 2044 } 2045 2046 else 2047 { 2048 f = frag_more (2); 2049 number_to_chars_bigendian (f, code, 1); 2050 number_to_chars_bigendian (f + 1, 0, 1); 2051 frag_var (rs_machine_dependent, 3, 3, 2052 ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_UNDF), 2053 operands[1].exp.X_add_symbol, (offsetT) n, f); 2054 } 2055 } 2056 } 2057 2058 #define OP_EXTENDED (M6811_OP_PAGE2 | M6811_OP_PAGE3 | M6811_OP_PAGE4) 2059 2060 /* Assemble the post index byte for 68HC12 extended addressing modes. */ 2061 2062 static int 2063 build_indexed_byte (operand *op, int format ATTRIBUTE_UNUSED, int move_insn) 2064 { 2065 unsigned char byte = 0; 2066 char *f; 2067 int mode; 2068 long val; 2069 2070 val = op->exp.X_add_number; 2071 mode = op->mode; 2072 if (mode & M6812_AUTO_INC_DEC) 2073 { 2074 byte = 0x20; 2075 if (mode & (M6812_POST_INC | M6812_POST_DEC)) 2076 byte |= 0x10; 2077 2078 if (op->exp.X_op == O_constant) 2079 { 2080 if (!check_range (val, mode)) 2081 as_bad (_("Increment/decrement value is out of range: `%ld'."), 2082 val); 2083 2084 if (mode & (M6812_POST_INC | M6812_PRE_INC)) 2085 byte |= (val - 1) & 0x07; 2086 else 2087 byte |= (8 - ((val) & 7)) | 0x8; 2088 } 2089 2090 switch (op->reg1) 2091 { 2092 case REG_NONE: 2093 as_fatal (_("Expecting a register.")); 2094 2095 case REG_X: 2096 byte |= 0; 2097 break; 2098 2099 case REG_Y: 2100 byte |= 0x40; 2101 break; 2102 2103 case REG_SP: 2104 byte |= 0x80; 2105 break; 2106 2107 default: 2108 as_bad (_("Invalid register for post/pre increment.")); 2109 break; 2110 } 2111 2112 f = frag_more (1); 2113 number_to_chars_bigendian (f, byte, 1); 2114 return 1; 2115 } 2116 2117 if (mode & (M6812_OP_IDX | M6812_OP_D_IDX_2)) 2118 { 2119 switch (op->reg1) 2120 { 2121 case REG_X: 2122 byte = 0; 2123 break; 2124 2125 case REG_Y: 2126 byte = 1; 2127 break; 2128 2129 case REG_SP: 2130 byte = 2; 2131 break; 2132 2133 case REG_PC: 2134 byte = 3; 2135 break; 2136 2137 default: 2138 as_bad (_("Invalid register.")); 2139 break; 2140 } 2141 2142 if (op->exp.X_op == O_constant) 2143 { 2144 if (!check_range (val, M6812_OP_IDX)) 2145 as_bad (_("Offset out of 16-bit range: %ld."), val); 2146 2147 if (move_insn && !(val >= -16 && val <= 15) 2148 && ((!(mode & M6812_OP_IDX) && !(mode & M6812_OP_D_IDX_2)) 2149 || !(current_architecture & cpu9s12x))) 2150 { 2151 as_bad (_("Offset out of 5-bit range for movw/movb insn: %ld."), 2152 val); 2153 return -1; 2154 } 2155 2156 if (val >= -16 && val <= 15 && !(mode & M6812_OP_D_IDX_2)) 2157 { 2158 byte = byte << 6; 2159 byte |= val & 0x1f; 2160 f = frag_more (1); 2161 number_to_chars_bigendian (f, byte, 1); 2162 return 1; 2163 } 2164 else if (val >= -256 && val <= 255 && !(mode & M6812_OP_D_IDX_2)) 2165 { 2166 byte = byte << 3; 2167 byte |= 0xe0; 2168 if (val < 0) 2169 byte |= 0x1; 2170 f = frag_more (2); 2171 number_to_chars_bigendian (f, byte, 1); 2172 number_to_chars_bigendian (f + 1, val & 0x0FF, 1); 2173 return 2; 2174 } 2175 else 2176 { 2177 byte = byte << 3; 2178 if (mode & M6812_OP_D_IDX_2) 2179 byte |= 0xe3; 2180 else 2181 byte |= 0xe2; 2182 2183 f = frag_more (3); 2184 number_to_chars_bigendian (f, byte, 1); 2185 number_to_chars_bigendian (f + 1, val & 0x0FFFF, 2); 2186 return 3; 2187 } 2188 } 2189 2190 if (mode & M6812_OP_D_IDX_2) 2191 { 2192 byte = (byte << 3) | 0xe3; 2193 f = frag_more (1); 2194 number_to_chars_bigendian (f, byte, 1); 2195 2196 fixup16 (&op->exp, 0, 0); 2197 } 2198 else if (op->reg1 != REG_PC) 2199 { 2200 symbolS *sym; 2201 offsetT off; 2202 2203 f = frag_more (1); 2204 number_to_chars_bigendian (f, byte, 1); 2205 sym = op->exp.X_add_symbol; 2206 off = op->exp.X_add_number; 2207 if (op->exp.X_op != O_symbol) 2208 { 2209 sym = make_expr_symbol (&op->exp); 2210 off = 0; 2211 } 2212 2213 /* movb/movw cannot be relaxed. */ 2214 if (move_insn) 2215 { 2216 if ((mode & M6812_OP_IDX) && (current_architecture & cpu9s12x)) 2217 { 2218 /* Must treat as a 16bit relocate as size of final result is unknown. */ 2219 2220 byte <<= 3; 2221 byte |= 0xe2; 2222 number_to_chars_bigendian (f, byte, 1); 2223 f = frag_more (2); 2224 fix_new (frag_now, f - frag_now->fr_literal, 2, 2225 sym, off, 0, BFD_RELOC_M68HC12_16B); 2226 return 1; 2227 } 2228 else 2229 { 2230 /* Non-S12X will fail at relocate stage if offset out of range. */ 2231 byte <<= 6; 2232 number_to_chars_bigendian (f, byte, 1); 2233 fix_new (frag_now, f - frag_now->fr_literal, 1, 2234 sym, off, 0, BFD_RELOC_M68HC12_5B); 2235 return 1; 2236 } 2237 } 2238 else 2239 { 2240 number_to_chars_bigendian (f, byte, 1); 2241 frag_var (rs_machine_dependent, 2, 2, 2242 ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_UNDF), 2243 sym, off, f); 2244 } 2245 } 2246 else 2247 { 2248 f = frag_more (1); 2249 2250 /* movb/movw cannot be relaxed. */ 2251 if (move_insn) 2252 { 2253 byte <<= 6; 2254 number_to_chars_bigendian (f, byte, 1); 2255 fix_new (frag_now, f - frag_now->fr_literal, 1, 2256 op->exp.X_add_symbol, op->exp.X_add_number, 0, BFD_RELOC_M68HC12_5B); 2257 return 1; 2258 } 2259 else 2260 { 2261 number_to_chars_bigendian (f, byte, 1); 2262 frag_var (rs_machine_dependent, 2, 2, 2263 ENCODE_RELAX (STATE_INDEXED_PCREL, STATE_UNDF), 2264 op->exp.X_add_symbol, 2265 op->exp.X_add_number, f); 2266 } 2267 } 2268 return 3; 2269 } 2270 2271 if (mode & (M6812_OP_REG | M6812_OP_D_IDX)) 2272 { 2273 if (mode & M6812_OP_D_IDX) 2274 { 2275 if (op->reg1 != REG_D) 2276 as_bad (_("Expecting register D for indexed indirect mode.")); 2277 if ((move_insn) && (!(current_architecture & cpu9s12x))) 2278 as_bad (_("Indexed indirect mode is not allowed for movb/movw.")); 2279 2280 byte = 0xE7; 2281 } 2282 else 2283 { 2284 switch (op->reg1) 2285 { 2286 case REG_A: 2287 byte = 0xE4; 2288 break; 2289 2290 case REG_B: 2291 byte = 0xE5; 2292 break; 2293 2294 default: 2295 as_bad (_("Invalid accumulator register.")); 2296 2297 case REG_D: 2298 byte = 0xE6; 2299 break; 2300 } 2301 } 2302 switch (op->reg2) 2303 { 2304 case REG_X: 2305 break; 2306 2307 case REG_Y: 2308 byte |= (1 << 3); 2309 break; 2310 2311 case REG_SP: 2312 byte |= (2 << 3); 2313 break; 2314 2315 case REG_PC: 2316 byte |= (3 << 3); 2317 break; 2318 2319 default: 2320 as_bad (_("Invalid indexed register.")); 2321 break; 2322 } 2323 f = frag_more (1); 2324 number_to_chars_bigendian (f, byte, 1); 2325 return 1; 2326 } 2327 2328 fprintf (stderr, "mode = 0x%x\nop->reg1 = 0x%x\nop->reg2 = 0x%x\n", 2329 mode, op->reg1, op->reg2); 2330 as_fatal (_("Addressing mode not implemented yet.")); 2331 return 0; 2332 } 2333 2334 /* Assemble the 68HC12 register mode byte. */ 2335 static int 2336 build_reg_mode (operand *op, int format) 2337 { 2338 unsigned char byte; 2339 char *f; 2340 2341 if ((format & M6812_OP_SEX_MARKER) 2342 && (op->reg1 != REG_A) && (op->reg1 != REG_B) && (op->reg1 != REG_CCR) 2343 && (!(current_architecture & cpu9s12x))) 2344 as_bad (_("Invalid source register for this instruction, use 'tfr'.")); 2345 else if (op->reg1 == REG_NONE || op->reg1 == REG_PC) 2346 as_bad (_("Invalid source register.")); 2347 2348 if (format & M6812_OP_SEX_MARKER 2349 && op->reg2 != REG_D 2350 && op->reg2 != REG_X && op->reg2 != REG_Y && op->reg2 != REG_SP) 2351 as_bad (_("Invalid destination register for this instruction, use 'tfr'.")); 2352 else if (op->reg2 == REG_NONE || op->reg2 == REG_PC) 2353 as_bad (_("Invalid destination register.")); 2354 2355 byte = (op->reg1 << 4) | (op->reg2); 2356 if (format & M6812_OP_EXG_MARKER) 2357 byte |= 0x80; 2358 2359 if ((format & M6812_OP_SEX_MARKER) 2360 && (op->reg1 == REG_D) && (current_architecture & cpu9s12x)) 2361 byte |= 0x08; 2362 2363 f = frag_more (1); 2364 number_to_chars_bigendian (f, byte, 1); 2365 return 1; 2366 } 2367 2368 /* build_insn_xg takes a pointer to the opcode entry in the opcode table, 2369 the array of operand expressions and builds the corresponding instruction. */ 2370 2371 static void 2372 build_insn_xg (struct m68hc11_opcode *opcode, 2373 operand operands[], 2374 int nb_operands ATTRIBUTE_UNUSED) 2375 { 2376 char *f; 2377 long format; 2378 2379 /* Put the page code instruction if there is one. */ 2380 format = opcode->format; 2381 2382 if (!(operands[0].mode & (M6811_OP_LOW_ADDR | M6811_OP_HIGH_ADDR))) 2383 /* Need to retain those two modes, but clear for others. */ 2384 operands[0].mode = 0; 2385 2386 if (format & M68XG_OP_R_IMM8) 2387 { 2388 /* These opcodes are byte followed by imm8. */ 2389 f = m68hc11_new_insn (1); 2390 number_to_chars_bigendian (f, opcode->opcode >> 8, 1); 2391 fixup8_xg (&operands[0].exp, format, operands[0].mode); 2392 } 2393 else if (format & M68XG_OP_R_IMM16) 2394 { 2395 fixS *fixp; 2396 /* These opcodes expand into two imm8 instructions. 2397 Emit as low:high as per the Freescale datasheet. 2398 The linker requires them to be adjacent to handle the upper byte. */ 2399 2400 /* Build low byte. */ 2401 f = m68hc11_new_insn (1); 2402 number_to_chars_bigendian (f, opcode->opcode >> 8, 1); 2403 operands[0].mode = M6811_OP_LOW_ADDR; 2404 f = frag_more (1); 2405 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1, 2406 &operands[0].exp, FALSE, BFD_RELOC_M68HC12_LO8XG); 2407 fixp->fx_no_overflow = 1; 2408 number_to_chars_bigendian (f, 0, 1); 2409 2410 /* Build high byte. */ 2411 f = m68hc11_new_insn (1); 2412 number_to_chars_bigendian (f, (opcode->opcode >> 8) | 0x08, 1); 2413 operands[0].mode = M6811_OP_HIGH_ADDR; 2414 f = frag_more (1); 2415 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1, 2416 &operands[0].exp, FALSE, BFD_RELOC_M68HC12_HI8XG); 2417 fixp->fx_no_overflow = 1; 2418 number_to_chars_bigendian (f, 0, 1); 2419 2420 } 2421 else if (format & M68XG_OP_REL9) 2422 { 2423 f = m68hc11_new_insn (1); 2424 number_to_chars_bigendian (f, opcode->opcode >> 8, 1); /* High byte. */ 2425 fixup8_xg (&operands[0].exp, format, M68XG_OP_REL9); 2426 } 2427 else if (format & M68XG_OP_REL10) 2428 { 2429 f = m68hc11_new_insn (1); 2430 number_to_chars_bigendian (f, opcode->opcode >> 8, 1); /* High byte. */ 2431 fixup8_xg (&operands[0].exp, format, M68XG_OP_REL10); 2432 } 2433 else 2434 { 2435 f = m68hc11_new_insn (2); 2436 number_to_chars_bigendian (f, opcode->opcode, 2); 2437 } 2438 return; 2439 } 2440 2441 /* build_insn takes a pointer to the opcode entry in the opcode table, 2442 the array of operand expressions and builds the corresponding instruction. 2443 This operation only deals with non relative jumps insn (need special 2444 handling). */ 2445 2446 static void 2447 build_insn (struct m68hc11_opcode *opcode, 2448 operand operands[], 2449 int nb_operands ATTRIBUTE_UNUSED) 2450 { 2451 int i; 2452 char *f; 2453 long format; 2454 int move_insn = 0; 2455 2456 /* Put the page code instruction if there is one. */ 2457 format = opcode->format; 2458 2459 if (format & M6811_OP_BRANCH) 2460 fix_new (frag_now, frag_now_fix (), 0, 2461 &abs_symbol, 0, 1, BFD_RELOC_M68HC11_RL_JUMP); 2462 2463 if (format & OP_EXTENDED) 2464 { 2465 int page_code; 2466 2467 f = m68hc11_new_insn (2); 2468 if (format & M6811_OP_PAGE2) 2469 page_code = M6811_OPCODE_PAGE2; 2470 else if (format & M6811_OP_PAGE3) 2471 page_code = M6811_OPCODE_PAGE3; 2472 else 2473 page_code = M6811_OPCODE_PAGE4; 2474 2475 number_to_chars_bigendian (f, page_code, 1); 2476 f++; 2477 } 2478 else 2479 f = m68hc11_new_insn (1); 2480 2481 number_to_chars_bigendian (f, opcode->opcode, 1); 2482 2483 i = 0; 2484 2485 /* The 68HC12 movb and movw instructions are special. We have to handle 2486 them in a special way. */ 2487 if (format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2)) 2488 { 2489 move_insn = 1; 2490 if (format & M6812_OP_IDX) 2491 { 2492 build_indexed_byte (&operands[0], format, 1); 2493 i = 1; 2494 format &= ~M6812_OP_IDX; 2495 } 2496 if (format & M6812_OP_IDX_P2) 2497 { 2498 build_indexed_byte (&operands[1], format, 1); 2499 i = 0; 2500 format &= ~M6812_OP_IDX_P2; 2501 } 2502 } 2503 2504 if (format & (M6811_OP_DIRECT | M6811_OP_IMM8)) 2505 { 2506 fixup8 (&operands[i].exp, 2507 format & (M6811_OP_DIRECT | M6811_OP_IMM8 | M6812_OP_TRAP_ID), 2508 operands[i].mode); 2509 i++; 2510 } 2511 else if (IS_CALL_SYMBOL (format) && nb_operands == 1) 2512 { 2513 format &= ~M6812_OP_PAGE; 2514 fixup24 (&operands[i].exp, format & M6811_OP_IND16, 2515 operands[i].mode); 2516 i++; 2517 } 2518 else if (format & (M6811_OP_IMM16 | M6811_OP_IND16)) 2519 { 2520 fixup16 (&operands[i].exp, 2521 format & (M6811_OP_IMM16 | M6811_OP_IND16 | M6812_OP_PAGE), 2522 operands[i].mode); 2523 i++; 2524 } 2525 else if (format & (M6811_OP_IX | M6811_OP_IY)) 2526 { 2527 if ((format & M6811_OP_IX) && (operands[0].reg1 != REG_X)) 2528 as_bad (_("Invalid indexed register, expecting register X.")); 2529 if ((format & M6811_OP_IY) && (operands[0].reg1 != REG_Y)) 2530 as_bad (_("Invalid indexed register, expecting register Y.")); 2531 2532 fixup8 (&operands[0].exp, M6811_OP_IX, operands[0].mode); 2533 i = 1; 2534 } 2535 else if (format & 2536 (M6812_OP_IDX | M6812_OP_IDX_2 | M6812_OP_IDX_1 2537 | M6812_OP_D_IDX | M6812_OP_D_IDX_2)) 2538 { 2539 build_indexed_byte (&operands[i], format, move_insn); 2540 i++; 2541 } 2542 else if (format & M6812_OP_REG && current_architecture & cpu6812) 2543 { 2544 build_reg_mode (&operands[i], format); 2545 i++; 2546 } 2547 if (format & M6811_OP_BITMASK) 2548 { 2549 fixup8 (&operands[i].exp, M6811_OP_BITMASK, operands[i].mode); 2550 i++; 2551 } 2552 if (format & M6811_OP_JUMP_REL) 2553 { 2554 fixup8 (&operands[i].exp, M6811_OP_JUMP_REL, operands[i].mode); 2555 } 2556 else if (format & M6812_OP_IND16_P2) 2557 { 2558 fixup16 (&operands[1].exp, M6811_OP_IND16, operands[1].mode); 2559 } 2560 if (format & M6812_OP_PAGE) 2561 { 2562 fixup8 (&operands[i].exp, M6812_OP_PAGE, operands[i].mode); 2563 } 2564 } 2565 2566 /* Opcode identification and operand analysis. */ 2568 2569 /* find() gets a pointer to an entry in the opcode table. It must look at all 2570 opcodes with the same name and use the operands to choose the correct 2571 opcode. Returns the opcode pointer if there was a match and 0 if none. */ 2572 static struct m68hc11_opcode * 2573 find (struct m68hc11_opcode_def *opc, operand operands[], int nb_operands) 2574 { 2575 int i, match, pos; 2576 struct m68hc11_opcode *opcode; 2577 struct m68hc11_opcode *op_indirect; 2578 2579 op_indirect = 0; 2580 opcode = opc->opcode; 2581 2582 /* Now search the opcode table table for one with operands 2583 that matches what we've got. */ 2584 2585 if (current_architecture & cpuxgate) 2586 { 2587 /* Many XGATE insns are simple enough that we get an exact match. */ 2588 for (pos = match = 0; match == 0 && pos < opc->nb_modes; pos++, opcode++) 2589 if (opcode->format == operands[nb_operands-1].mode) 2590 return opcode; 2591 2592 return 0; 2593 } 2594 2595 /* Non XGATE */ 2596 2597 /* Now search the opcode table table for one with operands 2598 that matches what we've got. We're only done if the operands matched so 2599 far AND there are no more to check. */ 2600 for (pos = match = 0; match == 0 && pos < opc->nb_modes; pos++, opcode++) 2601 { 2602 int poss_indirect = 0; 2603 long format = opcode->format; 2604 int expect; 2605 2606 expect = 0; 2607 if (opcode->format & M6811_OP_MASK) 2608 expect++; 2609 if (opcode->format & M6811_OP_BITMASK) 2610 expect++; 2611 if (opcode->format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) 2612 expect++; 2613 if (opcode->format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2)) 2614 expect++; 2615 if ((opcode->format & M6812_OP_PAGE) 2616 && (!IS_CALL_SYMBOL (opcode->format) || nb_operands == 2)) 2617 expect++; 2618 2619 for (i = 0; expect == nb_operands && i < nb_operands; i++) 2620 { 2621 int mode = operands[i].mode; 2622 2623 if (mode & M6811_OP_IMM16) 2624 { 2625 if (format & 2626 (M6811_OP_IMM8 | M6811_OP_IMM16 | M6811_OP_BITMASK)) 2627 continue; 2628 break; 2629 } 2630 if (mode == M6811_OP_DIRECT) 2631 { 2632 if (format & M6811_OP_DIRECT) 2633 continue; 2634 2635 /* If the operand is a page 0 operand, remember a 2636 possible <abs-16> addressing mode. We mark 2637 this and continue to check other operands. */ 2638 if (format & M6811_OP_IND16 2639 && flag_strict_direct_addressing && op_indirect == 0) 2640 { 2641 poss_indirect = 1; 2642 continue; 2643 } 2644 break; 2645 } 2646 if (mode & M6811_OP_IND16) 2647 { 2648 if (i == 0 && (format & M6811_OP_IND16) != 0) 2649 continue; 2650 if (i != 0 && (format & M6812_OP_PAGE) != 0) 2651 continue; 2652 if (i != 0 && (format & M6812_OP_IND16_P2) != 0) 2653 continue; 2654 if (i == 0 && (format & M6811_OP_BITMASK)) 2655 break; 2656 } 2657 if (mode & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) 2658 { 2659 if (format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) 2660 continue; 2661 } 2662 if (mode & M6812_OP_REG) 2663 { 2664 if (i == 0 2665 && (format & M6812_OP_REG) 2666 && (operands[i].reg2 == REG_NONE)) 2667 continue; 2668 if (i == 0 2669 && (format & M6812_OP_REG) 2670 && (format & M6812_OP_REG_2) 2671 && (operands[i].reg2 != REG_NONE)) 2672 continue; 2673 if (i == 0 2674 && (format & M6812_OP_IDX) 2675 && (operands[i].reg2 != REG_NONE)) 2676 continue; 2677 if (i == 0 2678 && (format & M6812_OP_IDX) 2679 && (format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2))) 2680 continue; 2681 if (i == 1 2682 && (format & M6812_OP_IDX_P2)) 2683 continue; 2684 break; 2685 } 2686 if (mode & M6812_OP_IDX) 2687 { 2688 if (format & M6811_OP_IX && operands[i].reg1 == REG_X) 2689 continue; 2690 if (format & M6811_OP_IY && operands[i].reg1 == REG_Y) 2691 continue; 2692 if (i == 0 2693 && format & (M6812_OP_IDX | M6812_OP_IDX_1 | M6812_OP_IDX_2) 2694 && (operands[i].reg1 == REG_X 2695 || operands[i].reg1 == REG_Y 2696 || operands[i].reg1 == REG_SP 2697 || operands[i].reg1 == REG_PC)) 2698 continue; 2699 if (i == 1 && (format & M6812_OP_IDX_P2)) 2700 continue; 2701 } 2702 if (mode & format & (M6812_OP_D_IDX | M6812_OP_D_IDX_2)) 2703 { 2704 if (i == 0) 2705 continue; 2706 } 2707 if (mode & M6812_AUTO_INC_DEC) 2708 { 2709 if (i == 0 2710 && format & (M6812_OP_IDX | M6812_OP_IDX_1 | 2711 M6812_OP_IDX_2)) 2712 continue; 2713 if (i == 1 && format & M6812_OP_IDX_P2) 2714 continue; 2715 } 2716 break; 2717 } 2718 match = i == nb_operands; 2719 2720 /* Operands are ok but an operand uses page 0 addressing mode 2721 while the insn supports abs-16 mode. Keep a reference to this 2722 insns in case there is no insn supporting page 0 addressing. */ 2723 if (match && poss_indirect) 2724 { 2725 op_indirect = opcode; 2726 match = 0; 2727 } 2728 if (match) 2729 break; 2730 } 2731 2732 /* Page 0 addressing is used but not supported by any insn. 2733 If absolute addresses are supported, we use that insn. */ 2734 if (match == 0 && op_indirect) 2735 { 2736 opcode = op_indirect; 2737 match = 1; 2738 } 2739 2740 return match ? opcode : 0; 2741 } 2742 2743 /* Find the real opcode and its associated operands. We use a progressive 2744 approach here. On entry, 'opc' points to the first opcode in the 2745 table that matches the opcode name in the source line. We try to 2746 isolate an operand, find a possible match in the opcode table. 2747 We isolate another operand if no match were found. The table 'operands' 2748 is filled while operands are recognized. 2749 2750 Returns the opcode pointer that matches the opcode name in the 2751 source line and the associated operands. */ 2752 static struct m68hc11_opcode * 2753 find_opcode (struct m68hc11_opcode_def *opc, operand operands[], 2754 int *nb_operands) 2755 { 2756 struct m68hc11_opcode *opcode; 2757 int i; 2758 2759 if (opc->max_operands == 0) 2760 { 2761 *nb_operands = 0; 2762 return opc->opcode; 2763 } 2764 2765 for (i = 0; i < opc->max_operands;) 2766 { 2767 int result; 2768 2769 result = get_operand (&operands[i], i, opc->format); 2770 if (result <= 0) 2771 return 0; 2772 2773 /* Special case where the bitmask of the bclr/brclr 2774 instructions is not introduced by #. 2775 Example: bclr 3,x $80. */ 2776 if (i == 1 && (opc->format & M6811_OP_BITMASK) 2777 && (operands[i].mode & M6811_OP_IND16)) 2778 { 2779 operands[i].mode = M6811_OP_IMM16; 2780 } 2781 2782 i += result; 2783 *nb_operands = i; 2784 if (i >= opc->min_operands) 2785 { 2786 opcode = find (opc, operands, i); 2787 2788 /* Another special case for 'call foo,page' instructions. 2789 Since we support 'call foo' and 'call foo,page' we must look 2790 if the optional page specification is present otherwise we will 2791 assemble immediately and treat the page spec as garbage. */ 2792 if (opcode && !(opcode->format & M6812_OP_PAGE)) 2793 return opcode; 2794 2795 if (opcode && *input_line_pointer != ',') 2796 return opcode; 2797 } 2798 2799 if (*input_line_pointer == ',') 2800 input_line_pointer++; 2801 } 2802 2803 return 0; 2804 } 2805 2806 #define M6812_XBCC_MARKER (M6812_OP_TBCC_MARKER \ 2807 | M6812_OP_DBCC_MARKER \ 2808 | M6812_OP_IBCC_MARKER) 2809 2810 /* Gas line assembler entry point. */ 2812 2813 /* This is the main entry point for the machine-dependent assembler. str 2814 points to a machine-dependent instruction. This function is supposed to 2815 emit the frags/bytes it assembles to. */ 2816 void 2817 md_assemble (char *str) 2818 { 2819 struct m68hc11_opcode_def *opc; 2820 struct m68hc11_opcode *opcode; 2821 2822 struct m68hc11_opcode opcode_local; 2823 unsigned char *op_start, *op_end; 2824 char *save; 2825 char name[20]; 2826 int nlen = 0; 2827 operand operands[M6811_MAX_OPERANDS]; 2828 int nb_operands = 0; 2829 int branch_optimize = 0; 2830 int alias_id = -1; 2831 2832 /* Drop leading whitespace. */ 2833 while (*str == ' ') 2834 str++; 2835 2836 /* Find the opcode end and get the opcode in 'name'. The opcode is forced 2837 lower case (the opcode table only has lower case op-codes). */ 2838 for (op_start = op_end = (unsigned char *) str; 2839 *op_end && !is_end_of_line[*op_end] && *op_end != ' '; 2840 op_end++) 2841 { 2842 name[nlen] = TOLOWER (op_start[nlen]); 2843 nlen++; 2844 if (nlen == sizeof (name) - 1) 2845 break; 2846 } 2847 name[nlen] = 0; 2848 2849 if (nlen == 0) 2850 { 2851 as_bad (_("No instruction or missing opcode.")); 2852 return; 2853 } 2854 2855 if (current_architecture == cpuxgate) 2856 { 2857 /* Find the opcode definition given its name. */ 2858 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, name); 2859 if (opc == NULL) 2860 { 2861 as_bad (_("Opcode `%s' is not recognized."), name); 2862 return; 2863 } 2864 2865 /* Grab a local copy. */ 2866 opcode_local.name = opc->opcode->name; 2867 /* These will be incomplete where multiple variants exist. */ 2868 opcode_local.opcode = opc->opcode->opcode; 2869 opcode_local.format = opc->opcode->format; 2870 2871 save = input_line_pointer; 2872 input_line_pointer = (char *) op_end; 2873 2874 if (opc->format == M68XG_OP_NONE) 2875 { 2876 /* No special handling required. */ 2877 opcode_local.format = M68XG_OP_NONE; 2878 build_insn_xg (opc->opcode, operands, 0); 2879 return; 2880 } 2881 2882 /* Special handling of TFR. */ 2883 if (strncmp (opc->opcode->name, "tfr",3) == 0) 2884 { 2885 /* There must be two operands with a comma. */ 2886 input_line_pointer = skip_whites (input_line_pointer); 2887 operands[0].reg1 = register_name (); 2888 if (operands[0].reg1 == REG_NONE) 2889 { 2890 as_bad ("Invalid register\n"); 2891 return; 2892 } 2893 input_line_pointer = skip_whites (input_line_pointer); 2894 if (*input_line_pointer != ',') 2895 { 2896 as_bad ("Missing comma.\n"); 2897 return; 2898 } 2899 input_line_pointer++; 2900 input_line_pointer = skip_whites (input_line_pointer); 2901 operands[1].reg1 = register_name (); 2902 if (operands[1].reg1 == REG_NONE) 2903 { 2904 as_bad ("Invalid register\n"); 2905 return; 2906 } 2907 input_line_pointer = skip_whites (input_line_pointer); 2908 if (*input_line_pointer != '\n' && *input_line_pointer) 2909 { 2910 as_bad (_("Garbage at end of instruction: `%s'."), 2911 input_line_pointer); 2912 return; 2913 } 2914 if (operands[1].reg1 == REG_CCR) /* ,CCR */ 2915 opc->opcode->opcode = 0x00f8 | ( operands[0].reg1 << 8); 2916 else if (operands[0].reg1 == REG_CCR) /* CCR, */ 2917 opc->opcode->opcode = 0x00f9 | ( operands[1].reg1 << 8); 2918 else if (operands[1].reg1 == REG_PC) /* ,PC */ 2919 opc->opcode->opcode = 0x00fa | ( operands[0].reg1 << 8); 2920 else 2921 { 2922 as_bad ("Invalid operand to TFR\n"); 2923 return; 2924 } 2925 /* no special handling required */ 2926 opcode_local.format = M68XG_OP_NONE; 2927 opcode_local.opcode = opc->opcode->opcode; 2928 build_insn_xg (&opcode_local, operands, 0); 2929 return; 2930 } 2931 2932 /* CSEM, SSEM */ 2933 if (opc->format & M68XG_OP_IMM3) 2934 { 2935 /* Either IMM3 or R */ 2936 input_line_pointer = skip_whites (input_line_pointer); 2937 if ((*input_line_pointer == 'R') || (*input_line_pointer == 'r')) 2938 { 2939 operands[0].reg1 = register_name (); 2940 if (operands[0].reg1 == REG_NONE) 2941 { 2942 as_bad ("Invalid register\n"); 2943 return; 2944 } 2945 operands[0].mode = M68XG_OP_R; 2946 /* One opcode has multiple modes, so find right one. */ 2947 opcode = find (opc, operands, 1); 2948 if (opcode) 2949 { 2950 opcode_local.opcode = opcode->opcode 2951 | (operands[0].reg1 << 8); 2952 opcode_local.format = M68XG_OP_NONE; 2953 build_insn_xg (&opcode_local, operands, 1); 2954 } 2955 else 2956 as_bad ("No opcode found\n"); 2957 2958 return; 2959 } 2960 else 2961 { 2962 if (*input_line_pointer == '#') 2963 input_line_pointer++; 2964 2965 expression (&operands[0].exp); 2966 if (operands[0].exp.X_op == O_illegal) 2967 { 2968 as_bad (_("Illegal operand.")); 2969 return; 2970 } 2971 else if (operands[0].exp.X_op == O_absent) 2972 { 2973 as_bad (_("Missing operand.")); 2974 return; 2975 } 2976 2977 if (check_range (operands[0].exp.X_add_number,M68XG_OP_IMM3)) 2978 { 2979 opcode_local.opcode |= (operands[0].exp.X_add_number); 2980 operands[0].mode = M68XG_OP_IMM3; 2981 2982 opcode = find (opc, operands, 1); 2983 if (opcode) 2984 { 2985 opcode_local.opcode = opcode->opcode; 2986 opcode_local.opcode 2987 |= (operands[0].exp.X_add_number) << 8; 2988 opcode_local.format = M68XG_OP_NONE; 2989 build_insn_xg (&opcode_local, operands, 1); 2990 } 2991 else 2992 as_bad ("No opcode found\n"); 2993 2994 return; 2995 } 2996 else 2997 { 2998 as_bad ("Number out of range for IMM3\n"); 2999 return; 3000 } 3001 } 3002 } 3003 3004 /* Special handling of SIF. */ 3005 if (strncmp (opc->opcode->name, "sif",3) == 0) 3006 { 3007 /* Either OP_NONE or OP_RS. */ 3008 if (*input_line_pointer != '\n') 3009 input_line_pointer = skip_whites (input_line_pointer); 3010 3011 if ((*input_line_pointer == '\n') || (*input_line_pointer == '\r') 3012 || (*input_line_pointer == '\0')) 3013 opc->opcode->opcode = 0x0300; 3014 else 3015 { 3016 operands[0].reg1 = register_name (); 3017 if (operands[0].reg1 == REG_NONE) 3018 { 3019 as_bad ("Invalid register\n"); 3020 return; 3021 } 3022 opcode_local.opcode = 0x00f7 | (operands[0].reg1 << 8); 3023 } 3024 opcode_local.format = M68XG_OP_NONE; 3025 build_insn_xg (&opcode_local, operands, 0); 3026 return; 3027 } 3028 3029 /* SEX, PAR, JAL plus aliases NEG, TST, COM */ 3030 if (opc->format & M68XG_OP_R) 3031 { 3032 input_line_pointer = skip_whites (input_line_pointer); 3033 operands[0].reg1 = register_name (); 3034 if (operands[0].reg1 == REG_NONE) 3035 { 3036 as_bad ("Invalid register\n"); 3037 return; 3038 } 3039 if ((*input_line_pointer == '\n') || (*input_line_pointer == '\r') 3040 || (*input_line_pointer == '\0')) 3041 { 3042 /* Likely to be OP R. */ 3043 if (opc->format & M68XG_OP_R) 3044 { 3045 operands[0].mode = M68XG_OP_R; 3046 3047 opcode = find (opc, operands, 1); 3048 if (opcode) 3049 { 3050 if ((strncmp (opc->opcode->name, "com",3) == 0) 3051 || (strncmp (opc->opcode->name, "neg",3) == 0)) 3052 /* Special case for com RD as alias for sub RD,R0,RS */ 3053 /* Special case for neg RD as alias for sub RD,R0,RS */ 3054 opcode_local.opcode = opcode->opcode 3055 | (operands[0].reg1 << 8) | (operands[0].reg1 << 2); 3056 else if (strncmp (opc->opcode->name, "tst",3) == 0) 3057 /* Special case for tst RS alias for sub R0, RS, R0 */ 3058 opcode_local.opcode = opcode->opcode 3059 | (operands[0].reg1 << 5); 3060 else 3061 opcode_local.opcode |= (operands[0].reg1 << 8); 3062 } 3063 opcode_local.format = M68XG_OP_NONE; 3064 build_insn_xg (&opcode_local, operands, 0); 3065 } 3066 else 3067 as_bad ("No valid mode found\n"); 3068 3069 return; 3070 } 3071 } 3072 3073 if (opc->format & (M68XG_OP_REL9 | M68XG_OP_REL10)) 3074 { 3075 opcode_local.format = opc->format; 3076 input_line_pointer = skip_whites (input_line_pointer); 3077 expression (&operands[0].exp); 3078 if (operands[0].exp.X_op == O_illegal) 3079 { 3080 as_bad (_("Illegal operand.")); 3081 return; 3082 } 3083 else if (operands[0].exp.X_op == O_absent) 3084 { 3085 as_bad (_("Missing operand.")); 3086 return; 3087 } 3088 opcode_local.opcode = opc->opcode->opcode; 3089 build_insn_xg (&opcode_local, operands, 1); 3090 return; 3091 } 3092 3093 3094 /* For other command formats, parse input line and determine the mode 3095 we are using as we go. */ 3096 3097 input_line_pointer = skip_whites (input_line_pointer); 3098 if ((*input_line_pointer == '\n') || (*input_line_pointer == '\r') 3099 || (*input_line_pointer == '\0')) 3100 return; /* nothing left */ 3101 3102 if (*input_line_pointer == '#') 3103 { 3104 as_bad ("No register specified before hash\n"); 3105 return; 3106 } 3107 3108 /* first operand is expected to be a register */ 3109 if ((*input_line_pointer == 'R') || (*input_line_pointer == 'r')) 3110 { 3111 operands[0].reg1 = register_name (); 3112 if (operands[0].reg1 == REG_NONE) 3113 { 3114 as_bad ("Invalid register\n"); 3115 return; 3116 } 3117 } 3118 3119 input_line_pointer = skip_whites (input_line_pointer); 3120 if (*input_line_pointer != ',') 3121 { 3122 as_bad ("Missing operand\n"); 3123 return; 3124 } 3125 input_line_pointer++; 3126 input_line_pointer = skip_whites (input_line_pointer); 3127 3128 if (*input_line_pointer == '#') 3129 { 3130 /* Some kind of immediate mode, check if this is possible. */ 3131 if (!(opc->format 3132 & (M68XG_OP_R_IMM8 | M68XG_OP_R_IMM16 | M68XG_OP_R_IMM4))) 3133 as_bad ("Invalid immediate mode for `%s'", opc->opcode->name); 3134 else 3135 { 3136 input_line_pointer++; 3137 input_line_pointer = skip_whites (input_line_pointer); 3138 if (strncmp (input_line_pointer, "%hi", 3) == 0) 3139 { 3140 input_line_pointer += 3; 3141 operands[0].mode = M6811_OP_HIGH_ADDR; 3142 } 3143 else if (strncmp (input_line_pointer, "%lo", 3) == 0) 3144 { 3145 input_line_pointer += 3; 3146 operands[0].mode = M6811_OP_LOW_ADDR; 3147 } 3148 else 3149 operands[0].mode = 0; 3150 3151 expression (&operands[0].exp); 3152 if (operands[0].exp.X_op == O_illegal) 3153 { 3154 as_bad (_("Illegal operand.")); 3155 return; 3156 } 3157 else if (operands[0].exp.X_op == O_absent) 3158 { 3159 as_bad (_("Missing operand.")); 3160 return; 3161 } 3162 /* ok so far, can only be one mode */ 3163 opcode_local.format = opc->format 3164 & (M68XG_OP_R_IMM8 | M68XG_OP_R_IMM16 | M68XG_OP_R_IMM4); 3165 if (opcode_local.format & M68XG_OP_R_IMM4) 3166 { 3167 operands[0].mode = M68XG_OP_R_IMM4; 3168 /* same opcodes have multiple modes, so find right one */ 3169 opcode = find (opc, operands, 1); 3170 if (opcode) 3171 opcode_local.opcode = opcode->opcode 3172 | (operands[0].reg1 << 8); 3173 3174 if (operands[0].exp.X_op != O_constant) 3175 as_bad ("Only constants supported at for IMM4 mode\n"); 3176 else 3177 { 3178 if (check_range 3179 (operands[0].exp.X_add_number,M68XG_OP_R_IMM4)) 3180 opcode_local.opcode 3181 |= (operands[0].exp.X_add_number << 4); 3182 else 3183 as_bad ("Number out of range for IMM4\n"); 3184 } 3185 opcode_local.format = M68XG_OP_NONE; 3186 } 3187 else if (opcode_local.format & M68XG_OP_R_IMM16) 3188 { 3189 operands[0].mode = M68XG_OP_R_IMM16; 3190 3191 opcode = find (opc, operands, 1); 3192 if (opcode) 3193 { 3194 opcode_local.opcode = opcode->opcode 3195 | (operands[0].reg1 << 8); 3196 } 3197 } 3198 else 3199 { 3200 opcode_local.opcode = opc->opcode->opcode 3201 | (operands[0].reg1 << 8); 3202 } 3203 build_insn_xg (&opcode_local, operands, 1); 3204 } 3205 } 3206 else if ((*input_line_pointer == 'R') || (*input_line_pointer == 'r')) 3207 { 3208 /* we've got as far as OP R, R */ 3209 operands[1].reg1 = register_name (); 3210 if (operands[1].reg1 == REG_NONE) 3211 { 3212 as_bad ("Invalid register\n"); 3213 return; 3214 } 3215 if ((*input_line_pointer == '\n') || (*input_line_pointer == '\r') 3216 || (*input_line_pointer == '\0')) 3217 { 3218 /* looks like OP_R_R */ 3219 if (opc->format & M68XG_OP_R_R) 3220 { 3221 operands[0].mode = M68XG_OP_R_R; 3222 /* same opcodes have multiple modes, so find right one */ 3223 opcode = find (opc, operands, 1); 3224 if (opcode) 3225 { 3226 if ((strncmp (opc->opcode->name, "com",3) == 0) 3227 || (strncmp (opc->opcode->name, "mov",3) == 0) 3228 || (strncmp (opc->opcode->name, "neg",3) == 0)) 3229 { 3230 /* Special cases for: 3231 com RD, RS alias for xnor RD,R0,RS 3232 mov RD, RS alias for or RD, R0, RS 3233 neg RD, RS alias for sub RD, R0, RS */ 3234 opcode_local.opcode = opcode->opcode 3235 | (operands[0].reg1 << 8) | (operands[1].reg1 << 2); 3236 } 3237 else if ((strncmp (opc->opcode->name, "cmp",3) == 0) 3238 || (strncmp (opc->opcode->name, "cpc",3) == 0)) 3239 { 3240 /* special cases for: 3241 cmp RS1, RS2 alias for sub R0, RS1, RS2 3242 cpc RS1, RS2 alias for sbc R0, RS1, RS2 */ 3243 opcode_local.opcode = opcode->opcode 3244 | (operands[0].reg1 << 5) | (operands[1].reg1 << 2); 3245 } 3246 else 3247 { 3248 opcode_local.opcode = opcode->opcode 3249 | (operands[0].reg1 << 8) | (operands[1].reg1 << 5); 3250 } 3251 opcode_local.format = M68XG_OP_NONE; 3252 build_insn_xg (&opcode_local, operands, 1); 3253 } 3254 } 3255 else 3256 { 3257 as_bad ("No valid mode found\n"); 3258 } 3259 } 3260 else 3261 { 3262 /* more data */ 3263 if (*input_line_pointer != ',') 3264 { 3265 as_bad (_("Missing operand.")); 3266 return; 3267 } 3268 input_line_pointer++; 3269 input_line_pointer = skip_whites (input_line_pointer); 3270 if ((*input_line_pointer == 'R') || (*input_line_pointer == 'r')) 3271 { 3272 operands[2].reg1 = register_name (); 3273 if (operands[2].reg1 == REG_NONE) 3274 { 3275 as_bad ("Invalid register\n"); 3276 return; 3277 } 3278 if (opc->format & M68XG_OP_R_R_R) 3279 { 3280 operands[0].mode = M68XG_OP_R_R_R; 3281 3282 opcode = find (opc, operands, 1); 3283 if (opcode) 3284 { 3285 opcode_local.opcode = opcode->opcode 3286 | (operands[0].reg1 << 8) | (operands[1].reg1 << 5) 3287 | (operands[2].reg1 << 2); 3288 opcode_local.format = M68XG_OP_NONE; 3289 build_insn_xg (&opcode_local, operands, 1); 3290 } 3291 } 3292 else 3293 { 3294 as_bad ("No valid mode found\n"); 3295 } 3296 } 3297 } 3298 } 3299 else if (*input_line_pointer == '(') /* Indexed modes */ 3300 { 3301 input_line_pointer++; 3302 input_line_pointer = skip_whites (input_line_pointer); 3303 if ((*input_line_pointer == 'R') || (*input_line_pointer == 'r')) 3304 { 3305 /* we've got as far as OP R, (R */ 3306 operands[1].reg1 = register_name (); 3307 if (operands[1].reg1 == REG_NONE) 3308 { 3309 as_bad ("Invalid register\n"); 3310 return; 3311 } 3312 3313 if ((*input_line_pointer == '\n') || (*input_line_pointer == '\r') 3314 || (*input_line_pointer == '\0')) 3315 { 3316 /* Looks like OP_R_R. */ 3317 as_bad (_("Missing operand.")); 3318 return; 3319 } 3320 3321 input_line_pointer = skip_whites (input_line_pointer); 3322 3323 if (*input_line_pointer != ',') 3324 { 3325 as_bad (_("Missing operand.")); 3326 return; 3327 } 3328 input_line_pointer++; 3329 input_line_pointer = skip_whites (input_line_pointer); 3330 3331 if (*input_line_pointer == '#') 3332 { 3333 input_line_pointer++; 3334 input_line_pointer = skip_whites (input_line_pointer); 3335 expression (&operands[0].exp); 3336 if (operands[0].exp.X_op == O_illegal) 3337 { 3338 as_bad (_("Illegal operand.")); 3339 return; 3340 } 3341 else if (operands[0].exp.X_op == O_absent) 3342 { 3343 as_bad (_("Missing operand.")); 3344 return; 3345 } 3346 3347 input_line_pointer = skip_whites (input_line_pointer); 3348 if (*input_line_pointer != ')') 3349 { 3350 as_bad ("Missing `)' to close register indirect operand."); 3351 return; 3352 } 3353 else 3354 { 3355 input_line_pointer++; 3356 } 3357 3358 /* Ok so far, can only be one mode. */ 3359 opcode_local.format = M68XG_OP_R_R_OFFS5; 3360 operands[0].mode = M68XG_OP_R_R_OFFS5; 3361 3362 opcode = find (opc, operands, 1); 3363 if (opcode) 3364 { 3365 opcode_local.opcode = opcode->opcode 3366 | (operands[0].reg1 << 8) | (operands[1].reg1 << 5); 3367 if (operands[0].exp.X_op != O_constant) 3368 { 3369 as_bad 3370 ("Only constants supported for indexed OFFS5 mode\n"); 3371 } 3372 else 3373 { 3374 if (check_range (operands[0].exp.X_add_number, 3375 M68XG_OP_R_R_OFFS5)) 3376 { 3377 opcode_local.opcode 3378 |= (operands[0].exp.X_add_number); 3379 opcode_local.format = M68XG_OP_NONE; 3380 build_insn_xg (&opcode_local, operands, 1); 3381 } 3382 else 3383 { 3384 as_bad ("Number out of range for OFFS5\n"); 3385 } 3386 } 3387 } 3388 } 3389 else 3390 { 3391 operands[0].mode = M68XG_OP_RD_RB_RI; 3392 3393 if (*input_line_pointer == '-') 3394 { 3395 operands[0].mode = M68XG_OP_RD_RB_mRI; 3396 input_line_pointer++; 3397 } 3398 operands[2].reg1 = register_name (); 3399 if (operands[2].reg1 == REG_NONE) 3400 { 3401 as_bad ("Invalid register\n"); 3402 return; 3403 } 3404 3405 if (*input_line_pointer == '+') 3406 { 3407 if (opcode_local.format == M68XG_OP_RD_RB_mRI) 3408 { 3409 as_bad (_("Illegal operand.")); 3410 return; 3411 } 3412 operands[0].mode = M68XG_OP_RD_RB_RIp; 3413 input_line_pointer++; 3414 } 3415 3416 input_line_pointer = skip_whites (input_line_pointer); 3417 if (*input_line_pointer != ')') 3418 { 3419 as_bad 3420 ("Missing `)' to close register indirect operand."); 3421 return; 3422 } 3423 else 3424 { 3425 input_line_pointer++; 3426 } 3427 3428 opcode = find (opc, operands, 1); 3429 if (opcode) 3430 { 3431 opcode_local.opcode = opcode->opcode 3432 | (operands[0].reg1 << 8) | (operands[1].reg1 << 5) 3433 | (operands[2].reg1 << 2); 3434 opcode_local.format = M68XG_OP_NONE; 3435 build_insn_xg (&opcode_local, operands, 1); 3436 } 3437 else 3438 { 3439 as_bad ("Failed to find opcode for %s %s\n", 3440 opc->opcode->name, (char *)op_end); 3441 } 3442 } 3443 } 3444 } 3445 else 3446 { 3447 as_bad (_("Failed to find a valid mode for `%s'."), 3448 opc->opcode->name); 3449 } 3450 3451 if (opc->opcode && !flag_mri) 3452 { 3453 char *p = input_line_pointer; 3454 3455 while (*p == ' ' || *p == '\t' || *p == '\n' || *p == '\r') 3456 p++; 3457 3458 if (*p != '\n' && *p) 3459 as_bad (_("Garbage at end of instruction: `%s'."), p); 3460 } 3461 3462 input_line_pointer = save; 3463 3464 /* Opcode is known but does not have valid operands. Print out the 3465 syntax for this opcode. */ 3466 if (opc->opcode == 0) 3467 { 3468 if (flag_print_insn_syntax) 3469 print_insn_format (name); 3470 3471 as_bad (_("Invalid operand for `%s'"), name); 3472 return; 3473 } 3474 3475 return; 3476 } 3477 3478 /* Find the opcode definition given its name. */ 3479 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, name); 3480 3481 /* If it's not recognized, look for 'jbsr' and 'jbxx'. These are 3482 pseudo insns for relative branch. For these branches, we always 3483 optimize them (turned into absolute branches) even if --short-branches 3484 is given. */ 3485 if (opc == NULL && name[0] == 'j' && name[1] == 'b') 3486 { 3487 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, &name[1]); 3488 if (opc 3489 && (!(opc->format & M6811_OP_JUMP_REL) 3490 || (opc->format & M6811_OP_BITMASK))) 3491 opc = 0; 3492 if (opc) 3493 branch_optimize = 1; 3494 } 3495 3496 /* The following test should probably be removed. This does not conform 3497 to Motorola assembler specs. */ 3498 if (opc == NULL && flag_mri) 3499 { 3500 if (*op_end == ' ' || *op_end == '\t') 3501 { 3502 while (*op_end == ' ' || *op_end == '\t') 3503 op_end++; 3504 3505 if (nlen < 19 3506 && (*op_end && 3507 (is_end_of_line[op_end[1]] 3508 || op_end[1] == ' ' || op_end[1] == '\t' 3509 || !ISALNUM (op_end[1]))) 3510 && (*op_end == 'a' || *op_end == 'b' 3511 || *op_end == 'A' || *op_end == 'B' 3512 || *op_end == 'd' || *op_end == 'D' 3513 || *op_end == 'x' || *op_end == 'X' 3514 || *op_end == 'y' || *op_end == 'Y')) 3515 { 3516 name[nlen++] = TOLOWER (*op_end++); 3517 name[nlen] = 0; 3518 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, 3519 name); 3520 } 3521 } 3522 } 3523 3524 /* Identify a possible instruction alias. There are some on the 3525 68HC12 to emulate a few 68HC11 instructions. */ 3526 if (opc == NULL && (current_architecture & cpu6812)) 3527 { 3528 int i; 3529 3530 for (i = 0; i < m68hc12_num_alias; i++) 3531 if (strcmp (m68hc12_alias[i].name, name) == 0) 3532 { 3533 alias_id = i; 3534 break; 3535 } 3536 } 3537 if (opc == NULL && alias_id < 0) 3538 { 3539 as_bad (_("Opcode `%s' is not recognized."), name); 3540 return; 3541 } 3542 save = input_line_pointer; 3543 input_line_pointer = (char *) op_end; 3544 3545 if (opc) 3546 { 3547 opc->used++; 3548 opcode = find_opcode (opc, operands, &nb_operands); 3549 } 3550 else 3551 opcode = 0; 3552 3553 if ((opcode || alias_id >= 0) && !flag_mri) 3554 { 3555 char *p = input_line_pointer; 3556 3557 while (*p == ' ' || *p == '\t' || *p == '\n' || *p == '\r') 3558 p++; 3559 3560 if (*p != '\n' && *p) 3561 as_bad (_("Garbage at end of instruction: `%s'."), p); 3562 } 3563 3564 input_line_pointer = save; 3565 3566 if (alias_id >= 0) 3567 { 3568 char *f = m68hc11_new_insn (m68hc12_alias[alias_id].size); 3569 3570 number_to_chars_bigendian (f, m68hc12_alias[alias_id].code1, 1); 3571 if (m68hc12_alias[alias_id].size > 1) 3572 number_to_chars_bigendian (f + 1, m68hc12_alias[alias_id].code2, 1); 3573 3574 return; 3575 } 3576 3577 /* Opcode is known but does not have valid operands. Print out the 3578 syntax for this opcode. */ 3579 if (opcode == 0) 3580 { 3581 if (flag_print_insn_syntax) 3582 print_insn_format (name); 3583 3584 if (((strcmp (name, "movb") == 0) || (strcmp (name, "movw") == 0)) 3585 && (current_architecture & cpu9s12x)) 3586 { 3587 char *f; 3588 int movb; 3589 if (strcmp (name, "movb") == 0) 3590 movb = 8; 3591 else 3592 movb = 0; 3593 3594 /* The existing operand extract code fell over if these additional modes 3595 were enabled in m68hc11-opc.c. So they are commented there and 3596 decoded here instead. */ 3597 3598 if (operands[1].mode & (M6812_OP_IDX | M6812_OP_IDX_1 3599 | M6812_OP_IDX_2 | M6812_OP_D_IDX | M6812_OP_D_IDX_2 | M6812_PRE_INC 3600 | M6812_PRE_DEC | M6812_POST_INC | M6812_POST_DEC )) 3601 { 3602 /* first check if valid mode then start building it up */ 3603 if (operands[0].mode & (M6811_OP_IMM8 | M6811_OP_IMM16 3604 | M6811_OP_IND16 | M6812_OP_IDX | M6812_OP_IDX_1 3605 | M6812_OP_IDX_2 | M6812_OP_D_IDX | M6812_OP_D_IDX_2)) 3606 { 3607 int opr16a; 3608 if (operands[1].mode & (M6811_OP_IND16)) 3609 opr16a = 3; 3610 else 3611 opr16a = 0; 3612 3613 f = m68hc11_new_insn (2); 3614 3615 if (operands[0].mode & (M6811_OP_IMM8 | M6811_OP_IMM16)) 3616 { 3617 number_to_chars_bigendian (f, 0x1800 + movb + opr16a, 2); 3618 build_indexed_byte (&operands[1], operands[1].mode, 1); 3619 if (movb) 3620 fixup8 (&operands[0].exp, M6811_OP_IMM8, 3621 operands[0].mode); 3622 else 3623 fixup16 (&operands[0].exp, M6811_OP_IMM16, 3624 operands[0].mode); 3625 3626 return; 3627 } 3628 else if (operands[0].mode & M6811_OP_IND16) 3629 { 3630 number_to_chars_bigendian (f, 0x1801 + movb + opr16a, 2); 3631 build_indexed_byte (&operands[1], operands[1].mode, 1); 3632 fixup16 (&operands[0].exp, M6811_OP_IND16, operands[0].mode); 3633 return; 3634 } 3635 else 3636 { 3637 number_to_chars_bigendian (f, 0x1802 + movb + opr16a, 2); 3638 build_indexed_byte (&operands[0], operands[0].mode, 1); 3639 build_indexed_byte (&operands[1], operands[1].mode, 1); 3640 return; 3641 } 3642 } 3643 } 3644 else if (operands[1].mode & M6811_OP_IND16) 3645 { 3646 /* First check if this is valid mode, then start building it up. */ 3647 if (operands[0].mode & (M6811_OP_IMM8 | M6811_OP_IMM16 3648 | M6811_OP_IND16 | M6812_OP_IDX | M6812_OP_IDX_1 3649 | M6812_OP_IDX_2 | M6812_OP_D_IDX | M6812_OP_D_IDX_2)) 3650 { 3651 int opr16a; 3652 if (operands[1].mode & (M6811_OP_IND16)) 3653 opr16a = 3; 3654 else 3655 opr16a = 0; 3656 3657 f = m68hc11_new_insn (2); 3658 3659 /* The first two cases here should actually be covered by the 3660 normal operand code. */ 3661 if (operands[0].mode & (M6811_OP_IMM8 | M6811_OP_IMM16)) 3662 { 3663 number_to_chars_bigendian (f, 0x1800 + movb + opr16a, 2); 3664 if (movb) 3665 fixup8 (&operands[0].exp, M6811_OP_IMM8, operands[0].mode); 3666 else 3667 fixup16 (&operands[0].exp, M6811_OP_IMM16, operands[0].mode); 3668 3669 fixup16 (&operands[0].exp, M6811_OP_IND16, operands[0].mode); 3670 return; 3671 } 3672 else if (operands[0].mode & M6811_OP_IND16) 3673 { 3674 number_to_chars_bigendian (f, 0x1801 + movb + opr16a, 2); 3675 build_indexed_byte (&operands[1], operands[1].mode, 1); 3676 fixup16 (&operands[0].exp, M6811_OP_IND16, operands[0].mode); 3677 return; 3678 } 3679 else 3680 { 3681 number_to_chars_bigendian (f, 0x1802 + movb + opr16a, 2); 3682 build_indexed_byte (&operands[0], operands[0].mode, 1); 3683 fixup16 (&operands[1].exp, M6811_OP_IND16, operands[1].mode); 3684 return; 3685 } 3686 } 3687 } 3688 3689 as_bad (_("Invalid operand for `%s'"), name); 3690 return; 3691 3692 } 3693 else 3694 { 3695 as_bad (_("Invalid operand for `%s'"), name); 3696 return; 3697 } 3698 } 3699 3700 /* Treat dbeq/ibeq/tbeq instructions in a special way. The branch is 3701 relative and must be in the range -256..255 (9-bits). */ 3702 if ((opcode->format & M6812_XBCC_MARKER) 3703 && (opcode->format & M6811_OP_JUMP_REL)) 3704 build_dbranch_insn (opcode, operands, nb_operands, branch_optimize); 3705 3706 /* Relative jumps instructions are taken care of separately. We have to make 3707 sure that the relative branch is within the range -128..127. If it's out 3708 of range, the instructions are changed into absolute instructions. 3709 This is not supported for the brset and brclr instructions. */ 3710 else if ((opcode->format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) 3711 && !(opcode->format & M6811_OP_BITMASK)) 3712 build_jump_insn (opcode, operands, nb_operands, branch_optimize); 3713 else 3714 build_insn (opcode, operands, nb_operands); 3715 } 3716 3717 3718 /* Pseudo op to control the ELF flags. */ 3720 static void 3721 s_m68hc11_mode (int x ATTRIBUTE_UNUSED) 3722 { 3723 char *name = input_line_pointer, ch; 3724 3725 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 3726 input_line_pointer++; 3727 ch = *input_line_pointer; 3728 *input_line_pointer = '\0'; 3729 3730 if (strcmp (name, "mshort") == 0) 3731 { 3732 elf_flags &= ~E_M68HC11_I32; 3733 } 3734 else if (strcmp (name, "mlong") == 0) 3735 { 3736 elf_flags |= E_M68HC11_I32; 3737 } 3738 else if (strcmp (name, "mshort-double") == 0) 3739 { 3740 elf_flags &= ~E_M68HC11_F64; 3741 } 3742 else if (strcmp (name, "mlong-double") == 0) 3743 { 3744 elf_flags |= E_M68HC11_F64; 3745 } 3746 else 3747 { 3748 as_warn (_("Invalid mode: %s\n"), name); 3749 } 3750 *input_line_pointer = ch; 3751 demand_empty_rest_of_line (); 3752 } 3753 3754 /* Mark the symbols with STO_M68HC12_FAR to indicate the functions 3755 are using 'rtc' for returning. It is necessary to use 'call' 3756 to invoke them. This is also used by the debugger to correctly 3757 find the stack frame. */ 3758 static void 3759 s_m68hc11_mark_symbol (int mark) 3760 { 3761 char *name; 3762 int c; 3763 symbolS *symbolP; 3764 asymbol *bfdsym; 3765 elf_symbol_type *elfsym; 3766 3767 do 3768 { 3769 c = get_symbol_name (&name); 3770 symbolP = symbol_find_or_make (name); 3771 (void) restore_line_pointer (c); 3772 3773 SKIP_WHITESPACE (); 3774 3775 bfdsym = symbol_get_bfdsym (symbolP); 3776 elfsym = elf_symbol_from (bfd_asymbol_bfd (bfdsym), bfdsym); 3777 3778 gas_assert (elfsym); 3779 3780 /* Mark the symbol far (using rtc for function return). */ 3781 elfsym->internal_elf_sym.st_other |= mark; 3782 3783 if (c == ',') 3784 { 3785 input_line_pointer ++; 3786 3787 SKIP_WHITESPACE (); 3788 3789 if (*input_line_pointer == '\n') 3790 c = '\n'; 3791 } 3792 } 3793 while (c == ','); 3794 3795 demand_empty_rest_of_line (); 3796 } 3797 3798 static void 3799 s_m68hc11_relax (int ignore ATTRIBUTE_UNUSED) 3800 { 3801 expressionS ex; 3802 3803 expression (&ex); 3804 3805 if (ex.X_op != O_symbol || ex.X_add_number != 0) 3806 { 3807 as_bad (_("bad .relax format")); 3808 ignore_rest_of_line (); 3809 return; 3810 } 3811 3812 fix_new_exp (frag_now, frag_now_fix (), 0, &ex, 1, 3813 BFD_RELOC_M68HC11_RL_GROUP); 3814 3815 demand_empty_rest_of_line (); 3816 } 3817 3818 3819 /* Relocation, relaxation and frag conversions. */ 3821 3822 /* PC-relative offsets are relative to the start of the 3823 next instruction. That is, the address of the offset, plus its 3824 size, since the offset is always the last part of the insn. */ 3825 long 3826 md_pcrel_from (fixS *fixP) 3827 { 3828 if (fixP->fx_r_type == BFD_RELOC_M68HC11_RL_JUMP) 3829 return 0; 3830 3831 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; 3832 } 3833 3834 /* If while processing a fixup, a reloc really needs to be created 3835 then it is done here. */ 3836 arelent * 3837 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 3838 { 3839 arelent *reloc; 3840 3841 reloc = XNEW (arelent); 3842 reloc->sym_ptr_ptr = XNEW (asymbol *); 3843 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 3844 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3845 if (fixp->fx_r_type == 0) 3846 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); 3847 else 3848 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); 3849 if (reloc->howto == (reloc_howto_type *) NULL) 3850 { 3851 as_bad_where (fixp->fx_file, fixp->fx_line, 3852 _("Relocation %d is not supported by object file format."), 3853 (int) fixp->fx_r_type); 3854 return NULL; 3855 } 3856 3857 /* Since we use Rel instead of Rela, encode the vtable entry to be 3858 used in the relocation's section offset. */ 3859 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 3860 reloc->address = fixp->fx_offset; 3861 3862 reloc->addend = 0; 3863 return reloc; 3864 } 3865 3866 /* We need a port-specific relaxation function to cope with sym2 - sym1 3867 relative expressions with both symbols in the same segment (but not 3868 necessarily in the same frag as this insn), for example: 3869 ldab sym2-(sym1-2),pc 3870 sym1: 3871 The offset can be 5, 9 or 16 bits long. */ 3872 3873 long 3874 m68hc11_relax_frag (segT seg ATTRIBUTE_UNUSED, fragS *fragP, 3875 long stretch ATTRIBUTE_UNUSED) 3876 { 3877 long growth; 3878 offsetT aim = 0; 3879 symbolS *symbolP; 3880 const relax_typeS *this_type; 3881 const relax_typeS *start_type; 3882 relax_substateT next_state; 3883 relax_substateT this_state; 3884 const relax_typeS *table = TC_GENERIC_RELAX_TABLE; 3885 3886 /* We only have to cope with frags as prepared by 3887 md_estimate_size_before_relax. The STATE_BITS16 case may geet here 3888 because of the different reasons that it's not relaxable. */ 3889 switch (fragP->fr_subtype) 3890 { 3891 case ENCODE_RELAX (STATE_INDEXED_PCREL, STATE_BITS16): 3892 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS16): 3893 /* When we get to this state, the frag won't grow any more. */ 3894 return 0; 3895 3896 case ENCODE_RELAX (STATE_INDEXED_PCREL, STATE_BITS5): 3897 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS5): 3898 case ENCODE_RELAX (STATE_INDEXED_PCREL, STATE_BITS9): 3899 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS9): 3900 if (fragP->fr_symbol == NULL 3901 || S_GET_SEGMENT (fragP->fr_symbol) != absolute_section) 3902 as_fatal (_("internal inconsistency problem in %s: fr_symbol %lx"), 3903 __FUNCTION__, (long) fragP->fr_symbol); 3904 symbolP = fragP->fr_symbol; 3905 if (symbol_resolved_p (symbolP)) 3906 as_fatal (_("internal inconsistency problem in %s: resolved symbol"), 3907 __FUNCTION__); 3908 aim = S_GET_VALUE (symbolP); 3909 break; 3910 3911 default: 3912 as_fatal (_("internal inconsistency problem in %s: fr_subtype %d"), 3913 __FUNCTION__, fragP->fr_subtype); 3914 } 3915 3916 /* The rest is stolen from relax_frag. There's no obvious way to 3917 share the code, but fortunately no requirement to keep in sync as 3918 long as fragP->fr_symbol does not have its segment changed. */ 3919 3920 this_state = fragP->fr_subtype; 3921 start_type = this_type = table + this_state; 3922 3923 if (aim < 0) 3924 { 3925 /* Look backwards. */ 3926 for (next_state = this_type->rlx_more; next_state;) 3927 if (aim >= this_type->rlx_backward) 3928 next_state = 0; 3929 else 3930 { 3931 /* Grow to next state. */ 3932 this_state = next_state; 3933 this_type = table + this_state; 3934 next_state = this_type->rlx_more; 3935 } 3936 } 3937 else 3938 { 3939 /* Look forwards. */ 3940 for (next_state = this_type->rlx_more; next_state;) 3941 if (aim <= this_type->rlx_forward) 3942 next_state = 0; 3943 else 3944 { 3945 /* Grow to next state. */ 3946 this_state = next_state; 3947 this_type = table + this_state; 3948 next_state = this_type->rlx_more; 3949 } 3950 } 3951 3952 growth = this_type->rlx_length - start_type->rlx_length; 3953 if (growth != 0) 3954 fragP->fr_subtype = this_state; 3955 return growth; 3956 } 3957 3958 void 3959 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, asection *sec ATTRIBUTE_UNUSED, 3960 fragS *fragP) 3961 { 3962 long value; 3963 long disp; 3964 char *buffer_address = fragP->fr_literal; 3965 3966 /* Address in object code of the displacement. */ 3967 int object_address = fragP->fr_fix + fragP->fr_address; 3968 3969 buffer_address += fragP->fr_fix; 3970 3971 /* The displacement of the address, from current location. */ 3972 value = S_GET_VALUE (fragP->fr_symbol); 3973 disp = (value + fragP->fr_offset) - object_address; 3974 3975 switch (fragP->fr_subtype) 3976 { 3977 case ENCODE_RELAX (STATE_PC_RELATIVE, STATE_BYTE): 3978 fragP->fr_opcode[1] = disp; 3979 break; 3980 3981 case ENCODE_RELAX (STATE_PC_RELATIVE, STATE_WORD): 3982 /* This relax is only for bsr and bra. */ 3983 gas_assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR) 3984 || IS_OPCODE (fragP->fr_opcode[0], M6811_BRA) 3985 || IS_OPCODE (fragP->fr_opcode[0], M6812_BSR)); 3986 3987 fragP->fr_opcode[0] = convert_branch (fragP->fr_opcode[0]); 3988 3989 fix_new (fragP, fragP->fr_fix - 1, 2, 3990 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16); 3991 fragP->fr_fix += 1; 3992 break; 3993 3994 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_BYTE): 3995 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_BYTE): 3996 fragP->fr_opcode[1] = disp; 3997 break; 3998 3999 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_WORD): 4000 /* Invert branch. */ 4001 fragP->fr_opcode[0] ^= 1; 4002 fragP->fr_opcode[1] = 3; /* Branch offset. */ 4003 buffer_address[0] = M6811_JMP; 4004 fix_new (fragP, fragP->fr_fix + 1, 2, 4005 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16); 4006 fragP->fr_fix += 3; 4007 break; 4008 4009 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_WORD): 4010 /* Translate branch into a long branch. */ 4011 fragP->fr_opcode[1] = fragP->fr_opcode[0]; 4012 fragP->fr_opcode[0] = M6811_OPCODE_PAGE2; 4013 4014 fix_new (fragP, fragP->fr_fix, 2, 4015 fragP->fr_symbol, fragP->fr_offset, 1, 4016 BFD_RELOC_16_PCREL); 4017 fragP->fr_fix += 2; 4018 break; 4019 4020 case ENCODE_RELAX (STATE_INDEXED_PCREL, STATE_BITS5): 4021 if (fragP->fr_symbol != 0 4022 && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section) 4023 value = disp; 4024 /* fall through */ 4025 4026 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS5): 4027 fragP->fr_opcode[0] = fragP->fr_opcode[0] << 6; 4028 fragP->fr_opcode[0] |= value & 0x1f; 4029 break; 4030 4031 case ENCODE_RELAX (STATE_INDEXED_PCREL, STATE_BITS9): 4032 /* For a PC-relative offset, use the displacement with a -1 correction 4033 to take into account the additional byte of the insn. */ 4034 if (fragP->fr_symbol != 0 4035 && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section) 4036 value = disp - 1; 4037 /* fall through */ 4038 4039 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS9): 4040 fragP->fr_opcode[0] = (fragP->fr_opcode[0] << 3); 4041 fragP->fr_opcode[0] |= 0xE0; 4042 fragP->fr_opcode[0] |= (value >> 8) & 1; 4043 fragP->fr_opcode[1] = value; 4044 fragP->fr_fix += 1; 4045 break; 4046 4047 case ENCODE_RELAX (STATE_INDEXED_PCREL, STATE_BITS16): 4048 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS16): 4049 fragP->fr_opcode[0] = (fragP->fr_opcode[0] << 3); 4050 fragP->fr_opcode[0] |= 0xe2; 4051 if ((fragP->fr_opcode[0] & 0x0ff) == 0x0fa 4052 && fragP->fr_symbol != 0 4053 && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section) 4054 { 4055 fix_new (fragP, fragP->fr_fix, 2, 4056 fragP->fr_symbol, fragP->fr_offset, 4057 1, BFD_RELOC_16_PCREL); 4058 } 4059 else 4060 { 4061 fix_new (fragP, fragP->fr_fix, 2, 4062 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16); 4063 } 4064 fragP->fr_fix += 2; 4065 break; 4066 4067 case ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_BYTE): 4068 if (disp < 0) 4069 fragP->fr_opcode[0] |= 0x10; 4070 4071 fragP->fr_opcode[1] = disp & 0x0FF; 4072 break; 4073 4074 case ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_WORD): 4075 /* Invert branch. */ 4076 fragP->fr_opcode[0] ^= 0x20; 4077 fragP->fr_opcode[1] = 3; /* Branch offset. */ 4078 buffer_address[0] = M6812_JMP; 4079 fix_new (fragP, fragP->fr_fix + 1, 2, 4080 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16); 4081 fragP->fr_fix += 3; 4082 break; 4083 4084 default: 4085 break; 4086 } 4087 } 4088 4089 /* On an ELF system, we can't relax a weak symbol. The weak symbol 4090 can be overridden at final link time by a non weak symbol. We can 4091 relax externally visible symbol because there is no shared library 4092 and such symbol can't be overridden (unless they are weak). */ 4093 static int 4094 relaxable_symbol (symbolS *symbol) 4095 { 4096 return ! S_IS_WEAK (symbol); 4097 } 4098 4099 /* Force truly undefined symbols to their maximum size, and generally set up 4100 the frag list to be relaxed. */ 4101 int 4102 md_estimate_size_before_relax (fragS *fragP, asection *segment) 4103 { 4104 if (RELAX_LENGTH (fragP->fr_subtype) == STATE_UNDF) 4105 { 4106 if (S_GET_SEGMENT (fragP->fr_symbol) != segment 4107 || !relaxable_symbol (fragP->fr_symbol) 4108 || (segment != absolute_section 4109 && RELAX_STATE (fragP->fr_subtype) == STATE_INDEXED_OFFSET)) 4110 { 4111 /* Non-relaxable cases. */ 4112 int old_fr_fix; 4113 char *buffer_address; 4114 4115 old_fr_fix = fragP->fr_fix; 4116 buffer_address = fragP->fr_fix + fragP->fr_literal; 4117 4118 switch (RELAX_STATE (fragP->fr_subtype)) 4119 { 4120 case STATE_PC_RELATIVE: 4121 4122 /* This relax is only for bsr and bra. */ 4123 gas_assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR) 4124 || IS_OPCODE (fragP->fr_opcode[0], M6811_BRA) 4125 || IS_OPCODE (fragP->fr_opcode[0], M6812_BSR)); 4126 4127 if (flag_fixed_branches) 4128 as_bad_where (fragP->fr_file, fragP->fr_line, 4129 _("bra or bsr with undefined symbol.")); 4130 4131 /* The symbol is undefined or in a separate section. 4132 Turn bra into a jmp and bsr into a jsr. The insn 4133 becomes 3 bytes long (instead of 2). A fixup is 4134 necessary for the unresolved symbol address. */ 4135 fragP->fr_opcode[0] = convert_branch (fragP->fr_opcode[0]); 4136 4137 fix_new (fragP, fragP->fr_fix - 1, 2, fragP->fr_symbol, 4138 fragP->fr_offset, 0, BFD_RELOC_16); 4139 fragP->fr_fix++; 4140 break; 4141 4142 case STATE_CONDITIONAL_BRANCH: 4143 gas_assert (current_architecture & cpu6811); 4144 4145 fragP->fr_opcode[0] ^= 1; /* Reverse sense of branch. */ 4146 fragP->fr_opcode[1] = 3; /* Skip next jmp insn (3 bytes). */ 4147 4148 /* Don't use fr_opcode[2] because this may be 4149 in a different frag. */ 4150 buffer_address[0] = M6811_JMP; 4151 4152 fragP->fr_fix++; 4153 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 4154 fragP->fr_offset, 0, BFD_RELOC_16); 4155 fragP->fr_fix += 2; 4156 break; 4157 4158 case STATE_INDEXED_OFFSET: 4159 gas_assert (current_architecture & cpu6812); 4160 4161 if (fragP->fr_symbol 4162 && S_GET_SEGMENT (fragP->fr_symbol) == absolute_section) 4163 { 4164 fragP->fr_subtype = ENCODE_RELAX (STATE_INDEXED_OFFSET, 4165 STATE_BITS5); 4166 /* Return the size of the variable part of the frag. */ 4167 return md_relax_table[fragP->fr_subtype].rlx_length; 4168 } 4169 else 4170 { 4171 /* Switch the indexed operation to 16-bit mode. */ 4172 fragP->fr_opcode[0] = fragP->fr_opcode[0] << 3; 4173 fragP->fr_opcode[0] |= 0xe2; 4174 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 4175 fragP->fr_offset, 0, BFD_RELOC_16); 4176 fragP->fr_fix += 2; 4177 } 4178 break; 4179 4180 case STATE_INDEXED_PCREL: 4181 gas_assert (current_architecture & cpu6812); 4182 4183 if (fragP->fr_symbol 4184 && S_GET_SEGMENT (fragP->fr_symbol) == absolute_section) 4185 { 4186 fragP->fr_subtype = ENCODE_RELAX (STATE_INDEXED_PCREL, 4187 STATE_BITS5); 4188 /* Return the size of the variable part of the frag. */ 4189 return md_relax_table[fragP->fr_subtype].rlx_length; 4190 } 4191 else 4192 { 4193 fragP->fr_opcode[0] = fragP->fr_opcode[0] << 3; 4194 fragP->fr_opcode[0] |= 0xe2; 4195 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 4196 fragP->fr_offset, 1, BFD_RELOC_16_PCREL); 4197 fragP->fr_fix += 2; 4198 } 4199 break; 4200 4201 case STATE_XBCC_BRANCH: 4202 gas_assert (current_architecture & cpu6812); 4203 4204 fragP->fr_opcode[0] ^= 0x20; /* Reverse sense of branch. */ 4205 fragP->fr_opcode[1] = 3; /* Skip next jmp insn (3 bytes). */ 4206 4207 /* Don't use fr_opcode[2] because this may be 4208 in a different frag. */ 4209 buffer_address[0] = M6812_JMP; 4210 4211 fragP->fr_fix++; 4212 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 4213 fragP->fr_offset, 0, BFD_RELOC_16); 4214 fragP->fr_fix += 2; 4215 break; 4216 4217 case STATE_CONDITIONAL_BRANCH_6812: 4218 gas_assert (current_architecture & cpu6812); 4219 4220 /* Translate into a lbcc branch. */ 4221 fragP->fr_opcode[1] = fragP->fr_opcode[0]; 4222 fragP->fr_opcode[0] = M6811_OPCODE_PAGE2; 4223 4224 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 4225 fragP->fr_offset, 1, BFD_RELOC_16_PCREL); 4226 fragP->fr_fix += 2; 4227 break; 4228 4229 default: 4230 as_fatal (_("Subtype %d is not recognized."), fragP->fr_subtype); 4231 } 4232 frag_wane (fragP); 4233 4234 /* Return the growth in the fixed part of the frag. */ 4235 return fragP->fr_fix - old_fr_fix; 4236 } 4237 4238 /* Relaxable cases. */ 4239 switch (RELAX_STATE (fragP->fr_subtype)) 4240 { 4241 case STATE_PC_RELATIVE: 4242 /* This relax is only for bsr and bra. */ 4243 gas_assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR) 4244 || IS_OPCODE (fragP->fr_opcode[0], M6811_BRA) 4245 || IS_OPCODE (fragP->fr_opcode[0], M6812_BSR)); 4246 4247 fragP->fr_subtype = ENCODE_RELAX (STATE_PC_RELATIVE, STATE_BYTE); 4248 break; 4249 4250 case STATE_CONDITIONAL_BRANCH: 4251 gas_assert (current_architecture & cpu6811); 4252 4253 fragP->fr_subtype = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, 4254 STATE_BYTE); 4255 break; 4256 4257 case STATE_INDEXED_OFFSET: 4258 gas_assert (current_architecture & cpu6812); 4259 4260 fragP->fr_subtype = ENCODE_RELAX (STATE_INDEXED_OFFSET, 4261 STATE_BITS5); 4262 break; 4263 4264 case STATE_INDEXED_PCREL: 4265 gas_assert (current_architecture & cpu6812); 4266 4267 fragP->fr_subtype = ENCODE_RELAX (STATE_INDEXED_PCREL, 4268 STATE_BITS5); 4269 break; 4270 4271 case STATE_XBCC_BRANCH: 4272 gas_assert (current_architecture & cpu6812); 4273 4274 fragP->fr_subtype = ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_BYTE); 4275 break; 4276 4277 case STATE_CONDITIONAL_BRANCH_6812: 4278 gas_assert (current_architecture & cpu6812); 4279 4280 fragP->fr_subtype = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, 4281 STATE_BYTE); 4282 break; 4283 } 4284 } 4285 4286 if (fragP->fr_subtype >= sizeof (md_relax_table) / sizeof (md_relax_table[0])) 4287 as_fatal (_("Subtype %d is not recognized."), fragP->fr_subtype); 4288 4289 /* Return the size of the variable part of the frag. */ 4290 return md_relax_table[fragP->fr_subtype].rlx_length; 4291 } 4292 4293 /* See whether we need to force a relocation into the output file. */ 4294 int 4295 tc_m68hc11_force_relocation (fixS *fixP) 4296 { 4297 if (fixP->fx_r_type == BFD_RELOC_M68HC11_RL_GROUP) 4298 return 1; 4299 4300 return generic_force_reloc (fixP); 4301 } 4302 4303 /* Here we decide which fixups can be adjusted to make them relative 4304 to the beginning of the section instead of the symbol. Basically 4305 we need to make sure that the linker relaxation is done 4306 correctly, so in some cases we force the original symbol to be 4307 used. */ 4308 int 4309 tc_m68hc11_fix_adjustable (fixS *fixP) 4310 { 4311 switch (fixP->fx_r_type) 4312 { 4313 /* For the linker relaxation to work correctly, these relocs 4314 need to be on the symbol itself. */ 4315 case BFD_RELOC_16: 4316 case BFD_RELOC_M68HC11_RL_JUMP: 4317 case BFD_RELOC_M68HC11_RL_GROUP: 4318 case BFD_RELOC_VTABLE_INHERIT: 4319 case BFD_RELOC_VTABLE_ENTRY: 4320 case BFD_RELOC_32: 4321 4322 /* The memory bank addressing translation also needs the original 4323 symbol. */ 4324 case BFD_RELOC_M68HC11_LO16: 4325 case BFD_RELOC_M68HC11_PAGE: 4326 case BFD_RELOC_M68HC11_24: 4327 return 0; 4328 4329 default: 4330 return 1; 4331 } 4332 } 4333 4334 void 4335 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 4336 { 4337 char *where; 4338 long value = * valP; 4339 4340 if (fixP->fx_addsy == (symbolS *) NULL) 4341 fixP->fx_done = 1; 4342 4343 /* We don't actually support subtracting a symbol. */ 4344 if (fixP->fx_subsy != (symbolS *) NULL) 4345 as_bad_where (fixP->fx_file, fixP->fx_line, _("Expression too complex.")); 4346 4347 /* Patch the instruction with the resolved operand. Elf relocation 4348 info will also be generated to take care of linker/loader fixups. 4349 The 68HC11 addresses only 64Kb, we are only concerned by 8 and 16-bit 4350 relocs. BFD_RELOC_8 is basically used for .page0 access (the linker 4351 will warn for overflows). BFD_RELOC_8_PCREL should not be generated 4352 because it's either resolved or turned out into non-relative insns (see 4353 relax table, bcc, bra, bsr transformations) 4354 4355 The BFD_RELOC_32 is necessary for the support of --gstabs. */ 4356 where = fixP->fx_frag->fr_literal + fixP->fx_where; 4357 4358 switch (fixP->fx_r_type) 4359 { 4360 case BFD_RELOC_32: 4361 bfd_putb32 ((bfd_vma) value, (unsigned char *) where); 4362 break; 4363 4364 case BFD_RELOC_24: 4365 case BFD_RELOC_M68HC11_24: 4366 bfd_putb16 ((bfd_vma) (value & 0x0ffff), (unsigned char *) where); 4367 ((bfd_byte*) where)[2] = ((value >> 16) & 0x0ff); 4368 break; 4369 4370 case BFD_RELOC_16: 4371 case BFD_RELOC_16_PCREL: 4372 case BFD_RELOC_M68HC11_LO16: 4373 bfd_putb16 ((bfd_vma) value, (unsigned char *) where); 4374 if (value < -65537 || value > 65535) 4375 as_bad_where (fixP->fx_file, fixP->fx_line, 4376 _("Value out of 16-bit range.")); 4377 break; 4378 4379 case BFD_RELOC_M68HC11_HI8: 4380 /* Caution, %hi(<symbol>+%ld) will generate incorrect code if %lo 4381 causes a carry. */ 4382 case BFD_RELOC_M68HC12_HI8XG: 4383 value = value >> 8; 4384 /* Fall through. */ 4385 4386 case BFD_RELOC_M68HC12_LO8XG: 4387 case BFD_RELOC_M68HC11_LO8: 4388 case BFD_RELOC_8: 4389 case BFD_RELOC_M68HC11_PAGE: 4390 ((bfd_byte *) where)[0] = (bfd_byte) value; 4391 break; 4392 4393 case BFD_RELOC_8_PCREL: 4394 ((bfd_byte *) where)[0] = (bfd_byte) value; 4395 4396 if (value < -128 || value > 127) 4397 as_bad_where (fixP->fx_file, fixP->fx_line, 4398 _("Value %ld too large for 8-bit PC-relative branch."), 4399 value); 4400 break; 4401 4402 /* These next two are for XGATE. */ 4403 case BFD_RELOC_M68HC12_9_PCREL: 4404 ((bfd_byte *) where)[0] |= (bfd_byte) ((value >>9) & 0x01); 4405 ((bfd_byte *) where)[1] = (bfd_byte) ((value>>1) & 0xff); 4406 if (value < -512 || value > 511) 4407 as_bad_where (fixP->fx_file, fixP->fx_line, 4408 _("Value %ld too large for 9-bit PC-relative branch."), 4409 value); 4410 break; 4411 4412 case BFD_RELOC_M68HC12_10_PCREL: 4413 ((bfd_byte *) where)[0] |= (bfd_byte) ((value >>9) & 0x03); 4414 ((bfd_byte *) where)[1] = (bfd_byte) ((value>>1) & 0xff); 4415 if (value < -1024 || value > 1023) 4416 as_bad_where (fixP->fx_file, fixP->fx_line, 4417 _("Value %ld too large for 10-bit PC-relative branch."), 4418 value); 4419 4420 break; 4421 4422 case BFD_RELOC_M68HC11_3B: 4423 if (value <= 0 || value > 8) 4424 as_bad_where (fixP->fx_file, fixP->fx_line, 4425 _("Auto increment/decrement offset '%ld' is out of range."), 4426 value); 4427 if (where[0] & 0x8) 4428 value = 8 - value; 4429 else 4430 value--; 4431 4432 where[0] = where[0] | (value & 0x07); 4433 break; 4434 4435 case BFD_RELOC_M68HC12_5B: 4436 if (value < -16 || value > 15) 4437 as_bad_where (fixP->fx_file, fixP->fx_line, 4438 _("Offset out of 5-bit range for movw/movb insn: %ld"), 4439 value); 4440 if (value >= 0) 4441 where[0] |= value; 4442 else 4443 where[0] |= (0x10 | (16 + value)); 4444 break; 4445 4446 case BFD_RELOC_M68HC12_9B: 4447 if (value < -256 || value > 255) 4448 as_bad_where (fixP->fx_file, fixP->fx_line, 4449 _("Offset out of 9-bit range for movw/movb insn: %ld"), 4450 value); 4451 /* sign bit already in xb postbyte */ 4452 if (value >= 0) 4453 where[1] = value; 4454 else 4455 where[1] = (256 + value); 4456 break; 4457 4458 case BFD_RELOC_M68HC12_16B: 4459 if (value < -32768 || value > 32767) 4460 as_bad_where (fixP->fx_file, fixP->fx_line, 4461 _("Offset out of 16-bit range for movw/movb insn: %ld"), 4462 value); 4463 if (value < 0) 4464 value += 65536; 4465 4466 where[0] = (value >> 8); 4467 where[1] = (value & 0xff); 4468 break; 4469 4470 case BFD_RELOC_M68HC11_RL_JUMP: 4471 case BFD_RELOC_M68HC11_RL_GROUP: 4472 case BFD_RELOC_VTABLE_INHERIT: 4473 case BFD_RELOC_VTABLE_ENTRY: 4474 fixP->fx_done = 0; 4475 return; 4476 4477 default: 4478 as_fatal (_("Line %d: unknown relocation type: 0x%x."), 4479 fixP->fx_line, fixP->fx_r_type); 4480 } 4481 } 4482 4483 /* Set the ELF specific flags. */ 4484 void 4485 m68hc11_elf_final_processing (void) 4486 { 4487 if (current_architecture & cpu6812s) 4488 elf_flags |= EF_M68HCS12_MACH; 4489 elf_elfheader (stdoutput)->e_flags &= ~EF_M68HC11_ABI; 4490 elf_elfheader (stdoutput)->e_flags |= elf_flags; 4491 } 4492 4493 /* Process directives specified via pseudo ops */ 4494 static void 4495 s_m68hc11_parse_pseudo_instruction (int pseudo_insn) 4496 { 4497 switch (pseudo_insn) 4498 { 4499 case E_M68HC11_NO_BANK_WARNING: 4500 elf_flags |= E_M68HC11_NO_BANK_WARNING; 4501 break; 4502 default: 4503 as_bad (_("Invalid directive")); 4504 } 4505 } 4506