| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/mips/ |
| mips32r2-fp32.l | 2 .*:12: Error: opcode not supported on this processor: .* \(.*\) `mfhc1 \$17,\$f0'
|
| mips32r2-fp32.d | 10 0+0000 <[^>]*> 44710000 mfhc1 \$17,\$f0
|
| mips32r2-fp32.s | 12 mfhc1 $17, $f0
|
| micromips@mips32r2-fp32.d | 11 [0-9a-f]+ <[^>]*> 5620 303b mfhc1 \$17,\$f0
|
| mips32r2-ill-fp64.s | 53 mfhc1 $17, $f0
54 mfhc1 $17, $f1
|
| mips32r2-ill.s | 53 mfhc1 $17, $f0
54 mfhc1 $17, $f1 # warn
|
| mipsr6@mips32r2-ill.s | 53 mfhc1 $17, $f0
|
| micromips.s | [all...] |
| micromips-insn32.d | [all...] |
| micromips-noinsn32.d | [all...] |
| micromips-trap.d | [all...] |
| micromips.d | [all...] |
| /art/runtime/arch/mips/ |
| asm_support_mips.S | 82 mfhc1 \temp, \feven
|
| /art/runtime/interpreter/mterp/mips/ |
| header.S | 408 mfhc1 AT, rlo; \
423 mfhc1 AT, rlo; \
555 mfhc1 AT, rlo; \
574 mfhc1 AT, rlo; \
645 mfhc1 AT, rlo; \
|
| /external/llvm/test/MC/Mips/mips32/ |
| invalid-mips32r2.s | 19 mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips4/ |
| invalid-mips64r2.s | 23 mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips5/ |
| invalid-mips64r2.s | 27 mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64/ |
| invalid-mips64r2.s | 23 mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /art/runtime/interpreter/mterp/mips64/ |
| header.S | 302 mfhc1 \vreg, \reg
|
| /external/llvm/test/MC/Mips/ |
| micromips-fpu-instructions.s | 56 # CHECK-EL: mfhc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x30]
121 # CHECK-EB: mfhc1 $6, $f8 # encoding: [0x54,0xc8,0x30,0x3b]
182 mfhc1 $6, $f8
|
| mips-fpu-instructions.s | 172 # CHECK: mfhc1 $17, $f4 # encoding: [0x00,0x20,0x71,0x44]
207 mfhc1 $17, $f4
|
| /external/capstone/suite/MC/Mips/ |
| mips-fpu-instructions.s.cs | 88 0x00,0x20,0x71,0x44 = mfhc1 $17, $f4
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips32r2.s | 30 mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/v8/src/crankshaft/mips64/ |
| lithium-codegen-mips64.cc | [all...] |
| /external/llvm/test/MC/Mips/micromips32r6/ |
| valid.s | 310 mfhc1 $zero, $f6 # CHECK: mfhc1 $zero, $f6 # encoding: [0x54,0x06,0x30,0x3b]
[all...] |
