| /external/llvm/test/MC/Mips/ |
| mips-coprocessor-encodings.s | 6 # MIPS64: mtc0 $12, $16, 2 # encoding: [0x40,0x8c,0x80,0x02]
7 # MIPS64: mtc0 $12, $16, 0 # encoding: [0x40,0x8c,0x80,0x00]
15 mtc0 $12, $16, 2
16 mtc0 $12, $16
|
| mips-fpu-instructions.s | 156 # CHECK: mtc0 $9, $8, 0 # encoding: [0x00,0x40,0x89,0x40]
160 # CHECK: mtc0 $9, $8, 3 # encoding: [0x03,0x40,0x89,0x40]
191 mtc0 $9, $8
195 mtc0 $9, $8, 3
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/mips/ |
| octeon.s | 41 mtc0 $6,$2
42 mtc0 $21,$9,6
|
| octeon.d | 40 .*: 40861000 mtc0 \$6,\$2
41 .*: 40954806 mtc0 \$21,\$9,6
|
| micromips.s | 1364 mtc0 $2, $0
1365 mtc0 $2, $1
1366 mtc0 $2, $2
1367 mtc0 $2, $3
1368 mtc0 $2, $4
1369 mtc0 $2, $5
1370 mtc0 $2, $6
1371 mtc0 $2, $7
1372 mtc0 $2, $8
1373 mtc0 $2, $
[all...] |
| set-arch.d | 260 000003f0 <[^>]*> 4084c803 mtc0 a0,c0_perfcnt,3
261 000003f4 <[^>]*> 4084c802 mtc0 a0,c0_perfcnt,2
|
| micromips-insn32.d | [all...] |
| micromips-noinsn32.d | [all...] |
| micromips-trap.d | [all...] |
| micromips.d | [all...] |
| /external/llvm/test/MC/Mips/mips5/ |
| invalid-mips64.s | 23 mtc0 $9,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips64r2.s | 30 mtc0 $9,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/iq2000/ |
| allinsn.s | 380 .global mtc0
381 mtc0: label
382 mtc0 %0,%0
|
| allinsn.d | 289 00000178 <mtc0>:
290 178: 40 80 00 00 mtc0 r0,r0
|
| /external/capstone/suite/MC/Mips/ |
| mips-fpu-instructions.s.cs | 72 0x00,0x40,0x89,0x40 = mtc0 $9, $8, 0
76 0x03,0x40,0x89,0x40 = mtc0 $9, $8, 3
|
| /external/llvm/test/MC/Mips/mips4/ |
| invalid-mips64.s | 22 mtc0 $t1,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips64r2.s | 26 mtc0 $t1,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips32.s | 41 mtc0 $9,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips32r2.s | 52 mtc0 $t1,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| valid.s | 193 mtc0 $5, $9 # CHECK: mtc0 $5, $9, 0 # encoding: [0x00,0xa9,0x02,0xfc]
194 mtc0 $1, $2, 7 # CHECK: mtc0 $1, $2, 7 # encoding: [0x00,0x22,0x3a,0xfc]
|
| /external/llvm/test/MC/Mips/micromips32r6/ |
| valid.s | 296 mtc0 $5, $9 # CHECK: mtc0 $5, $9, 0 # encoding: [0x00,0xa9,0x02,0xfc]
297 mtc0 $1, $2, 7 # CHECK: mtc0 $1, $2, 7 # encoding: [0x00,0x22,0x3a,0xfc]
[all...] |
| /external/llvm/test/MC/Mips/mips32/ |
| valid.s | 116 mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01]
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| valid.s | 133 mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01]
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| valid.s | 133 mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01]
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| valid.s | 134 mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01]
|
